--modified by Peter Onaka
--  This is the top level of the control chip for the counter Board.
--
--*************************************************************
--  Revision history
--
--  Date		Rev	Eng				Description
--  --------	---	--------------	----------------------  
--	11/30/02	1	RY				Initial File
--  12/24/02	2	PMO				changed tristate signals
--  12/27/02	3	PMO				added bp_reset to c6
--	01/02/03	4	RY				changed unused Control lines to highZ instead of driving '0' and 
--									commented out debug lines
--	01/02/03	5	RY				swapped pins 42 and 43 in the control file because they are switched
--									on the board.
--	01/02/03	6	RY				Changed polarity of clock for outputing address to counter chips.
--									Counter chips clock Address in on rising edge so adress should be 
--									clocked out on falling edge.

library IEEE;
use IEEE.std_logic_1164.all; 
use IEEE.std_logic_unsigned.all;

entity Control_Top is
	port(
      	LED : 				out std_logic_vector(3 downto 1);
		SYSCLK:				in STD_LOGIC;
	 	-- 
      	-- backplane data bus and associated control signal
      	--
      	BPADDR: 			in std_logic_vector(7 downto 0);
     	BPCTRL: 			in std_logic_vector(15 downto 0);
      	BPD: 				out std_logic_vector(15 downto 0);
		BPD_L_TRISTATE:		out std_logic;
		BPD_H_TRISTATE:		out std_logic;
  		bpd_h_dir: 			out std_logic;
      	bpd_l_dir: 			out std_logic;
      	bpaddr_dir: 		out std_logic;
      	bpaddr_tristate:	out std_logic;
      	bpctrl_h_dir: 		out std_logic;
      	bpctrl_l_dir: 		out std_logic;
      	bpctrl_h_tristate: 	out std_logic;
      	bpctrl_l_tristate: 	out std_logic;
      	SW: 				in std_logic_vector(7 downto 0);
      	--
      	-- internal bus
      	--
      	D: 					in std_logic_vector(15 downto 0);
      	C: 					out std_logic_vector(15 downto 0)
	);
end Control_Top;

architecture Control_Top of Control_Top is 
	signal Addr_rising:		STD_LOGIC_VECTOR(7 downto 0); -- stores the address at the rising edge of clock
	signal Addr_Valid:		STD_LOGIC; -- Address is stable for 2 consectutive clock edges
	signal Addr_Good:		STD_LOGIC; -- Address is on board
begin
	-- constant signals
  	C(15 downto 8)  <= (others => 'Z');
  	bpd_h_dir <= '0';
  	bpd_l_dir <= '0';
  	bpaddr_dir <= '1';
  	bpaddr_tristate <= '0';
  	bpctrl_h_dir <= '0';
  	bpctrl_l_dir <= '1';
  	bpctrl_h_tristate <= '1';
  	bpctrl_l_tristate <= '0';
	LED <= "000";

	-- validate back plane address
	valid_Addr : process(SYSCLK, Addr_rising, BPADDR)
	begin
		-- Store BP adress at rising clock edge for comparison to BP address at falling clock edge
		-- Create half clock cycle delayed version of Addr_Valid
		if (SYSCLK'event and SYSCLK = '1') then
			Addr_rising <= BPADDR(7 downto 0);
			if (Addr_rising = BPADDR) then
				Addr_Valid <= '1';
			else
				Addr_Valid <= '0';
			end if;
		end if;
		-- check if BP address is stable on falling clock edge
--		if (SYSCLK'event and SYSCLK = '0') then
--			-- if BP adress is stable then Addr_Valid = '1'
--			if (Addr_rising = BPADDR) then 
--				Addr_Valid <= '1';
--			-- if BP address is NOT stable then Addr_Valid = '0'
--	 		else
--				Addr_Valid <= '0';
--			end if;
--		end if;
	end process;

	-- drive BP_Tristates when Address is valid and Upper Address matches SW[7:5]
	-- Create Output Enable signal for Counter chips
	control7 : process (Addr_Valid, Addr_Good)
	begin
		if (Addr_Valid = '1') and (Addr_Good = '1') then
--			C(7) <= '1';
			BPD_L_TRISTATE <=  '0';-- was'1';
			BPD_H_TRISTATE <= '0';-- was '1';
		else
--			C(7) <= '0';
			BPD_L_TRISTATE <=  '1'; --was '0';
			BPD_H_TRISTATE <= '1'; --was '0';
		end if;
	end process;
-- DEBUG --
	C(7) <= '0';
--	C(8) <= Addr_Valid;
--	C(9) <= Addr_Good;	
-- END DEBUG --
-- missing reset signal PMO
	C(6) <= BPCTRL(3);
	-- Pass Data and phase directly out
	BPD(15 downto 0) <= D(15 downto 0);
	C(0) <= BPCTRL(1);

	-- pass BP address to counter chips and set Addr_Good = '1' if it matches SW
	-- else pass all ones and set Addr_Good = '0'
	board_addr : process(SYSCLK, BPADDR, SW)
	begin 
		if (SYSCLK'event and SYSCLK = '0') then
			-- if BP address is on board then set address bits to BPAddr and Addr_Good = '1'
			if (BPADDR(7 downto 5) = SW(7 downto 5)) then
		 		C(5 downto 1) <= BPADDR(4 downto 0);
				Addr_Good <= '1';
			-- if BP address is not on board then set address bits to all ones and Addr_Good = '0'
	   		else 
				C(5 downto 1) <= "11111";
				Addr_Good <= '0';
			end if;
		end if;
	end process;


end Control_Top;