--
--  This is a 16-bit asynchronous counter w/ count enable and reset
--
--	***************************************************************
--  Revision history
--
--  Date		Rev	Eng				Description
--  --------	---	--------------	----------------------  
--	12/16/02	1	RY				Initial File
--	1/3/03		2	PMO				change counter 13bit to fit
--	1/6/03		3	PMO				sync counter

library IEEE;
use IEEE.std_logic_1164.all; 
use IEEE.std_logic_unsigned.all;

entity sync_Counter is
	port (	
		RESET:		in STD_LOGIC;
		COUNT_EN:	in STD_LOGIC;
		D_IN:	in STD_LOGIC;
		clk:	in STD_LOGIC;
--		COUNT_OUT:	out STD_LOGIC_VECTOR(13 downto 0)
		COUNT_OUT:	out STD_LOGIC_VECTOR(14 downto 0)
		);
end sync_Counter;

architecture sync_Counter of sync_Counter is 
--	 signal TempCount:	STD_LOGIC_VECTOR(13 downto 0);
-- signal TempCount:	STD_LOGIC_VECTOR(11 downto 0);
begin
	count : process (clk,D_IN, COUNT_EN, RESET)
	begin
		if ((RESET = '1')) then 
		COUNT_OUT	<= (others => '0');
--		TempCount	<= (others => '0');
		elsif (clk'event and clk = '1') then
--		elsif (D_IN'event and D_IN = '1') then
			if (COUNT_EN = '1' and D_IN = '1') then 
--				TempCount	<= TempCount + 1;
				COUNT_OUT	<= 	COUNT_OUT +1;
			end if;
		end if;
	end process;

--	COUNT_OUT <= TempCount;
end sync_Counter;