-- -- Pulse Generator -- This is a test chip for the Counter boards. It creates 1 pulse -- every X clock pulses. Where X is the value that read from the -- C[7:0]. Note: value is a binary value -- -- *************************************************************** -- Revision history -- -- Date Rev Eng Description -- -------- --- -------------- ---------------------- -- 01/13/02 1 RY Initial File -- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity PulseGenControl is port( LED : out std_logic_vector(3 downto 1); SYSCLK: in STD_LOGIC; -- -- backplane data bus and associated control signal -- -- BPADDR: in std_logic_vector(7 downto 0); BPCTRL: in std_logic_vector(8 downto 0); -- BPCTRL: in std_logic_vector(15 downto 0); -- BPD: out std_logic_vector(15 downto 0); BPD_L_TRISTATE: out std_logic; BPD_H_TRISTATE: out std_logic; bpd_h_dir: out std_logic; bpd_l_dir: out std_logic; bpaddr_dir: out std_logic; bpaddr_tristate: out std_logic; bpctrl_h_dir: out std_logic; bpctrl_l_dir: out std_logic; bpctrl_h_tristate: out std_logic; bpctrl_l_tristate: out std_logic; SW: in std_logic_vector(7 downto 0); -- -- internal bus -- -- D: in std_logic_vector(15 downto 0); C: out std_logic_vector(15 downto 0) ); end PulseGenControl; architecture PulseGenControl of PulseGenControl is begin -- constant signals C(15 downto 9) <= (others => 'Z'); bpd_h_dir <= '0'; bpd_l_dir <= '0'; bpaddr_dir <= '1'; bpaddr_tristate <= '0'; bpctrl_h_dir <= '0'; bpctrl_l_dir <= '1'; bpctrl_h_tristate <= '1'; bpctrl_l_tristate <= '0'; BPD_L_TRISTATE <= '1'; BPD_H_TRISTATE <= '1'; LED(3 downto 2) <= "00"; Control : process(SYSCLK, BPCTRL(1), SW) begin if (SYSCLK'event and SYSCLK = '1') then C(0) <= BPCTRL(1); C(8 downto 1) <= SW; LED(1) <= BPCTRL(1); end if; end process; end PulseGenControl;