--
--  Pulse Generator
--	This is a test chip for the Counter boards.  It creates 1 pulse
--	every X clock pulses.  Where X is the value that read from the 
--	C[7:0].  Note:  value is a binary value
--
--	***************************************************************
--  Revision history
--
--  Date		Rev	Eng				Description
--  --------	---	--------------	----------------------  
--	12/16/02	1	RY				Initial File
--

library IEEE;
use IEEE.std_logic_1164.all; 
use IEEE.std_logic_unsigned.all;

entity PulseGen is
	port (	
		SYSCLK:			in STD_LOGIC;
		C:				in STD_LOGIC_VECTOR(8 downto 0);
		PULSE_OUT:		out STD_LOGIC_VECTOR(4 downto 1);
		D:				out STD_LOGIC_VECTOR(15 downto 0);
		DCI:			in STD_LOGIC_VECTOR(14 downto 0);
		DCO:			out STD_LOGIC_VECTOR(14 downto 0)
		);
end PulseGen;

architecture PulseGen of PulseGen is 
	signal count:		STD_LOGIC_VECTOR(15 downto 0):=(others => '0');
	signal pulse:		STD_LOGIC;
	signal max_count:	STD_LOGIC_VECTOR(15 downto 0);
begin
	MaxCount : process (SYSCLK, C(5 downto 1))
	begin
		if (SYSCLK'event and SYSCLK = '1') then 
			-- NOTE: C(5 downto 1) coresponds to SW(5 downto 1)
			case (C(5 downto 1)) is
				when "00000" => max_count <= x"0002";
				when "00001" => max_count <= x"0004";
				when "00010" => max_count <= x"0008";
				when "00011" => max_count <= x"0010";
				when "00100" => max_count <= x"0020";
				when "00101" => max_count <= x"0040";
				when "00110" => max_count <= x"0080";
				when "00111" => max_count <= x"0100";
				when "01000" => max_count <= x"0200";
				when "01001" => max_count <= x"0400";
				when "01010" => max_count <= x"0800";
				when "01011" => max_count <= x"1000";
				when "01100" => max_count <= x"2000";
				when "01101" => max_count <= x"4000";
				when "01110" => max_count <= x"8000";
				when "01111" => max_count <= x"FFFF";
				when others => max_count <= x"0003";
			end case;
		end if;
	end process;

	-- Count until counter hits value on C then create pulse and reset counter
	Counter : process (SYSCLK, C)
    begin
		if (SYSCLK'event and SYSCLK = '1') then
			if (count = max_count)then
				pulse <= '1';
				count <= (others => '0');
				-- write value of count to DCO for debugging
				DCO(13 downto 0) <= count(13 downto 0);
		else
				pulse <= '0';
				count <= count + 1;
				-- write value of count to DCO for debugging
				DCO(13 downto 0) <= count(13 downto 0);
			end if;
		end if;
	end process;

	-- for debugging, route clock signal to DCO(14)
	DCO(14) <= SYSCLK;
	
	Output : process (SYSCLK, C(8 downto 6))
	begin
		if (SYSCLK'event and SYSCLK = '1') then
			-- NOTE: C(58 downto 6) coresponds to SW(8 downto 6)
			case (C(8 downto 6)) is
				-- No Counts - All zeros
				when "000" =>
				 	PULSE_OUT(1) <= '0';
					PULSE_OUT(2) <= '0';
					PULSE_OUT(3) <= '0';
					PULSE_OUT(4) <= '0';
			    -- Low Counts ONLY
				when "001" =>
					if (C(0)='0') then
						PULSE_OUT(1) <= pulse;
						PULSE_OUT(2) <= pulse;
						PULSE_OUT(3) <= pulse;
						PULSE_OUT(4) <= pulse;
					else 
					 	PULSE_OUT(1) <= '0';
						PULSE_OUT(2) <= '0';
						PULSE_OUT(3) <= '0';
						PULSE_OUT(4) <= '0';
					end if;
				-- High Counts ONLY
				when "010" =>
					if (C(0)='1') then
						PULSE_OUT(1) <= pulse;
						PULSE_OUT(2) <= pulse;
						PULSE_OUT(3) <= pulse;
						PULSE_OUT(4) <= pulse;
					else 
					 	PULSE_OUT(1) <= '0';
						PULSE_OUT(2) <= '0';
						PULSE_OUT(3) <= '0';
						PULSE_OUT(4) <= '0';
					end if;
				-- Count ALL
				when "011" =>
					PULSE_OUT(1) <= pulse;
					PULSE_OUT(2) <= pulse;
					PULSE_OUT(3) <= pulse;
					PULSE_OUT(4) <= pulse;
				when others =>
   					PULSE_OUT(1) <= pulse;
					PULSE_OUT(2) <= pulse;
					PULSE_OUT(3) <= pulse;
					PULSE_OUT(4) <= pulse;
			end case;
		end if;
	end process;
end PulseGen;