ENTITY pulsegen IS
    PORT (
	sysclk : in std_logic  ; 
	c : in std_logic_vector (8 downto 0) ; 
	pulse_out : inout std_logic_vector (4 downto 1) ; 
	d : inout std_logic_vector (15 downto 0) ; 
	dci : in std_logic_vector (14 downto 0) ; 
	dco : inout std_logic_vector (14 downto 0)
    ) ;
END pulsegen ;