| | | | | | | _________________ -| |- -| |- -| |- -| CYPRESS |- -| |- -| |- Warp VHDL Synthesis Compiler: Version 6.0.1 IR 18 -| |- Copyright (C) 1991-2000 Cypress Semiconductor |_______________| | | | | | | | ====================================================================== Compiling: pc_remote_fiber.vhd Options: -m -yu -e10 -w100 -o2 -ygs -fO -fP -v10 -dc37256 -pcy37256p160-125ac -u pc_remote_fiber.hie -uch0000 pc_remote_fiber.vhd ====================================================================== vhdlfe V6.0.1 IR 18: VHDL parser Wed Feb 21 12:09:14 2001 Library 'work' => directory 'lc37256' Linking 'f:\warp6\bin\std.vhd'. Linking 'f:\warp6\lib\common\cypress.vhd'. Linking 'f:\warp6\lib\common\work\cypress.vif'. Using control file 'pc_remote_fiber.ctl'. Library 'ieee' => directory 'f:\warp6\lib\ieee\work' Linking 'f:\warp6\lib\ieee\work\stdlogic.vif'. Linking 'f:\warp6\lib\common\stdlogic\lpmpkg.vif'. Linking 'f:\warp6\lib\common\stdlogic\rtlpkg.vif'. Linking 'f:\warp6\lib\common\stdlogic\mod_cnst.vif'. Linking 'f:\warp6\lib\common\stdlogic\mod_mthu.vif'. Linking 'f:\warp6\lib\common\stdlogic\mod_mths.vif'. Linking 'f:\warp6\lib\common\stdlogic\mod_genu.vif'. Note: Using config. rule 'clk' to set attribute 'pin_numbers' on 'clk'. Note: Using config. rule 'reset' to set attribute 'pin_numbers' on 'reset'. pc_remote_fiber.vhd (line 63, col 34): Note: Substituting module 'cmp_vv_us' for '='. pc_remote_fiber.vhd (line 67, col 36): Note: Substituting module 'add_vi_us' for '+'. pc_remote_fiber.vhd (line 76, col 34): Note: Substituting module 'cmp_vv_us' for '='. pc_remote_fiber.vhd (line 79, col 36): Note: Substituting module 'add_vi_us' for '+'. Library 'ieee' => directory 'f:\warp6\lib\ieee\work' Note: Using config. rule 'clk' to set attribute 'pin_numbers' on 'clk'. Note: Using config. rule 'reset' to set attribute 'pin_numbers' on 'reset'. pc_remote_fiber.vhd (line 212, col 34): Note: Substituting module 'cmp_vv_us' for '='. pc_remote_fiber.vhd (line 218, col 36): Note: Substituting module 'add_vi_us' for '+'. pc_remote_fiber.vhd (line 234, col 34): Note: Substituting module 'cmp_vv_us' for '='. pc_remote_fiber.vhd (line 243, col 36): Note: Substituting module 'add_vi_us' for '+'. pc_remote_fiber.vhd (line 272, col 34): Note: Substituting module 'cmp_vv_us' for '='. pc_remote_fiber.vhd (line 275, col 36): Note: Substituting module 'add_vi_us' for '+'. pc_remote_fiber.vhd (line 283, col 34): Note: Substituting module 'cmp_vv_us' for '='. pc_remote_fiber.vhd (line 286, col 36): Note: Substituting module 'add_vi_us' for '+'. Library 'ieee' => directory 'f:\warp6\lib\ieee\work' Note: Using config. rule 'clk' to set attribute 'pin_numbers' on 'clk'. Note: Using config. rule 'reset' to set attribute 'pin_numbers' on 'reset'. Note: Using config. rule 'fo_ena_l' to set attribute 'pin_numbers' on 'fo_ena_l'. Note: Using config. rule 'fo_d(9)' to set attribute 'pin_numbers' on 'fo_d(9)'. Note: Using config. rule 'fo_d(8)' to set attribute 'pin_numbers' on 'fo_d(8)'. Library 'ieee' => directory 'f:\warp6\lib\ieee\work' Note: Using config. rule 'clk' to set attribute 'pin_numbers' on 'clk'. Note: Using config. rule 'reset' to set attribute 'pin_numbers' on 'reset'. pc_remote_fiber.vhd (line 462, col 24): Note: Substituting module 'cmp_vv_us' for '='. pc_remote_fiber.vhd (line 465, col 26): Note: Substituting module 'add_vi_us' for '+'. pc_remote_fiber.vhd (line 476, col 26): Note: Substituting module 'cmp_vv_us' for '='. pc_remote_fiber.vhd (line 479, col 29): Note: Substituting module 'add_vi_us' for '+'. Library 'ieee' => directory 'f:\warp6\lib\ieee\work' Note: Using config. rule 'clk' to set attribute 'pin_numbers' on 'clk'. Note: Using config. rule 'fr_rdy_l' to set attribute 'pin_numbers' on 'fr_rdy_l'. Note: Using config. rule 'fr_status' to set attribute 'pin_numbers' on 'fr_status'. Note: Using config. rule 'fifo_reset_l' to set attribute 'pin_numbers' on 'fifo_reset_l'. Note: Using config. rule 'fifo_write_l' to set attribute 'pin_numbers' on 'fifo_write_l'. Note: Using config. rule 'fr_d(11)' to set attribute 'pin_numbers' on 'fr_d(11)'. Note: Using config. rule 'fr_d(10)' to set attribute 'pin_numbers' on 'fr_d(10)'. Note: Using config. rule 'fr_d(9)' to set attribute 'pin_numbers' on 'fr_d(9)'. Note: Using config. rule 'fr_d(8)' to set attribute 'pin_numbers' on 'fr_d(8)'. Library 'ieee' => directory 'f:\warp6\lib\ieee\work' Note: Using config. rule 'clk' to set attribute 'pin_numbers' on 'clk'. Note: Using config. rule 'reset' to set attribute 'pin_numbers' on 'reset'. Note: Using config. rule 'fifo_read_l' to set attribute 'pin_numbers' on 'fifo_read_l'. Note: Using config. rule 'fifo_reset_l' to set attribute 'pin_numbers' on 'fifo_reset_l'. Note: Using config. rule 'fifo_empty_l' to set attribute 'pin_numbers' on 'fifo_empty_l'. pc_remote_fiber.vhd (line 643, col 19): Note: Substituting module 'cmp_vv_us' for '='. pc_remote_fiber.vhd (line 647, col 20): Note: Substituting module 'add_vi_us' for '+'. Library 'ieee' => directory 'f:\warp6\lib\ieee\work' Note: Using config. rule 'clk' to set attribute 'pin_numbers' on 'clk'. Note: Using config. rule 'debug' to set attribute 'pin_numbers' on 'debug'. Note: Using config. rule 'reset' to set attribute 'pin_numbers' on 'reset'. Note: Using config. rule 'ao_from_pc_strobe' to set attribute 'pin_numbers' on 'ao_from_pc_strobe'. Note: Using config. rule 'ao_from_pc_ack' to set attribute 'pin_numbers' on 'ao_from_pc_ack'. Note: Using config. rule 'ao_to_pc_strobe' to set attribute 'pin_numbers' on 'ao_to_pc_strobe'. Note: Using config. rule 'ao_to_pc_ack' to set attribute 'pin_numbers' on 'ao_to_pc_ack'. Note: Using config. rule 'fr_ref_clk' to set attribute 'pin_numbers' on 'fr_ref_clk'. Note: Using config. rule 'fr_rf' to set attribute 'pin_numbers' on 'fr_rf'. Note: Using config. rule 'fr_mode' to set attribute 'pin_numbers' on 'fr_mode'. Note: Using config. rule 'fr_status' to set attribute 'pin_numbers' on 'fr_status'. Note: Using config. rule 'fr_rdy_l' to set attribute 'pin_numbers' on 'fr_rdy_l'. Note: Using config. rule 'fr_ckr' to set attribute 'pin_numbers' on 'fr_ckr'. Note: Using config. rule 'fo_enn_l' to set attribute 'pin_numbers' on 'fo_enn_l'. Note: Using config. rule 'fo_ena_l' to set attribute 'pin_numbers' on 'fo_ena_l'. Note: Using config. rule 'fo_ckw' to set attribute 'pin_numbers' on 'fo_ckw'. Note: Using config. rule 'fo_mode' to set attribute 'pin_numbers' on 'fo_mode'. Note: Using config. rule 'fo_foto' to set attribute 'pin_numbers' on 'fo_foto'. Note: Using config. rule 'fo_rp_l' to set attribute 'pin_numbers' on 'fo_rp_l'. Note: Using config. rule 'fifo_reset_l' to set attribute 'pin_numbers' on 'fifo_reset_l'. Note: Using config. rule 'fifo_write_l' to set attribute 'pin_numbers' on 'fifo_write_l'. Note: Using config. rule 'fifo_read_l' to set attribute 'pin_numbers' on 'fifo_read_l'. Note: Using config. rule 'fifo_full_l' to set attribute 'pin_numbers' on 'fifo_full_l'. Note: Using config. rule 'fifo_half_l' to set attribute 'pin_numbers' on 'fifo_half_l'. Note: Using config. rule 'fifo_empty_l' to set attribute 'pin_numbers' on 'fifo_empty_l'. Note: Using config. rule 'clk' to set attribute 'pin_numbers' on 'clk'. Note: Using config. rule 'reset' to set attribute 'pin_numbers' on 'reset'. Note: Using config. rule 'clk' to set attribute 'pin_numbers' on 'clk'. Note: Using config. rule 'reset' to set attribute 'pin_numbers' on 'reset'. Note: Using config. rule 'clk' to set attribute 'pin_numbers' on 'clk'. Note: Using config. rule 'reset' to set attribute 'pin_numbers' on 'reset'. Note: Using config. rule 'fo_d(9)' to set attribute 'pin_numbers' on 'fo_d(9)'. Note: Using config. rule 'fo_d(8)' to set attribute 'pin_numbers' on 'fo_d(8)'. Note: Using config. rule 'fo_ena_l' to set attribute 'pin_numbers' on 'fo_ena_l'. Note: Using config. rule 'clk' to set attribute 'pin_numbers' on 'clk'. Note: Using config. rule 'reset' to set attribute 'pin_numbers' on 'reset'. Note: Using config. rule 'clk' to set attribute 'pin_numbers' on 'clk'. Note: Using config. rule 'fr_d(11)' to set attribute 'pin_numbers' on 'fr_d(11)'. Note: Using config. rule 'fr_d(10)' to set attribute 'pin_numbers' on 'fr_d(10)'. Note: Using config. rule 'fr_d(9)' to set attribute 'pin_numbers' on 'fr_d(9)'. Note: Using config. rule 'fr_d(8)' to set attribute 'pin_numbers' on 'fr_d(8)'. Note: Using config. rule 'fr_rdy_l' to set attribute 'pin_numbers' on 'fr_rdy_l'. Note: Using config. rule 'fr_status' to set attribute 'pin_numbers' on 'fr_status'. Note: Using config. rule 'fifo_reset_l' to set attribute 'pin_numbers' on 'fifo_reset_l'. Note: Using config. rule 'fifo_write_l' to set attribute 'pin_numbers' on 'fifo_write_l'. Note: Using config. rule 'clk' to set attribute 'pin_numbers' on 'clk'. Note: Using config. rule 'reset' to set attribute 'pin_numbers' on 'reset'. Note: Using config. rule 'fifo_read_l' to set attribute 'pin_numbers' on 'fifo_read_l'. Note: Using config. rule 'fifo_reset_l' to set attribute 'pin_numbers' on 'fifo_reset_l'. Note: Using config. rule 'fifo_empty_l' to set attribute 'pin_numbers' on 'fifo_empty_l'. vhdlfe: No errors. tovif V6.0.1 IR 18: High-level synthesis Wed Feb 21 12:09:17 2001 Linking 'f:\warp6\bin\std.vhd'. Linking 'f:\warp6\lib\common\cypress.vhd'. Linking 'f:\warp6\lib\common\work\cypress.vif'. Linking '\\Dejima\ao\AO\arc_2001_1_17\vhdl\interface\interface\pc_remote\pc_remote_fiber.ctl'. Linking 'f:\warp6\lib\ieee\work\stdlogic.vif'. Linking 'f:\warp6\lib\common\stdlogic\lpmpkg.vif'. Linking 'f:\warp6\lib\common\stdlogic\rtlpkg.vif'. Linking 'f:\warp6\lib\common\stdlogic\mod_cnst.vif'. Linking 'f:\warp6\lib\common\stdlogic\mod_mthu.vif'. Linking 'f:\warp6\lib\common\stdlogic\mod_mths.vif'. Linking 'f:\warp6\lib\common\stdlogic\mod_genu.vif'. Note: Using config. rule 'fo_d(7)' to set attribute 'pin_numbers' on 'fo_d(7)'. Note: Using config. rule 'fo_d(6)' to set attribute 'pin_numbers' on 'fo_d(6)'. Note: Using config. rule 'fo_d(5)' to set attribute 'pin_numbers' on 'fo_d(5)'. Note: Using config. rule 'fo_d(4)' to set attribute 'pin_numbers' on 'fo_d(4)'. Note: Using config. rule 'fo_d(3)' to set attribute 'pin_numbers' on 'fo_d(3)'. Note: Using config. rule 'fo_d(2)' to set attribute 'pin_numbers' on 'fo_d(2)'. Note: Using config. rule 'fo_d(1)' to set attribute 'pin_numbers' on 'fo_d(1)'. Note: Using config. rule 'fo_d(0)' to set attribute 'pin_numbers' on 'fo_d(0)'. Note: Using config. rule 'fr_d(7)' to set attribute 'pin_numbers' on 'fr_d(7)'. Note: Using config. rule 'fr_d(6)' to set attribute 'pin_numbers' on 'fr_d(6)'. Note: Using config. rule 'fr_d(5)' to set attribute 'pin_numbers' on 'fr_d(5)'. Note: Using config. rule 'fr_d(4)' to set attribute 'pin_numbers' on 'fr_d(4)'. Note: Using config. rule 'fr_d(3)' to set attribute 'pin_numbers' on 'fr_d(3)'. Note: Using config. rule 'fr_d(2)' to set attribute 'pin_numbers' on 'fr_d(2)'. Note: Using config. rule 'fr_d(1)' to set attribute 'pin_numbers' on 'fr_d(1)'. Note: Using config. rule 'fr_d(0)' to set attribute 'pin_numbers' on 'fr_d(0)'. Note: Using config. rule 'fifo_d(8)' to set attribute 'pin_numbers' on 'fifo_d(8)'. Note: Using config. rule 'fifo_d(7)' to set attribute 'pin_numbers' on 'fifo_d(7)'. Note: Using config. rule 'fifo_d(6)' to set attribute 'pin_numbers' on 'fifo_d(6)'. Note: Using config. rule 'fifo_d(5)' to set attribute 'pin_numbers' on 'fifo_d(5)'. Note: Using config. rule 'fifo_d(4)' to set attribute 'pin_numbers' on 'fifo_d(4)'. Note: Using config. rule 'fifo_d(3)' to set attribute 'pin_numbers' on 'fifo_d(3)'. Note: Using config. rule 'fifo_d(2)' to set attribute 'pin_numbers' on 'fifo_d(2)'. Note: Using config. rule 'fifo_d(1)' to set attribute 'pin_numbers' on 'fifo_d(1)'. Note: Using config. rule 'fifo_d(0)' to set attribute 'pin_numbers' on 'fifo_d(0)'. Note: Using config. rule 'fifo_out(8)' to set attribute 'pin_numbers' on 'fifo_out(8)'. Note: Using config. rule 'fifo_out(7)' to set attribute 'pin_numbers' on 'fifo_out(7)'. Note: Using config. rule 'fifo_out(6)' to set attribute 'pin_numbers' on 'fifo_out(6)'. Note: Using config. rule 'fifo_out(5)' to set attribute 'pin_numbers' on 'fifo_out(5)'. Note: Using config. rule 'fifo_out(4)' to set attribute 'pin_numbers' on 'fifo_out(4)'. Note: Using config. rule 'fifo_out(3)' to set attribute 'pin_numbers' on 'fifo_out(3)'. Note: Using config. rule 'fifo_out(2)' to set attribute 'pin_numbers' on 'fifo_out(2)'. Note: Using config. rule 'fifo_out(1)' to set attribute 'pin_numbers' on 'fifo_out(1)'. Note: Using config. rule 'fifo_out(0)' to set attribute 'pin_numbers' on 'fifo_out(0)'. Note: Using config. rule 'id(31)' to set attribute 'pin_numbers' on 'id(31)'. Note: Using config. rule 'id(30)' to set attribute 'pin_numbers' on 'id(30)'. Note: Using config. rule 'id(29)' to set attribute 'pin_numbers' on 'id(29)'. Note: Using config. rule 'id(28)' to set attribute 'pin_numbers' on 'id(28)'. Note: Using config. rule 'id(27)' to set attribute 'pin_numbers' on 'id(27)'. Note: Using config. rule 'id(26)' to set attribute 'pin_numbers' on 'id(26)'. Note: Using config. rule 'id(25)' to set attribute 'pin_numbers' on 'id(25)'. Note: Using config. rule 'id(24)' to set attribute 'pin_numbers' on 'id(24)'. Note: Using config. rule 'id(23)' to set attribute 'pin_numbers' on 'id(23)'. Note: Using config. rule 'id(22)' to set attribute 'pin_numbers' on 'id(22)'. Note: Using config. rule 'id(21)' to set attribute 'pin_numbers' on 'id(21)'. Note: Using config. rule 'id(20)' to set attribute 'pin_numbers' on 'id(20)'. Note: Using config. rule 'id(19)' to set attribute 'pin_numbers' on 'id(19)'. Note: Using config. rule 'id(18)' to set attribute 'pin_numbers' on 'id(18)'. Note: Using config. rule 'id(17)' to set attribute 'pin_numbers' on 'id(17)'. Note: Using config. rule 'id(16)' to set attribute 'pin_numbers' on 'id(16)'. Note: Using config. rule 'id(15)' to set attribute 'pin_numbers' on 'id(15)'. Note: Using config. rule 'id(14)' to set attribute 'pin_numbers' on 'id(14)'. Note: Using config. rule 'id(13)' to set attribute 'pin_numbers' on 'id(13)'. Note: Using config. rule 'id(12)' to set attribute 'pin_numbers' on 'id(12)'. Note: Using config. rule 'id(11)' to set attribute 'pin_numbers' on 'id(11)'. Note: Using config. rule 'id(10)' to set attribute 'pin_numbers' on 'id(10)'. Note: Using config. rule 'id(9)' to set attribute 'pin_numbers' on 'id(9)'. Note: Using config. rule 'id(8)' to set attribute 'pin_numbers' on 'id(8)'. Note: Using config. rule 'id(7)' to set attribute 'pin_numbers' on 'id(7)'. Note: Using config. rule 'id(6)' to set attribute 'pin_numbers' on 'id(6)'. Note: Using config. rule 'id(5)' to set attribute 'pin_numbers' on 'id(5)'. Note: Using config. rule 'id(4)' to set attribute 'pin_numbers' on 'id(4)'. Note: Using config. rule 'id(3)' to set attribute 'pin_numbers' on 'id(3)'. Note: Using config. rule 'id(2)' to set attribute 'pin_numbers' on 'id(2)'. Note: Using config. rule 'id(1)' to set attribute 'pin_numbers' on 'id(1)'. Note: Using config. rule 'id(0)' to set attribute 'pin_numbers' on 'id(0)'. Note: Using config. rule 'fr_d(11)' to set attribute 'pin_numbers' on 'fr_d(11)'. Note: Using config. rule 'fr_d(10)' to set attribute 'pin_numbers' on 'fr_d(10)'. Note: Using config. rule 'fr_d(9)' to set attribute 'pin_numbers' on 'fr_d(9)'. Note: Using config. rule 'fr_d(8)' to set attribute 'pin_numbers' on 'fr_d(8)'. Note: Using config. rule 'fr_d(7)' to set attribute 'pin_numbers' on 'fr_d(7)'. Note: Using config. rule 'fr_d(6)' to set attribute 'pin_numbers' on 'fr_d(6)'. Note: Using config. rule 'fr_d(5)' to set attribute 'pin_numbers' on 'fr_d(5)'. Note: Using config. rule 'fr_d(4)' to set attribute 'pin_numbers' on 'fr_d(4)'. Note: Using config. rule 'fr_d(3)' to set attribute 'pin_numbers' on 'fr_d(3)'. Note: Using config. rule 'fr_d(2)' to set attribute 'pin_numbers' on 'fr_d(2)'. Note: Using config. rule 'fr_d(1)' to set attribute 'pin_numbers' on 'fr_d(1)'. Note: Using config. rule 'fr_d(0)' to set attribute 'pin_numbers' on 'fr_d(0)'. Note: Using config. rule 'fo_d(9)' to set attribute 'pin_numbers' on 'fo_d(9)'. Note: Using config. rule 'fo_d(8)' to set attribute 'pin_numbers' on 'fo_d(8)'. Note: Using config. rule 'fo_d(7)' to set attribute 'pin_numbers' on 'fo_d(7)'. Note: Using config. rule 'fo_d(6)' to set attribute 'pin_numbers' on 'fo_d(6)'. Note: Using config. rule 'fo_d(5)' to set attribute 'pin_numbers' on 'fo_d(5)'. Note: Using config. rule 'fo_d(4)' to set attribute 'pin_numbers' on 'fo_d(4)'. Note: Using config. rule 'fo_d(3)' to set attribute 'pin_numbers' on 'fo_d(3)'. Note: Using config. rule 'fo_d(2)' to set attribute 'pin_numbers' on 'fo_d(2)'. Note: Using config. rule 'fo_d(1)' to set attribute 'pin_numbers' on 'fo_d(1)'. Note: Using config. rule 'fo_d(0)' to set attribute 'pin_numbers' on 'fo_d(0)'. Note: Using config. rule 'fifo_d(8)' to set attribute 'pin_numbers' on 'fifo_d(8)'. Note: Using config. rule 'fifo_d(7)' to set attribute 'pin_numbers' on 'fifo_d(7)'. Note: Using config. rule 'fifo_d(6)' to set attribute 'pin_numbers' on 'fifo_d(6)'. Note: Using config. rule 'fifo_d(5)' to set attribute 'pin_numbers' on 'fifo_d(5)'. Note: Using config. rule 'fifo_d(4)' to set attribute 'pin_numbers' on 'fifo_d(4)'. Note: Using config. rule 'fifo_d(3)' to set attribute 'pin_numbers' on 'fifo_d(3)'. Note: Using config. rule 'fifo_d(2)' to set attribute 'pin_numbers' on 'fifo_d(2)'. Note: Using config. rule 'fifo_d(1)' to set attribute 'pin_numbers' on 'fifo_d(1)'. Note: Using config. rule 'fifo_d(0)' to set attribute 'pin_numbers' on 'fifo_d(0)'. Note: Using config. rule 'fifo_out(8)' to set attribute 'pin_numbers' on 'fifo_out(8)'. Note: Using config. rule 'fifo_out(7)' to set attribute 'pin_numbers' on 'fifo_out(7)'. Note: Using config. rule 'fifo_out(6)' to set attribute 'pin_numbers' on 'fifo_out(6)'. Note: Using config. rule 'fifo_out(5)' to set attribute 'pin_numbers' on 'fifo_out(5)'. Note: Using config. rule 'fifo_out(4)' to set attribute 'pin_numbers' on 'fifo_out(4)'. Note: Using config. rule 'fifo_out(3)' to set attribute 'pin_numbers' on 'fifo_out(3)'. Note: Using config. rule 'fifo_out(2)' to set attribute 'pin_numbers' on 'fifo_out(2)'. Note: Using config. rule 'fifo_out(1)' to set attribute 'pin_numbers' on 'fifo_out(1)'. Note: Using config. rule 'fifo_out(0)' to set attribute 'pin_numbers' on 'fifo_out(0)'. tovif: No errors. topld V6.0.1 IR 18: Synthesis and optimization Wed Feb 21 12:09:23 2001 Linking 'f:\warp6\bin\std.vhd'. Linking 'f:\warp6\lib\common\cypress.vhd'. Linking 'f:\warp6\lib\common\work\cypress.vif'. Linking '\\Dejima\ao\AO\arc_2001_1_17\vhdl\interface\interface\pc_remote\pc_remote_fiber.ctl'. Linking 'f:\warp6\lib\ieee\work\stdlogic.vif'. Linking 'f:\warp6\lib\common\stdlogic\lpmpkg.vif'. Linking 'f:\warp6\lib\common\stdlogic\rtlpkg.vif'. Linking 'f:\warp6\lib\common\stdlogic\mod_cnst.vif'. Linking 'f:\warp6\lib\common\stdlogic\mod_mthu.vif'. Linking 'f:\warp6\lib\common\stdlogic\mod_mths.vif'. Linking 'f:\warp6\lib\common\stdlogic\mod_genu.vif'. Note: Using config. rule 'clk' to set attribute 'pin_numbers' on 'clk'. Note: Using config. rule 'debug' to set attribute 'pin_numbers' on 'debug'. Note: Using config. rule 'id(31)' to set attribute 'pin_numbers' on 'id(31)'. Note: Using config. rule 'id(30)' to set attribute 'pin_numbers' on 'id(30)'. Note: Using config. rule 'id(29)' to set attribute 'pin_numbers' on 'id(29)'. Note: Using config. rule 'id(28)' to set attribute 'pin_numbers' on 'id(28)'. Note: Using config. rule 'id(27)' to set attribute 'pin_numbers' on 'id(27)'. Note: Using config. rule 'id(26)' to set attribute 'pin_numbers' on 'id(26)'. Note: Using config. rule 'id(25)' to set attribute 'pin_numbers' on 'id(25)'. Note: Using config. rule 'id(24)' to set attribute 'pin_numbers' on 'id(24)'. Note: Using config. rule 'id(23)' to set attribute 'pin_numbers' on 'id(23)'. Note: Using config. rule 'id(22)' to set attribute 'pin_numbers' on 'id(22)'. Note: Using config. rule 'id(21)' to set attribute 'pin_numbers' on 'id(21)'. Note: Using config. rule 'id(20)' to set attribute 'pin_numbers' on 'id(20)'. Note: Using config. rule 'id(19)' to set attribute 'pin_numbers' on 'id(19)'. Note: Using config. rule 'id(18)' to set attribute 'pin_numbers' on 'id(18)'. Note: Using config. rule 'id(17)' to set attribute 'pin_numbers' on 'id(17)'. Note: Using config. rule 'id(16)' to set attribute 'pin_numbers' on 'id(16)'. Note: Using config. rule 'id(15)' to set attribute 'pin_numbers' on 'id(15)'. Note: Using config. rule 'id(14)' to set attribute 'pin_numbers' on 'id(14)'. Note: Using config. rule 'id(13)' to set attribute 'pin_numbers' on 'id(13)'. Note: Using config. rule 'id(12)' to set attribute 'pin_numbers' on 'id(12)'. Note: Using config. rule 'id(11)' to set attribute 'pin_numbers' on 'id(11)'. Note: Using config. rule 'id(10)' to set attribute 'pin_numbers' on 'id(10)'. Note: Using config. rule 'id(9)' to set attribute 'pin_numbers' on 'id(9)'. Note: Using config. rule 'id(8)' to set attribute 'pin_numbers' on 'id(8)'. Note: Using config. rule 'id(7)' to set attribute 'pin_numbers' on 'id(7)'. Note: Using config. rule 'id(6)' to set attribute 'pin_numbers' on 'id(6)'. Note: Using config. rule 'id(5)' to set attribute 'pin_numbers' on 'id(5)'. Note: Using config. rule 'id(4)' to set attribute 'pin_numbers' on 'id(4)'. Note: Using config. rule 'id(3)' to set attribute 'pin_numbers' on 'id(3)'. Note: Using config. rule 'id(2)' to set attribute 'pin_numbers' on 'id(2)'. Note: Using config. rule 'id(1)' to set attribute 'pin_numbers' on 'id(1)'. Note: Using config. rule 'id(0)' to set attribute 'pin_numbers' on 'id(0)'. Note: Using config. rule 'reset' to set attribute 'pin_numbers' on 'reset'. Note: Using config. rule 'ao_from_pc_strobe' to set attribute 'pin_numbers' on 'ao_from_pc_strobe'. Note: Using config. rule 'ao_from_pc_ack' to set attribute 'pin_numbers' on 'ao_from_pc_ack'. Note: Using config. rule 'ao_to_pc_strobe' to set attribute 'pin_numbers' on 'ao_to_pc_strobe'. Note: Using config. rule 'ao_to_pc_ack' to set attribute 'pin_numbers' on 'ao_to_pc_ack'. Note: Using config. rule 'fr_d(11)' to set attribute 'pin_numbers' on 'fr_d(11)'. Note: Using config. rule 'fr_d(10)' to set attribute 'pin_numbers' on 'fr_d(10)'. Note: Using config. rule 'fr_d(9)' to set attribute 'pin_numbers' on 'fr_d(9)'. Note: Using config. rule 'fr_d(8)' to set attribute 'pin_numbers' on 'fr_d(8)'. Note: Using config. rule 'fr_d(7)' to set attribute 'pin_numbers' on 'fr_d(7)'. Note: Using config. rule 'fr_d(6)' to set attribute 'pin_numbers' on 'fr_d(6)'. Note: Using config. rule 'fr_d(5)' to set attribute 'pin_numbers' on 'fr_d(5)'. Note: Using config. rule 'fr_d(4)' to set attribute 'pin_numbers' on 'fr_d(4)'. Note: Using config. rule 'fr_d(3)' to set attribute 'pin_numbers' on 'fr_d(3)'. Note: Using config. rule 'fr_d(2)' to set attribute 'pin_numbers' on 'fr_d(2)'. Note: Using config. rule 'fr_d(1)' to set attribute 'pin_numbers' on 'fr_d(1)'. Note: Using config. rule 'fr_d(0)' to set attribute 'pin_numbers' on 'fr_d(0)'. Note: Using config. rule 'fr_ref_clk' to set attribute 'pin_numbers' on 'fr_ref_clk'. Note: Using config. rule 'fr_rf' to set attribute 'pin_numbers' on 'fr_rf'. Note: Using config. rule 'fr_mode' to set attribute 'pin_numbers' on 'fr_mode'. Note: Using config. rule 'fr_status' to set attribute 'pin_numbers' on 'fr_status'. Note: Using config. rule 'fr_rdy_l' to set attribute 'pin_numbers' on 'fr_rdy_l'. Note: Using config. rule 'fr_ckr' to set attribute 'pin_numbers' on 'fr_ckr'. Note: Using config. rule 'fo_d(9)' to set attribute 'pin_numbers' on 'fo_d(9)'. Note: Using config. rule 'fo_d(8)' to set attribute 'pin_numbers' on 'fo_d(8)'. Note: Using config. rule 'fo_d(7)' to set attribute 'pin_numbers' on 'fo_d(7)'. Note: Using config. rule 'fo_d(6)' to set attribute 'pin_numbers' on 'fo_d(6)'. Note: Using config. rule 'fo_d(5)' to set attribute 'pin_numbers' on 'fo_d(5)'. Note: Using config. rule 'fo_d(4)' to set attribute 'pin_numbers' on 'fo_d(4)'. Note: Using config. rule 'fo_d(3)' to set attribute 'pin_numbers' on 'fo_d(3)'. Note: Using config. rule 'fo_d(2)' to set attribute 'pin_numbers' on 'fo_d(2)'. Note: Using config. rule 'fo_d(1)' to set attribute 'pin_numbers' on 'fo_d(1)'. Note: Using config. rule 'fo_d(0)' to set attribute 'pin_numbers' on 'fo_d(0)'. Note: Using config. rule 'fo_enn_l' to set attribute 'pin_numbers' on 'fo_enn_l'. Note: Using config. rule 'fo_ena_l' to set attribute 'pin_numbers' on 'fo_ena_l'. Note: Using config. rule 'fo_ckw' to set attribute 'pin_numbers' on 'fo_ckw'. Note: Using config. rule 'fo_mode' to set attribute 'pin_numbers' on 'fo_mode'. Note: Using config. rule 'fo_foto' to set attribute 'pin_numbers' on 'fo_foto'. Note: Using config. rule 'fo_rp_l' to set attribute 'pin_numbers' on 'fo_rp_l'. Note: Using config. rule 'fifo_reset_l' to set attribute 'pin_numbers' on 'fifo_reset_l'. Note: Using config. rule 'fifo_write_l' to set attribute 'pin_numbers' on 'fifo_write_l'. Note: Using config. rule 'fifo_d(8)' to set attribute 'pin_numbers' on 'fifo_d(8)'. Note: Using config. rule 'fifo_d(7)' to set attribute 'pin_numbers' on 'fifo_d(7)'. Note: Using config. rule 'fifo_d(6)' to set attribute 'pin_numbers' on 'fifo_d(6)'. Note: Using config. rule 'fifo_d(5)' to set attribute 'pin_numbers' on 'fifo_d(5)'. Note: Using config. rule 'fifo_d(4)' to set attribute 'pin_numbers' on 'fifo_d(4)'. Note: Using config. rule 'fifo_d(3)' to set attribute 'pin_numbers' on 'fifo_d(3)'. Note: Using config. rule 'fifo_d(2)' to set attribute 'pin_numbers' on 'fifo_d(2)'. Note: Using config. rule 'fifo_d(1)' to set attribute 'pin_numbers' on 'fifo_d(1)'. Note: Using config. rule 'fifo_d(0)' to set attribute 'pin_numbers' on 'fifo_d(0)'. Note: Using config. rule 'fifo_read_l' to set attribute 'pin_numbers' on 'fifo_read_l'. Note: Using config. rule 'fifo_full_l' to set attribute 'pin_numbers' on 'fifo_full_l'. Note: Using config. rule 'fifo_half_l' to set attribute 'pin_numbers' on 'fifo_half_l'. Note: Using config. rule 'fifo_empty_l' to set attribute 'pin_numbers' on 'fifo_empty_l'. Note: Using config. rule 'fifo_out(8)' to set attribute 'pin_numbers' on 'fifo_out(8)'. Note: Using config. rule 'fifo_out(7)' to set attribute 'pin_numbers' on 'fifo_out(7)'. Note: Using config. rule 'fifo_out(6)' to set attribute 'pin_numbers' on 'fifo_out(6)'. Note: Using config. rule 'fifo_out(5)' to set attribute 'pin_numbers' on 'fifo_out(5)'. Note: Using config. rule 'fifo_out(4)' to set attribute 'pin_numbers' on 'fifo_out(4)'. Note: Using config. rule 'fifo_out(3)' to set attribute 'pin_numbers' on 'fifo_out(3)'. Note: Using config. rule 'fifo_out(2)' to set attribute 'pin_numbers' on 'fifo_out(2)'. Note: Using config. rule 'fifo_out(1)' to set attribute 'pin_numbers' on 'fifo_out(1)'. Note: Using config. rule 'fifo_out(0)' to set attribute 'pin_numbers' on 'fifo_out(0)'. Linking 'f:\warp6\lib\lc370\stdlogic\c370.vif'. State variable 'iu_read' is represented by a Bit_vector (0 to 1). State encoding (sequential) for 'iu_read' is: idle := b"00"; hs := b"01"; iu_hs1 := b"10"; iu_hs2 := b"11"; State variable 'fi_read_state' is represented by a Bit_vector (0 to 2). State encoding (sequential) for 'fi_read_state' is: idle := b"000"; am_i_addressed := b"001"; fi_hs_for_address := b"010"; fi_hs_for_data := b"011"; fi_use_ctrl_data := b"100"; internal_ack1 := b"101"; internal_ack2 := b"110"; State variable 'state' is represented by a Bit_vector (0 to 2). State encoding (sequential) for 'state' is: fo_idle := b"000"; fo_byte1 := b"001"; fo_wait1 := b"010"; fo_byte2 := b"011"; fo_wait2 := b"100"; State variable 'read_state' is represented by a Bit_vector (0 to 1). State encoding (sequential) for 'read_state' is: idle := b"00"; read_req := b"01"; end_cycle := b"10"; State variable 'fr_state' is represented by a Bit_vector (0 to 0). State encoding (sequential) for 'fr_state' is: idle := b"0"; fifo_latch := b"1"; State variable 'pump_state' is represented by a Bit_vector (0 to 1). State encoding (sequential) for 'pump_state' is: idle := b"00"; fifo_strobe := b"01"; fifo_read_data := b"10"; fifo_wait_on_empty := b"11"; Note: Using config. rule 'clk' to set attribute 'pin_numbers' on 'clk'. Note: Using config. rule 'clk' to set attribute 'pin_numbers' on 'clk'. ---------------------------------------------------------- Detecting unused logic. ---------------------------------------------------------- User names \fi_reader:loopback_state\ this_chip_selected address_from_pc_7 address_from_pc_6 address_from_pc_5 address_from_pc_4 address_from_pc_3 address_from_pc_2 address_from_pc_1 address_from_pc_0 \ibus_fo:fo_send\ violation_count_7 violation_count_6 violation_count_5 violation_count_4 violation_count_3 violation_count_2 violation_count_1 violation_count_0 increment_fifo_count Deleted 20 User equations/components. Deleted 22 Synthesized equations/components. ------------------------------------------------------ Alias Detection ------------------------------------------------------ ------------------------------------------------------ Aliased 1 equations, 63 wires. ------------------------------------------------------ ---------------------------------------------------------- Circuit simplification ---------------------------------------------------------- ---------------------------------------------------------- Circuit simplification results: Expanded 37 signals. Turned 0 signals into soft nodes. Maximum expansion cost was set at 10. ---------------------------------------------------------- ------------------------------------------------------ Alias Detection ------------------------------------------------------ ------------------------------------------------------ Aliased 0 equations, 0 wires. ------------------------------------------------------ Created 468 PLD nodes. topld: No errors. ---------------------------------------------------------------------------- PLD Optimizer Software: DSGNOPT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 DESIGN HEADER INFORMATION (12:09:36) Input File(s): pc_remote_fiber.pla Device : cy37256p160 Package : cy37256p160-125ac ReportFile : pc_remote_fiber.rpt Program Controls: COMMAND LANGUAGE_VHDL COMMAND UserCode 0000000000000000 COMMAND PROPERTY BUS_HOLD ENABLE Signal Requests: GROUP DT-OPT ALL GROUP USEPOL ALL GROUP FAST_SLEW ALL Completed Successfully ---------------------------------------------------------------------------- PLD Optimizer Software: DSGNOPT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 OPTIMIZATION OPTIONS (12:09:36) Messages: Information: Process virtual '\pump:count_0\\D\' ... expanded. Information: Process virtual '\pump:count_1\\D\' ... expanded. Information: Process virtual '\pump:pump_stateSBV_1\\D\' ... expanded. Information: Process virtual '\pump:pump_stateSBV_0\\D\' ... expanded. Information: Process virtual '\fr_imp:fr_stateSBV_0\\D\' ... expanded. Information: Process virtual 'fiber_to_ibus_buf_0D' ... expanded. Information: Process virtual 'fiber_to_ibus_buf_1D' ... expanded. Information: Process virtual 'fiber_to_ibus_buf_2D' ... expanded. Information: Process virtual 'fiber_to_ibus_buf_3D' ... expanded. Information: Process virtual 'fiber_to_ibus_buf_4D' ... expanded. Information: Process virtual 'fiber_to_ibus_buf_5D' ... expanded. Information: Process virtual 'fiber_to_ibus_buf_6D' ... expanded. Information: Process virtual 'fiber_to_ibus_buf_7D' ... expanded. Information: Process virtual 'fiber_to_ibus_buf_8D' ... expanded. Information: Process virtual 'fiber_to_ibus_buf_9D' ... expanded. Information: Process virtual 'fiber_to_ibus_buf_10D' ... expanded. Information: Process virtual 'fiber_to_ibus_buf_11D' ... expanded. Information: Process virtual 'fiber_to_ibus_buf_12D' ... expanded. Information: Process virtual 'fiber_to_ibus_buf_13D' ... expanded. Information: Process virtual 'fiber_to_ibus_buf_14D' ... expanded. Information: Process virtual 'fiber_to_ibus_buf_15D' ... expanded. Information: Process virtual '\ibus_fi:timeout_0\\D\' ... expanded. Information: Process virtual '\ibus_fi:timeout_1\\D\' ... expanded. Information: Process virtual '\ibus_fi:timeout_2\\D\' ... expanded. Information: Process virtual '\ibus_fi:timeout_3\\D\' ... expanded. Information: Process virtual 'refill_ibus_output_bufD' ... expanded. Information: Process virtual 'data_pump_word_readyD' ... expanded. Information: Process virtual '\ibus_fi:read_stateSBV_1\\D\' ... expanded. Information: Process virtual '\ibus_fi:read_stateSBV_0\\D\' ... expanded. Information: Process virtual '\ibus_fo:stateSBV_2\\D\' ... expanded. Information: Process virtual '\ibus_fo:stateSBV_1\\D\' ... expanded. Information: Process virtual '\ibus_fo:stateSBV_0\\D\' ... expanded. Information: Process virtual '\fi_reader:timeout_0\\D\' ... expanded. Information: Process virtual '\fi_reader:timeout_1\\D\' ... expanded. Information: Process virtual '\fi_reader:timeout_2\\D\' ... expanded. Information: Process virtual '\fi_reader:timeout_3\\D\' ... expanded. Information: Process virtual 'fi_data_0D' ... expanded. Information: Process virtual 'fi_data_1D' ... expanded. Information: Process virtual 'fi_data_2D' ... expanded. Information: Process virtual 'fi_data_3D' ... expanded. Information: Process virtual 'fi_data_4D' ... expanded. Information: Process virtual 'fi_data_6D' ... expanded. Information: Process virtual 'fi_data_7D' ... expanded. Information: Process virtual 'fi_data_13D' ... expanded. Information: Process virtual 'fi_data_14D' ... expanded. Information: Process virtual 'fi_data_5D' ... expanded. Information: Process virtual 'fi_data_8D' ... expanded. Information: Process virtual 'fi_data_9D' ... expanded. Information: Process virtual 'fi_data_10D' ... expanded. Information: Process virtual 'fi_data_11D' ... expanded. Information: Process virtual 'fi_data_12D' ... expanded. Information: Process virtual 'fi_data_15D' ... expanded. Information: Process virtual '\fi_reader:this_is_a_ctrl_transaction\\D\' ... expanded. Information: Process virtual 'fi_to_ibus_ackD' ... expanded. Information: Process virtual '\fi_reader:fi_read_stateSBV_2\\D\' ... expanded. Information: Process virtual '\fi_reader:fi_read_stateSBV_1\\D\' ... expanded. Information: Process virtual '\fi_reader:fi_read_stateSBV_0\\D\' ... expanded. Information: Process virtual '\ibus_reader:timeout_0\\D\' ... expanded. Information: Process virtual '\ibus_reader:timeout_1\\D\' ... expanded. Information: Process virtual '\ibus_reader:timeout_2\\D\' ... expanded. Information: Process virtual '\ibus_reader:timeout_3\\D\' ... expanded. Information: Process virtual 'data_to_fo_0D' ... expanded. Information: Process virtual 'data_to_fo_1D' ... expanded. Information: Process virtual 'data_to_fo_2D' ... expanded. Information: Process virtual 'data_to_fo_3D' ... expanded. Information: Process virtual 'data_to_fo_4D' ... expanded. Information: Process virtual 'data_to_fo_5D' ... expanded. Information: Process virtual 'data_to_fo_6D' ... expanded. Information: Process virtual 'data_to_fo_7D' ... expanded. Information: Process virtual 'data_to_fo_8D' ... expanded. Information: Process virtual 'data_to_fo_9D' ... expanded. Information: Process virtual 'data_to_fo_10D' ... expanded. Information: Process virtual 'data_to_fo_11D' ... expanded. Information: Process virtual 'data_to_fo_12D' ... expanded. Information: Process virtual 'data_to_fo_13D' ... expanded. Information: Process virtual 'data_to_fo_14D' ... expanded. Information: Process virtual 'data_to_fo_15D' ... expanded. Information: Process virtual 'write_to_fo_ackD' ... expanded. Information: Process virtual '\ibus_reader:iu_readSBV_1\\D\' ... expanded. Information: Process virtual '\ibus_reader:iu_readSBV_0\\D\' ... expanded. Information: Process virtual 'write_to_fo_reqD' ... expanded. Information: Process virtual 'fifo_read_lD' ... expanded. Information: Process virtual '\fifo_d(0)D\' ... expanded. Information: Process virtual '\fifo_d(1)D\' ... expanded. Information: Process virtual '\fifo_d(2)D\' ... expanded. Information: Process virtual '\fifo_d(3)D\' ... expanded. Information: Process virtual '\fifo_d(4)D\' ... expanded. Information: Process virtual '\fifo_d(5)D\' ... expanded. Information: Process virtual '\fifo_d(6)D\' ... expanded. Information: Process virtual '\fifo_d(7)D\' ... expanded. Information: Process virtual '\fifo_d(8)D\' ... expanded. Information: Process virtual 'fifo_write_lD' ... expanded. Information: Process virtual 'fifo_reset_lD' ... expanded. Information: Process virtual 'fo_ena_lD' ... expanded. Information: Process virtual '\fo_d(0)D\' ... expanded. Information: Process virtual '\fo_d(1)D\' ... expanded. Information: Process virtual '\fo_d(2)D\' ... expanded. Information: Process virtual '\fo_d(3)D\' ... expanded. Information: Process virtual '\fo_d(4)D\' ... expanded. Information: Process virtual '\fo_d(5)D\' ... expanded. Information: Process virtual '\fo_d(6)D\' ... expanded. Information: Process virtual '\fo_d(7)D\' ... expanded. Information: Process virtual '\fo_d(8)D\' ... expanded. Information: Process virtual '\fo_d(9)D\' ... expanded. Information: Process virtual 'ao_to_pc_ackD' ... expanded. Information: Process virtual 'ao_from_pc_strobeD' ... expanded. Information: Process virtual '\id(0)D\' ... expanded. Information: Process virtual '\id(1)D\' ... expanded. Information: Process virtual '\id(2)D\' ... expanded. Information: Process virtual '\id(3)D\' ... expanded. Information: Process virtual '\id(4)D\' ... expanded. Information: Process virtual '\id(5)D\' ... expanded. Information: Process virtual '\id(6)D\' ... expanded. Information: Process virtual '\id(7)D\' ... expanded. Information: Process virtual '\id(8)D\' ... expanded. Information: Process virtual '\id(9)D\' ... expanded. Information: Process virtual '\id(10)D\' ... expanded. Information: Process virtual '\id(11)D\' ... expanded. Information: Process virtual '\id(12)D\' ... expanded. Information: Process virtual '\id(13)D\' ... expanded. Information: Process virtual '\id(14)D\' ... expanded. Information: Process virtual '\id(15)D\' ... expanded. Information: Process virtual '\pump:count_0\' ... converted to NODE. Information: Process virtual '\pump:count_1\' ... converted to NODE. Information: Process virtual '\pump:pump_stateSBV_1\' ... converted to NODE. Information: Process virtual '\pump:pump_stateSBV_0\' ... converted to NODE. Information: Process virtual '\fr_imp:fr_stateSBV_0\' ... converted to NODE. Information: Process virtual 'fiber_to_ibus_buf_0' ... converted to NODE. Information: Process virtual 'fiber_to_ibus_buf_1' ... converted to NODE. Information: Process virtual 'fiber_to_ibus_buf_2' ... converted to NODE. Information: Process virtual 'fiber_to_ibus_buf_3' ... converted to NODE. Information: Process virtual 'fiber_to_ibus_buf_4' ... converted to NODE. Information: Process virtual 'fiber_to_ibus_buf_5' ... converted to NODE. Information: Process virtual 'fiber_to_ibus_buf_6' ... converted to NODE. Information: Process virtual 'fiber_to_ibus_buf_7' ... converted to NODE. Information: Process virtual 'fiber_to_ibus_buf_8' ... converted to NODE. Information: Process virtual 'fiber_to_ibus_buf_9' ... converted to NODE. Information: Process virtual 'fiber_to_ibus_buf_10' ... converted to NODE. Information: Process virtual 'fiber_to_ibus_buf_11' ... converted to NODE. Information: Process virtual 'fiber_to_ibus_buf_12' ... converted to NODE. Information: Process virtual 'fiber_to_ibus_buf_13' ... converted to NODE. Information: Process virtual 'fiber_to_ibus_buf_14' ... converted to NODE. Information: Process virtual 'fiber_to_ibus_buf_15' ... converted to NODE. Information: Process virtual '\ibus_fi:timeout_0\' ... converted to NODE. Information: Process virtual '\ibus_fi:timeout_1\' ... converted to NODE. Information: Process virtual '\ibus_fi:timeout_2\' ... converted to NODE. Information: Process virtual '\ibus_fi:timeout_3\' ... converted to NODE. Information: Process virtual 'refill_ibus_output_buf' ... converted to NODE. Information: Process virtual 'data_pump_word_ready' ... converted to NODE. Information: Process virtual '\ibus_fi:read_stateSBV_1\' ... converted to NODE. Information: Process virtual '\ibus_fi:read_stateSBV_0\' ... converted to NODE. Information: Process virtual '\ibus_fo:stateSBV_2\' ... converted to NODE. Information: Process virtual '\ibus_fo:stateSBV_1\' ... converted to NODE. Information: Process virtual '\ibus_fo:stateSBV_0\' ... converted to NODE. Information: Process virtual '\fi_reader:timeout_0\' ... converted to NODE. Information: Process virtual '\fi_reader:timeout_1\' ... converted to NODE. Information: Process virtual '\fi_reader:timeout_2\' ... converted to NODE. Information: Process virtual '\fi_reader:timeout_3\' ... converted to NODE. Information: Process virtual 'fi_data_0' ... converted to NODE. Information: Process virtual 'fi_data_1' ... converted to NODE. Information: Process virtual 'fi_data_2' ... converted to NODE. Information: Process virtual 'fi_data_3' ... converted to NODE. Information: Process virtual 'fi_data_4' ... converted to NODE. Information: Process virtual 'fi_data_6' ... converted to NODE. Information: Process virtual 'fi_data_7' ... converted to NODE. Information: Process virtual 'fi_data_13' ... converted to NODE. Information: Process virtual 'fi_data_14' ... converted to NODE. Information: Process virtual 'fi_to_ibus_req' ... converted to NODE. Information: Process virtual 'fi_data_5' ... converted to NODE. Information: Process virtual 'fi_data_8' ... converted to NODE. Information: Process virtual 'fi_data_9' ... converted to NODE. Information: Process virtual 'fi_data_10' ... converted to NODE. Information: Process virtual 'fi_data_11' ... converted to NODE. Information: Process virtual 'fi_data_12' ... converted to NODE. Information: Process virtual 'fi_data_15' ... converted to NODE. Information: Process virtual 'reset_fifo' ... converted to NODE. Information: Process virtual '\fi_reader:this_is_a_ctrl_transaction\' ... converted to NODE. Information: Process virtual 'fi_to_ibus_ack' ... converted to NODE. Information: Process virtual '\fi_reader:fi_read_stateSBV_2\' ... converted to NODE. Information: Process virtual '\fi_reader:fi_read_stateSBV_1\' ... converted to NODE. Information: Process virtual '\fi_reader:fi_read_stateSBV_0\' ... converted to NODE. Information: Process virtual '\ibus_reader:timeout_0\' ... converted to NODE. Information: Process virtual '\ibus_reader:timeout_1\' ... converted to NODE. Information: Process virtual '\ibus_reader:timeout_2\' ... converted to NODE. Information: Process virtual '\ibus_reader:timeout_3\' ... converted to NODE. Information: Process virtual 'data_to_fo_0' ... converted to NODE. Information: Process virtual 'data_to_fo_1' ... converted to NODE. Information: Process virtual 'data_to_fo_2' ... converted to NODE. Information: Process virtual 'data_to_fo_3' ... converted to NODE. Information: Process virtual 'data_to_fo_4' ... converted to NODE. Information: Process virtual 'data_to_fo_5' ... converted to NODE. Information: Process virtual 'data_to_fo_6' ... converted to NODE. Information: Process virtual 'data_to_fo_7' ... converted to NODE. Information: Process virtual 'data_to_fo_8' ... converted to NODE. Information: Process virtual 'data_to_fo_9' ... converted to NODE. Information: Process virtual 'data_to_fo_10' ... converted to NODE. Information: Process virtual 'data_to_fo_11' ... converted to NODE. Information: Process virtual 'data_to_fo_12' ... converted to NODE. Information: Process virtual 'data_to_fo_13' ... converted to NODE. Information: Process virtual 'data_to_fo_14' ... converted to NODE. Information: Process virtual 'data_to_fo_15' ... converted to NODE. Information: Process virtual 'write_to_fo_ack' ... converted to NODE. Information: Process virtual '\ibus_reader:iu_readSBV_1\' ... converted to NODE. Information: Process virtual '\ibus_reader:iu_readSBV_0\' ... converted to NODE. Information: Process virtual 'write_to_fo_req' ... converted to NODE. Information: Process virtual 'fo_data_strobe' ... expanded. Information: Process virtual 'fi_to_ibus_reqD' ... expanded. Information: Process virtual 'reset_fifoD' ... expanded. Information: Generating both D & T register equations for signal id(0).D[2] Information: Expanding XOR equation found on signal id(0).T[2] Information: Generating both D & T register equations for signal id(1).D[3] Information: Expanding XOR equation found on signal id(1).T[3] Information: Generating both D & T register equations for signal id(2).D[4] Information: Expanding XOR equation found on signal id(2).T[4] Information: Generating both D & T register equations for signal id(3).D[5] Information: Expanding XOR equation found on signal id(3).T[5] Information: Generating both D & T register equations for signal id(4).D[7] Information: Expanding XOR equation found on signal id(4).T[7] Information: Generating both D & T register equations for signal id(5).D[8] Information: Expanding XOR equation found on signal id(5).T[8] Information: Generating both D & T register equations for signal id(6).D[9] Information: Expanding XOR equation found on signal id(6).T[9] Information: Generating both D & T register equations for signal id(7).D[11] Information: Expanding XOR equation found on signal id(7).T[11] Information: Generating both D & T register equations for signal id(8).D[12] Information: Expanding XOR equation found on signal id(8).T[12] Information: Generating both D & T register equations for signal id(9).D[13] Information: Expanding XOR equation found on signal id(9).T[13] Information: Generating both D & T register equations for signal id(10).D[14] Information: Expanding XOR equation found on signal id(10).T[14] Information: Generating both D & T register equations for signal id(11).D[15] Information: Expanding XOR equation found on signal id(11).T[15] Information: Generating both D & T register equations for signal id(12).D[16] Information: Expanding XOR equation found on signal id(12).T[16] Information: Generating both D & T register equations for signal id(13).D[17] Information: Expanding XOR equation found on signal id(13).T[17] Information: Generating both D & T register equations for signal id(14).D[18] Information: Expanding XOR equation found on signal id(14).T[18] Information: Generating both D & T register equations for signal id(15).D[23] Information: Expanding XOR equation found on signal id(15).T[23] Information: Generating both D & T register equations for signal ao_from_pc_strobe.D[53] Information: Expanding XOR equation found on signal ao_from_pc_strobe.T[53] Information: Generating both D & T register equations for signal ao_to_pc_ack.D[56] Information: Expanding XOR equation found on signal ao_to_pc_ack.T[56] Information: Generating both D & T register equations for signal fo_d(0).D[103] Information: Expanding XOR equation found on signal fo_d(0).T[103] Information: Generating both D & T register equations for signal fo_d(1).D[104] Information: Expanding XOR equation found on signal fo_d(1).T[104] Information: Generating both D & T register equations for signal fo_d(2).D[105] Information: Expanding XOR equation found on signal fo_d(2).T[105] Information: Generating both D & T register equations for signal fo_d(3).D[106] Information: Expanding XOR equation found on signal fo_d(3).T[106] Information: Generating both D & T register equations for signal fo_d(4).D[107] Information: Expanding XOR equation found on signal fo_d(4).T[107] Information: Generating both D & T register equations for signal fo_d(5).D[108] Information: Expanding XOR equation found on signal fo_d(5).T[108] Information: Generating both D & T register equations for signal fo_d(6).D[109] Information: Expanding XOR equation found on signal fo_d(6).T[109] Information: Generating both D & T register equations for signal fo_d(7).D[110] Information: Expanding XOR equation found on signal fo_d(7).T[110] Information: Generating both D & T register equations for signal fo_d(8).D[112] Information: Expanding XOR equation found on signal fo_d(8).T[112] Information: Generating both D & T register equations for signal fo_d(9).D[113] Information: Expanding XOR equation found on signal fo_d(9).T[113] Information: Generating both D & T register equations for signal fo_ena_l.D[118] Information: Expanding XOR equation found on signal fo_ena_l.T[118] Information: Generating both D & T register equations for signal fo_ckw.D[119] Information: Expanding XOR equation found on signal fo_ckw.T[119] Information: Generating both D & T register equations for signal fifo_reset_l.D[127] Information: Expanding XOR equation found on signal fifo_reset_l.T[127] Information: Generating both D & T register equations for signal fifo_write_l.D[128] Information: Expanding XOR equation found on signal fifo_write_l.T[128] Information: Generating both D & T register equations for signal fifo_d(8).D[129] Information: Expanding XOR equation found on signal fifo_d(8).T[129] Information: Generating both D & T register equations for signal fifo_d(0).D[131] Information: Expanding XOR equation found on signal fifo_d(0).T[131] Information: Generating both D & T register equations for signal fifo_d(1).D[132] Information: Expanding XOR equation found on signal fifo_d(1).T[132] Information: Generating both D & T register equations for signal fifo_d(2).D[133] Information: Expanding XOR equation found on signal fifo_d(2).T[133] Information: Generating both D & T register equations for signal fifo_d(3).D[134] Information: Expanding XOR equation found on signal fifo_d(3).T[134] Information: Generating both D & T register equations for signal fifo_d(4).D[135] Information: Expanding XOR equation found on signal fifo_d(4).T[135] Information: Generating both D & T register equations for signal fifo_d(5).D[136] Information: Expanding XOR equation found on signal fifo_d(5).T[136] Information: Generating both D & T register equations for signal fifo_d(6).D[137] Information: Expanding XOR equation found on signal fifo_d(6).T[137] Information: Generating both D & T register equations for signal fifo_d(7).D[138] Information: Expanding XOR equation found on signal fifo_d(7).T[138] Information: Generating both D & T register equations for signal fifo_read_l.D[146] Information: Expanding XOR equation found on signal fifo_read_l.T[146] Information: Generating both D & T register equations for signal \pump:count_0\.D Information: Expanding XOR equation found on signal \pump:count_0\.T Information: Generating both D & T register equations for signal \pump:count_1\.D Information: Expanding XOR equation found on signal \pump:count_1\.T Information: Generating both D & T register equations for signal \pump:pump_stateSBV_1\.D Information: Expanding XOR equation found on signal \pump:pump_stateSBV_1\.T Information: Generating both D & T register equations for signal \pump:pump_stateSBV_0\.D Information: Expanding XOR equation found on signal \pump:pump_stateSBV_0\.T Information: Generating both D & T register equations for signal \fr_imp:fr_stateSBV_0\.D Information: Expanding XOR equation found on signal \fr_imp:fr_stateSBV_0\.T Information: Generating both D & T register equations for signal fiber_to_ibus_buf_0.D Information: Expanding XOR equation found on signal fiber_to_ibus_buf_0.T Information: Generating both D & T register equations for signal fiber_to_ibus_buf_1.D Information: Expanding XOR equation found on signal fiber_to_ibus_buf_1.T Information: Generating both D & T register equations for signal fiber_to_ibus_buf_2.D Information: Expanding XOR equation found on signal fiber_to_ibus_buf_2.T Information: Generating both D & T register equations for signal fiber_to_ibus_buf_3.D Information: Expanding XOR equation found on signal fiber_to_ibus_buf_3.T Information: Generating both D & T register equations for signal fiber_to_ibus_buf_4.D Information: Expanding XOR equation found on signal fiber_to_ibus_buf_4.T Information: Generating both D & T register equations for signal fiber_to_ibus_buf_5.D Information: Expanding XOR equation found on signal fiber_to_ibus_buf_5.T Information: Generating both D & T register equations for signal fiber_to_ibus_buf_6.D Information: Expanding XOR equation found on signal fiber_to_ibus_buf_6.T Information: Generating both D & T register equations for signal fiber_to_ibus_buf_7.D Information: Expanding XOR equation found on signal fiber_to_ibus_buf_7.T Information: Generating both D & T register equations for signal fiber_to_ibus_buf_8.D Information: Expanding XOR equation found on signal fiber_to_ibus_buf_8.T Information: Generating both D & T register equations for signal fiber_to_ibus_buf_9.D Information: Expanding XOR equation found on signal fiber_to_ibus_buf_9.T Information: Generating both D & T register equations for signal fiber_to_ibus_buf_10.D Information: Expanding XOR equation found on signal fiber_to_ibus_buf_10.T Information: Generating both D & T register equations for signal fiber_to_ibus_buf_11.D Information: Expanding XOR equation found on signal fiber_to_ibus_buf_11.T Information: Generating both D & T register equations for signal fiber_to_ibus_buf_12.D Information: Expanding XOR equation found on signal fiber_to_ibus_buf_12.T Information: Generating both D & T register equations for signal fiber_to_ibus_buf_13.D Information: Expanding XOR equation found on signal fiber_to_ibus_buf_13.T Information: Generating both D & T register equations for signal fiber_to_ibus_buf_14.D Information: Expanding XOR equation found on signal fiber_to_ibus_buf_14.T Information: Generating both D & T register equations for signal fiber_to_ibus_buf_15.D Information: Expanding XOR equation found on signal fiber_to_ibus_buf_15.T Information: Generating both D & T register equations for signal \ibus_fi:timeout_0\.D Information: Expanding XOR equation found on signal \ibus_fi:timeout_0\.T Information: Generating both D & T register equations for signal \ibus_fi:timeout_1\.D Information: Expanding XOR equation found on signal \ibus_fi:timeout_1\.T Information: Generating both D & T register equations for signal \ibus_fi:timeout_2\.D Information: Expanding XOR equation found on signal \ibus_fi:timeout_2\.T Information: Generating both D & T register equations for signal \ibus_fi:timeout_3\.D Information: Expanding XOR equation found on signal \ibus_fi:timeout_3\.T Information: Generating both D & T register equations for signal refill_ibus_output_buf.D Information: Expanding XOR equation found on signal refill_ibus_output_buf.T Information: Generating both D & T register equations for signal data_pump_word_ready.D Information: Expanding XOR equation found on signal data_pump_word_ready.T Information: Generating both D & T register equations for signal \ibus_fi:read_stateSBV_1\.D Information: Expanding XOR equation found on signal \ibus_fi:read_stateSBV_1\.T Information: Generating both D & T register equations for signal \ibus_fi:read_stateSBV_0\.D Information: Expanding XOR equation found on signal \ibus_fi:read_stateSBV_0\.T Information: Generating both D & T register equations for signal \ibus_fo:stateSBV_2\.D Information: Expanding XOR equation found on signal \ibus_fo:stateSBV_2\.T Information: Generating both D & T register equations for signal \ibus_fo:stateSBV_1\.D Information: Expanding XOR equation found on signal \ibus_fo:stateSBV_1\.T Information: Generating both D & T register equations for signal \ibus_fo:stateSBV_0\.D Information: Expanding XOR equation found on signal \ibus_fo:stateSBV_0\.T Information: Generating both D & T register equations for signal \fi_reader:timeout_0\.D Information: Expanding XOR equation found on signal \fi_reader:timeout_0\.T Information: Generating both D & T register equations for signal \fi_reader:timeout_1\.D Information: Expanding XOR equation found on signal \fi_reader:timeout_1\.T Information: Generating both D & T register equations for signal \fi_reader:timeout_2\.D Information: Expanding XOR equation found on signal \fi_reader:timeout_2\.T Information: Generating both D & T register equations for signal \fi_reader:timeout_3\.D Information: Expanding XOR equation found on signal \fi_reader:timeout_3\.T Information: Generating both D & T register equations for signal fi_data_0.D Information: Expanding XOR equation found on signal fi_data_0.T Information: Generating both D & T register equations for signal fi_data_1.D Information: Expanding XOR equation found on signal fi_data_1.T Information: Generating both D & T register equations for signal fi_data_2.D Information: Expanding XOR equation found on signal fi_data_2.T Information: Generating both D & T register equations for signal fi_data_3.D Information: Expanding XOR equation found on signal fi_data_3.T Information: Generating both D & T register equations for signal fi_data_4.D Information: Expanding XOR equation found on signal fi_data_4.T Information: Generating both D & T register equations for signal fi_data_6.D Information: Expanding XOR equation found on signal fi_data_6.T Information: Generating both D & T register equations for signal fi_data_7.D Information: Expanding XOR equation found on signal fi_data_7.T Information: Generating both D & T register equations for signal fi_data_13.D Information: Expanding XOR equation found on signal fi_data_13.T Information: Generating both D & T register equations for signal fi_data_14.D Information: Expanding XOR equation found on signal fi_data_14.T Information: Generating both D & T register equations for signal fi_to_ibus_req.D Information: Expanding XOR equation found on signal fi_to_ibus_req.T Information: Generating both D & T register equations for signal fi_data_5.D Information: Expanding XOR equation found on signal fi_data_5.T Information: Generating both D & T register equations for signal fi_data_8.D Information: Expanding XOR equation found on signal fi_data_8.T Information: Generating both D & T register equations for signal fi_data_9.D Information: Expanding XOR equation found on signal fi_data_9.T Information: Generating both D & T register equations for signal fi_data_10.D Information: Expanding XOR equation found on signal fi_data_10.T Information: Generating both D & T register equations for signal fi_data_11.D Information: Expanding XOR equation found on signal fi_data_11.T Information: Generating both D & T register equations for signal fi_data_12.D Information: Expanding XOR equation found on signal fi_data_12.T Information: Generating both D & T register equations for signal fi_data_15.D Information: Expanding XOR equation found on signal fi_data_15.T Information: Generating both D & T register equations for signal reset_fifo.D Information: Expanding XOR equation found on signal reset_fifo.T Information: Generating both D & T register equations for signal \fi_reader:this_is_a_ctrl_transaction\.D Information: Expanding XOR equation found on signal \fi_reader:this_is_a_ctrl_transaction\.T Information: Generating both D & T register equations for signal fi_to_ibus_ack.D Information: Expanding XOR equation found on signal fi_to_ibus_ack.T Information: Generating both D & T register equations for signal \fi_reader:fi_read_stateSBV_2\.D Information: Expanding XOR equation found on signal \fi_reader:fi_read_stateSBV_2\.T Information: Generating both D & T register equations for signal \fi_reader:fi_read_stateSBV_1\.D Information: Expanding XOR equation found on signal \fi_reader:fi_read_stateSBV_1\.T Information: Generating both D & T register equations for signal \fi_reader:fi_read_stateSBV_0\.D Information: Expanding XOR equation found on signal \fi_reader:fi_read_stateSBV_0\.T Information: Generating both D & T register equations for signal \ibus_reader:timeout_0\.D Information: Expanding XOR equation found on signal \ibus_reader:timeout_0\.T Information: Generating both D & T register equations for signal \ibus_reader:timeout_1\.D Information: Expanding XOR equation found on signal \ibus_reader:timeout_1\.T Information: Generating both D & T register equations for signal \ibus_reader:timeout_2\.D Information: Expanding XOR equation found on signal \ibus_reader:timeout_2\.T Information: Generating both D & T register equations for signal \ibus_reader:timeout_3\.D Information: Expanding XOR equation found on signal \ibus_reader:timeout_3\.T Information: Generating both D & T register equations for signal data_to_fo_0.D Information: Expanding XOR equation found on signal data_to_fo_0.T Information: Generating both D & T register equations for signal data_to_fo_1.D Information: Expanding XOR equation found on signal data_to_fo_1.T Information: Generating both D & T register equations for signal data_to_fo_2.D Information: Expanding XOR equation found on signal data_to_fo_2.T Information: Generating both D & T register equations for signal data_to_fo_3.D Information: Expanding XOR equation found on signal data_to_fo_3.T Information: Generating both D & T register equations for signal data_to_fo_4.D Information: Expanding XOR equation found on signal data_to_fo_4.T Information: Generating both D & T register equations for signal data_to_fo_5.D Information: Expanding XOR equation found on signal data_to_fo_5.T Information: Generating both D & T register equations for signal data_to_fo_6.D Information: Expanding XOR equation found on signal data_to_fo_6.T Information: Generating both D & T register equations for signal data_to_fo_7.D Information: Expanding XOR equation found on signal data_to_fo_7.T Information: Generating both D & T register equations for signal data_to_fo_8.D Information: Expanding XOR equation found on signal data_to_fo_8.T Information: Generating both D & T register equations for signal data_to_fo_9.D Information: Expanding XOR equation found on signal data_to_fo_9.T Information: Generating both D & T register equations for signal data_to_fo_10.D Information: Expanding XOR equation found on signal data_to_fo_10.T Information: Generating both D & T register equations for signal data_to_fo_11.D Information: Expanding XOR equation found on signal data_to_fo_11.T Information: Generating both D & T register equations for signal data_to_fo_12.D Information: Expanding XOR equation found on signal data_to_fo_12.T Information: Generating both D & T register equations for signal data_to_fo_13.D Information: Expanding XOR equation found on signal data_to_fo_13.T Information: Generating both D & T register equations for signal data_to_fo_14.D Information: Expanding XOR equation found on signal data_to_fo_14.T Information: Generating both D & T register equations for signal data_to_fo_15.D Information: Expanding XOR equation found on signal data_to_fo_15.T Information: Generating both D & T register equations for signal write_to_fo_ack.D Information: Expanding XOR equation found on signal write_to_fo_ack.T Information: Generating both D & T register equations for signal \ibus_reader:iu_readSBV_1\.D Information: Expanding XOR equation found on signal \ibus_reader:iu_readSBV_1\.T Information: Generating both D & T register equations for signal \ibus_reader:iu_readSBV_0\.D Information: Expanding XOR equation found on signal \ibus_reader:iu_readSBV_0\.T Information: Generating both D & T register equations for signal write_to_fo_req.D Information: Expanding XOR equation found on signal write_to_fo_req.T Information: Optimizing logic without changing polarity for signals: \fi_reader:fi_read_stateSBV_0\.T \fi_reader:fi_read_stateSBV_1\.T \fi_reader:fi_read_stateSBV_2\.T \fi_reader:this_is_a_ctrl_transaction\.T \fi_reader:timeout_0\.T \fi_reader:timeout_1\.T \fi_reader:timeout_2\.T \fi_reader:timeout_3\.T \fr_imp:fr_stateSBV_0\.T \ibus_fi:read_stateSBV_0\.T \ibus_fi:read_stateSBV_1\.T \ibus_fi:timeout_0\.T \ibus_fi:timeout_1\.T \ibus_fi:timeout_2\.T \ibus_fi:timeout_3\.T \ibus_fo:stateSBV_0\.T \ibus_fo:stateSBV_1\.T \ibus_fo:stateSBV_2\.T \ibus_reader:iu_readSBV_0\.T \ibus_reader:iu_readSBV_1\.T \ibus_reader:timeout_0\.T \ibus_reader:timeout_1\.T \ibus_reader:timeout_2\.T \ibus_reader:timeout_3\.T \pump:count_0\.T \pump:count_1\.T \pump:pump_stateSBV_0\.T \pump:pump_stateSBV_1\.T ao_from_pc_strobe.T ao_to_pc_ack.T data_pump_word_ready.T data_to_fo_0.T data_to_fo_1.T data_to_fo_10.T data_to_fo_11.T data_to_fo_12.T data_to_fo_13.T data_to_fo_14.T data_to_fo_15.T data_to_fo_2.T data_to_fo_3.T data_to_fo_4.T data_to_fo_5.T data_to_fo_6.T data_to_fo_7.T data_to_fo_8.T data_to_fo_9.T fi_data_0.T fi_data_1.T fi_data_10.T fi_data_11.T fi_data_12.T fi_data_13.T fi_data_14.T fi_data_15.T fi_data_2.T fi_data_3.T fi_data_4.T fi_data_5.T fi_data_6.T fi_data_7.T fi_data_8.T fi_data_9.T fi_to_ibus_ack.T fi_to_ibus_req.T fiber_to_ibus_buf_0.T fiber_to_ibus_buf_1.T fiber_to_ibus_buf_10.T fiber_to_ibus_buf_11.T fiber_to_ibus_buf_12.T fiber_to_ibus_buf_13.T fiber_to_ibus_buf_14.T fiber_to_ibus_buf_15.T fiber_to_ibus_buf_2.T fiber_to_ibus_buf_3.T fiber_to_ibus_buf_4.T fiber_to_ibus_buf_5.T fiber_to_ibus_buf_6.T fiber_to_ibus_buf_7.T fiber_to_ibus_buf_8.T fiber_to_ibus_buf_9.T fifo_d(0).T fifo_d(1).T fifo_d(2).T fifo_d(3).T fifo_d(4).T fifo_d(5).T fifo_d(6).T fifo_d(7).T fifo_d(8).T fifo_read_l.T fifo_reset_l.T fifo_write_l.T fo_ckw.T fo_d(0).T fo_d(1).T fo_d(2).T fo_d(3).T fo_d(4).T fo_d(5).T fo_d(6).T fo_d(7).T fo_ena_l.T id(0).T id(1).T id(10).T id(11).T id(12).T id(13).T id(14).T id(15).T id(2).T id(3).T id(4).T id(5).T id(6).T id(7).T id(8).T id(9).T refill_ibus_output_buf.T reset_fifo.T write_to_fo_ack.T write_to_fo_req.T Information: Optimizing logic using best output polarity for signals: \fi_reader:fi_read_stateSBV_0\.D \fi_reader:fi_read_stateSBV_1\.D \fi_reader:fi_read_stateSBV_2\.D \fi_reader:this_is_a_ctrl_transaction\.D \fi_reader:timeout_0\.D \fi_reader:timeout_1\.D \fi_reader:timeout_2\.D \fi_reader:timeout_3\.D \ibus_fi:read_stateSBV_0\.D \ibus_fi:read_stateSBV_1\.D \ibus_fi:timeout_0\.D \ibus_fi:timeout_1\.D \ibus_fi:timeout_2\.D \ibus_fi:timeout_3\.D \ibus_fo:stateSBV_1\.D \ibus_fo:stateSBV_2\.D \ibus_reader:iu_readSBV_0\.D \ibus_reader:iu_readSBV_1\.D \ibus_reader:timeout_0\.D \ibus_reader:timeout_1\.D \ibus_reader:timeout_2\.D \ibus_reader:timeout_3\.D \pump:count_0\.D \pump:count_1\.D \pump:pump_stateSBV_0\.D \pump:pump_stateSBV_1\.D ao_from_pc_strobe.D ao_to_pc_ack.D data_to_fo_0.D data_to_fo_1.D data_to_fo_10.D data_to_fo_11.D data_to_fo_12.D data_to_fo_13.D data_to_fo_14.D data_to_fo_15.D data_to_fo_2.D data_to_fo_3.D data_to_fo_4.D data_to_fo_5.D data_to_fo_6.D data_to_fo_7.D data_to_fo_8.D data_to_fo_9.D fi_data_0.D fi_data_1.D fi_data_10.D fi_data_11.D fi_data_12.D fi_data_13.D fi_data_14.D fi_data_15.D fi_data_2.D fi_data_3.D fi_data_4.D fi_data_5.D fi_data_6.D fi_data_7.D fi_data_8.D fi_data_9.D fiber_to_ibus_buf_0.D fiber_to_ibus_buf_1.D fiber_to_ibus_buf_10.D fiber_to_ibus_buf_11.D fiber_to_ibus_buf_12.D fiber_to_ibus_buf_13.D fiber_to_ibus_buf_14.D fiber_to_ibus_buf_15.D fiber_to_ibus_buf_2.D fiber_to_ibus_buf_3.D fiber_to_ibus_buf_4.D fiber_to_ibus_buf_5.D fiber_to_ibus_buf_6.D fiber_to_ibus_buf_7.D fiber_to_ibus_buf_8.D fiber_to_ibus_buf_9.D fifo_d(0).D fifo_d(1).D fifo_d(2).D fifo_d(3).D fifo_d(4).D fifo_d(5).D fifo_d(6).D fifo_d(7).D fifo_d(8).D fifo_read_l.D fifo_reset_l.D fifo_write_l.D fo_d(0).D fo_d(1).D fo_d(2).D fo_d(3).D fo_d(4).D fo_d(5).D fo_d(6).D fo_d(7).D fo_d(8).D fo_d(9).D fo_ena_l.D id(0).D id(1).D id(10).D id(11).D id(12).D id(13).D id(14).D id(15).D id(2).D id(3).D id(4).D id(5).D id(6).D id(7).D id(8).D id(9).D refill_ibus_output_buf.D write_to_fo_ack.D write_to_fo_req.D Information: Selected logic optimization OFF for signals: \fi_reader:fi_read_stateSBV_0\.C \fi_reader:fi_read_stateSBV_1\.C \fi_reader:fi_read_stateSBV_2\.C \fi_reader:this_is_a_ctrl_transaction\.AR \fi_reader:this_is_a_ctrl_transaction\.C \fi_reader:timeout_0\.C \fi_reader:timeout_1\.C \fi_reader:timeout_2\.C \fi_reader:timeout_3\.C \fr_imp:fr_stateSBV_0\.D \fr_imp:fr_stateSBV_0\.C \ibus_fi:read_stateSBV_0\.C \ibus_fi:read_stateSBV_1\.C \ibus_fi:timeout_0\.C \ibus_fi:timeout_1\.C \ibus_fi:timeout_2\.C \ibus_fi:timeout_3\.C \ibus_fo:stateSBV_0\.D \ibus_fo:stateSBV_0\.C \ibus_fo:stateSBV_1\.C \ibus_fo:stateSBV_2\.C \ibus_reader:iu_readSBV_0\.C \ibus_reader:iu_readSBV_1\.C \ibus_reader:timeout_0\.C \ibus_reader:timeout_1\.C \ibus_reader:timeout_2\.C \ibus_reader:timeout_3\.C \pump:count_0\.C \pump:count_1\.C \pump:pump_stateSBV_0\.C \pump:pump_stateSBV_1\.C ao_from_pc_strobe.C ao_to_pc_ack.C data_pump_word_ready.D data_pump_word_ready.C data_to_fo_0.C data_to_fo_1.C data_to_fo_10.C data_to_fo_11.C data_to_fo_12.C data_to_fo_13.C data_to_fo_14.C data_to_fo_15.C data_to_fo_2.C data_to_fo_3.C data_to_fo_4.C data_to_fo_5.C data_to_fo_6.C data_to_fo_7.C data_to_fo_8.C data_to_fo_9.C debug fi_data_0.C fi_data_1.C fi_data_10.C fi_data_11.C fi_data_12.C fi_data_13.C fi_data_14.C fi_data_15.C fi_data_2.C fi_data_3.C fi_data_4.C fi_data_5.C fi_data_6.C fi_data_7.C fi_data_8.C fi_data_9.C fi_to_ibus_ack.D fi_to_ibus_ack.C fi_to_ibus_req.D fi_to_ibus_req.C fiber_to_ibus_buf_0.C fiber_to_ibus_buf_1.C fiber_to_ibus_buf_10.C fiber_to_ibus_buf_11.C fiber_to_ibus_buf_12.C fiber_to_ibus_buf_13.C fiber_to_ibus_buf_14.C fiber_to_ibus_buf_15.C fiber_to_ibus_buf_2.C fiber_to_ibus_buf_3.C fiber_to_ibus_buf_4.C fiber_to_ibus_buf_5.C fiber_to_ibus_buf_6.C fiber_to_ibus_buf_7.C fiber_to_ibus_buf_8.C fiber_to_ibus_buf_9.C fifo_d(0).C fifo_d(1).C fifo_d(2).C fifo_d(3).C fifo_d(4).C fifo_d(5).C fifo_d(6).C fifo_d(7).C fifo_d(8).C fifo_read_l.AP fifo_read_l.C fifo_reset_l.AP fifo_reset_l.C fifo_write_l.AP fifo_write_l.C fo_ckw.D fo_ckw.C fo_d(0).C fo_d(1).C fo_d(2).C fo_d(3).C fo_d(4).C fo_d(5).C fo_d(6).C fo_d(7).C fo_d(8).T fo_d(8).C fo_d(9).T fo_d(9).C fo_ena_l.C fo_enn_l fo_foto fo_mode fr_mode fr_ref_clk fr_rf id(0).C id(1).C id(10).C id(11).C id(12).C id(13).C id(14).C id(15).C id(2).C id(3).C id(4).C id(5).C id(6).C id(7).C id(8).C id(9).C refill_ibus_output_buf.AR refill_ibus_output_buf.C reset_fifo.D reset_fifo.C write_to_fo_ack.C write_to_fo_req.C Summary: Error Count = 0 Warning Count = 0 Completed Successfully ---------------------------------------------------------------------------- PLD Optimizer Software: MINOPT.EXE 01/NOV/1999 [v4.02 ] 6.0.1 IR 18 LOGIC MINIMIZATION () Messages: Summary: Error Count = 0 Warning Count = 0 Completed Successfully ---------------------------------------------------------------------------- PLD Optimizer Software: DSGNOPT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 OPTIMIZATION OPTIONS (12:09:43) Messages: Information: Optimizing Banked Preset/Reset requirements. Information: Selecting D register equation as minimal for signal fifo_reset_l Information: Inverting Preset/Reset & output logic polarity for fifo_write_l. Information: Selecting T register equation as minimal for signal fifo_write_l Information: Selecting D register equation as minimal for signal \fi_reader:this_is_a_ctrl_transaction\ Information: Selecting D register equation as minimal for signal fifo_read_l Information: Inverting Preset/Reset & output logic polarity for refill_ibus_output_buf. Information: Selecting D register equation as minimal for signal refill_ibus_output_buf Information: Optimizing logic without changing polarity for signals: \fi_reader:fi_read_stateSBV_0\.D \fi_reader:fi_read_stateSBV_0\.T \fi_reader:fi_read_stateSBV_1\.D \fi_reader:fi_read_stateSBV_1\.T \fi_reader:fi_read_stateSBV_2\.D \fi_reader:fi_read_stateSBV_2\.T \fi_reader:this_is_a_ctrl_transaction\.D \fi_reader:timeout_0\.D \fi_reader:timeout_0\.T \fi_reader:timeout_1\.D \fi_reader:timeout_1\.T \fi_reader:timeout_2\.D \fi_reader:timeout_2\.T \fi_reader:timeout_3\.D \fi_reader:timeout_3\.T \fr_imp:fr_stateSBV_0\.T \ibus_fi:read_stateSBV_0\.D \ibus_fi:read_stateSBV_0\.T \ibus_fi:read_stateSBV_1\.D \ibus_fi:read_stateSBV_1\.T \ibus_fi:timeout_0\.D \ibus_fi:timeout_0\.T \ibus_fi:timeout_1\.D \ibus_fi:timeout_1\.T \ibus_fi:timeout_2\.D \ibus_fi:timeout_2\.T \ibus_fi:timeout_3\.D \ibus_fi:timeout_3\.T \ibus_fo:stateSBV_0\.T \ibus_fo:stateSBV_1\.D \ibus_fo:stateSBV_1\.T \ibus_fo:stateSBV_2\.D \ibus_fo:stateSBV_2\.T \ibus_reader:iu_readSBV_0\.D \ibus_reader:iu_readSBV_0\.T \ibus_reader:iu_readSBV_1\.D \ibus_reader:iu_readSBV_1\.T \ibus_reader:timeout_0\.D \ibus_reader:timeout_0\.T \ibus_reader:timeout_1\.D \ibus_reader:timeout_1\.T \ibus_reader:timeout_2\.D \ibus_reader:timeout_2\.T \ibus_reader:timeout_3\.D \ibus_reader:timeout_3\.T \pump:count_0\.D \pump:count_0\.T \pump:count_1\.D \pump:count_1\.T \pump:pump_stateSBV_0\.D \pump:pump_stateSBV_0\.T \pump:pump_stateSBV_1\.D \pump:pump_stateSBV_1\.T ao_from_pc_strobe.D ao_from_pc_strobe.T ao_to_pc_ack.D ao_to_pc_ack.T data_pump_word_ready.T data_to_fo_0.D data_to_fo_0.T data_to_fo_1.D data_to_fo_1.T data_to_fo_10.D data_to_fo_10.T data_to_fo_11.D data_to_fo_11.T data_to_fo_12.D data_to_fo_12.T data_to_fo_13.D data_to_fo_13.T data_to_fo_14.D data_to_fo_14.T data_to_fo_15.D data_to_fo_15.T data_to_fo_2.D data_to_fo_2.T data_to_fo_3.D data_to_fo_3.T data_to_fo_4.D data_to_fo_4.T data_to_fo_5.D data_to_fo_5.T data_to_fo_6.D data_to_fo_6.T data_to_fo_7.D data_to_fo_7.T data_to_fo_8.D data_to_fo_8.T data_to_fo_9.D data_to_fo_9.T fi_data_0.D fi_data_0.T fi_data_1.D fi_data_1.T fi_data_10.D fi_data_10.T fi_data_11.D fi_data_11.T fi_data_12.D fi_data_12.T fi_data_13.D fi_data_13.T fi_data_14.D fi_data_14.T fi_data_15.D fi_data_15.T fi_data_2.D fi_data_2.T fi_data_3.D fi_data_3.T fi_data_4.D fi_data_4.T fi_data_5.D fi_data_5.T fi_data_6.D fi_data_6.T fi_data_7.D fi_data_7.T fi_data_8.D fi_data_8.T fi_data_9.D fi_data_9.T fi_to_ibus_ack.T fi_to_ibus_req.T fiber_to_ibus_buf_0.D fiber_to_ibus_buf_0.T fiber_to_ibus_buf_1.D fiber_to_ibus_buf_1.T fiber_to_ibus_buf_10.D fiber_to_ibus_buf_10.T fiber_to_ibus_buf_11.D fiber_to_ibus_buf_11.T fiber_to_ibus_buf_12.D fiber_to_ibus_buf_12.T fiber_to_ibus_buf_13.D fiber_to_ibus_buf_13.T fiber_to_ibus_buf_14.D fiber_to_ibus_buf_14.T fiber_to_ibus_buf_15.D fiber_to_ibus_buf_15.T fiber_to_ibus_buf_2.D fiber_to_ibus_buf_2.T fiber_to_ibus_buf_3.D fiber_to_ibus_buf_3.T fiber_to_ibus_buf_4.D fiber_to_ibus_buf_4.T fiber_to_ibus_buf_5.D fiber_to_ibus_buf_5.T fiber_to_ibus_buf_6.D fiber_to_ibus_buf_6.T fiber_to_ibus_buf_7.D fiber_to_ibus_buf_7.T fiber_to_ibus_buf_8.D fiber_to_ibus_buf_8.T fiber_to_ibus_buf_9.D fiber_to_ibus_buf_9.T fifo_d(0).D fifo_d(0).T fifo_d(1).D fifo_d(1).T fifo_d(2).D fifo_d(2).T fifo_d(3).D fifo_d(3).T fifo_d(4).D fifo_d(4).T fifo_d(5).D fifo_d(5).T fifo_d(6).D fifo_d(6).T fifo_d(7).D fifo_d(7).T fifo_d(8).D fifo_d(8).T fifo_reset_l.D fifo_write_l.T fo_d(0).D fo_d(0).T fo_d(1).D fo_d(1).T fo_d(2).D fo_d(2).T fo_d(3).D fo_d(3).T fo_d(4).D fo_d(4).T fo_d(5).D fo_d(5).T fo_d(6).D fo_d(6).T fo_d(7).D fo_d(7).T fo_d(8).D fo_d(9).D fo_ena_l.D fo_ena_l.T id(0).D id(0).T id(1).D id(1).T id(10).D id(10).T id(11).D id(11).T id(12).D id(12).T id(13).D id(13).T id(14).D id(14).T id(15).D id(15).T id(2).D id(2).T id(3).D id(3).T id(4).D id(4).T id(5).D id(5).T id(6).D id(6).T id(7).D id(7).T id(8).D id(8).T id(9).D id(9).T refill_ibus_output_buf.D reset_fifo.T write_to_fo_ack.D write_to_fo_ack.T write_to_fo_req.D write_to_fo_req.T Information: Selected logic optimization OFF for signals: \fi_reader:fi_read_stateSBV_0\.C \fi_reader:fi_read_stateSBV_1\.C \fi_reader:fi_read_stateSBV_2\.C \fi_reader:this_is_a_ctrl_transaction\.AP \fi_reader:this_is_a_ctrl_transaction\.AR \fi_reader:this_is_a_ctrl_transaction\.C \fi_reader:timeout_0\.C \fi_reader:timeout_1\.C \fi_reader:timeout_2\.C \fi_reader:timeout_3\.C \fr_imp:fr_stateSBV_0\.D \fr_imp:fr_stateSBV_0\.C \ibus_fi:read_stateSBV_0\.C \ibus_fi:read_stateSBV_1\.C \ibus_fi:timeout_0\.C \ibus_fi:timeout_1\.C \ibus_fi:timeout_2\.C \ibus_fi:timeout_3\.C \ibus_fo:stateSBV_0\.D \ibus_fo:stateSBV_0\.C \ibus_fo:stateSBV_1\.C \ibus_fo:stateSBV_2\.C \ibus_reader:iu_readSBV_0\.C \ibus_reader:iu_readSBV_1\.C \ibus_reader:timeout_0\.C \ibus_reader:timeout_1\.C \ibus_reader:timeout_2\.C \ibus_reader:timeout_3\.C \pump:count_0\.C \pump:count_1\.C \pump:pump_stateSBV_0\.C \pump:pump_stateSBV_1\.C ao_from_pc_strobe.C ao_to_pc_ack.C data_pump_word_ready.D data_pump_word_ready.C data_to_fo_0.C data_to_fo_1.C data_to_fo_10.C data_to_fo_11.C data_to_fo_12.C data_to_fo_13.C data_to_fo_14.C data_to_fo_15.C data_to_fo_2.C data_to_fo_3.C data_to_fo_4.C data_to_fo_5.C data_to_fo_6.C data_to_fo_7.C data_to_fo_8.C data_to_fo_9.C debug fi_data_0.C fi_data_1.C fi_data_10.C fi_data_11.C fi_data_12.C fi_data_13.C fi_data_14.C fi_data_15.C fi_data_2.C fi_data_3.C fi_data_4.C fi_data_5.C fi_data_6.C fi_data_7.C fi_data_8.C fi_data_9.C fi_to_ibus_ack.D fi_to_ibus_ack.C fi_to_ibus_req.D fi_to_ibus_req.C fiber_to_ibus_buf_0.C fiber_to_ibus_buf_1.C fiber_to_ibus_buf_10.C fiber_to_ibus_buf_11.C fiber_to_ibus_buf_12.C fiber_to_ibus_buf_13.C fiber_to_ibus_buf_14.C fiber_to_ibus_buf_15.C fiber_to_ibus_buf_2.C fiber_to_ibus_buf_3.C fiber_to_ibus_buf_4.C fiber_to_ibus_buf_5.C fiber_to_ibus_buf_6.C fiber_to_ibus_buf_7.C fiber_to_ibus_buf_8.C fiber_to_ibus_buf_9.C fifo_d(0).C fifo_d(1).C fifo_d(2).C fifo_d(3).C fifo_d(4).C fifo_d(5).C fifo_d(6).C fifo_d(7).C fifo_d(8).C fifo_read_l.D fifo_read_l.AP fifo_read_l.AR fifo_read_l.C fifo_reset_l.AP fifo_reset_l.AR fifo_reset_l.C fifo_write_l.AP fifo_write_l.AR fifo_write_l.C fo_ckw.D fo_ckw.T fo_ckw.C fo_d(0).C fo_d(1).C fo_d(2).C fo_d(3).C fo_d(4).C fo_d(5).C fo_d(6).C fo_d(7).C fo_d(8).T fo_d(8).C fo_d(9).T fo_d(9).C fo_ena_l.C fo_enn_l fo_foto fo_mode fr_mode fr_ref_clk fr_rf id(0).C id(1).C id(10).C id(11).C id(12).C id(13).C id(14).C id(15).C id(2).C id(3).C id(4).C id(5).C id(6).C id(7).C id(8).C id(9).C refill_ibus_output_buf.AP refill_ibus_output_buf.AR refill_ibus_output_buf.C reset_fifo.D reset_fifo.C write_to_fo_ack.C write_to_fo_req.C Summary: Error Count = 0 Warning Count = 0 Completed Successfully ---------------------------------------------------------------------------- PLD Optimizer Software: MINOPT.EXE 01/NOV/1999 [v4.02 ] 6.0.1 IR 18 LOGIC MINIMIZATION () Messages: Summary: Error Count = 0 Warning Count = 0 Completed Successfully ---------------------------------------------------------------------------- PLD Optimizer Software: DSGNOPT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 OPTIMIZATION OPTIONS (12:09:47) Messages: Information: Selecting T register equation as minimal for signal id(0) Information: Selecting T register equation as minimal for signal id(1) Information: Selecting T register equation as minimal for signal id(2) Information: Selecting T register equation as minimal for signal id(3) Information: Selecting T register equation as minimal for signal id(4) Information: Selecting T register equation as minimal for signal id(5) Information: Selecting T register equation as minimal for signal id(6) Information: Selecting T register equation as minimal for signal id(7) Information: Selecting T register equation as minimal for signal id(8) Information: Selecting T register equation as minimal for signal id(9) Information: Selecting T register equation as minimal for signal id(10) Information: Selecting T register equation as minimal for signal id(11) Information: Selecting T register equation as minimal for signal id(12) Information: Selecting T register equation as minimal for signal id(13) Information: Selecting T register equation as minimal for signal id(14) Information: Selecting T register equation as minimal for signal id(15) Information: Selecting D register equation as minimal for signal ao_from_pc_strobe Information: Selecting D register equation as minimal for signal ao_to_pc_ack Information: Selecting T register equation as minimal for signal fo_d(0) Information: Selecting T register equation as minimal for signal fo_d(1) Information: Selecting T register equation as minimal for signal fo_d(2) Information: Selecting T register equation as minimal for signal fo_d(3) Information: Selecting T register equation as minimal for signal fo_d(4) Information: Selecting T register equation as minimal for signal fo_d(5) Information: Selecting T register equation as minimal for signal fo_d(6) Information: Selecting T register equation as minimal for signal fo_d(7) Information: Selecting T register equation as minimal for signal fo_d(8) Information: Selecting T register equation as minimal for signal fo_d(9) Information: Selecting D register equation as minimal for signal fo_ena_l Information: Selecting D register equation as minimal for signal fo_ckw Information: Selecting T register equation as minimal for signal fifo_d(8) Information: Selecting T register equation as minimal for signal fifo_d(0) Information: Selecting T register equation as minimal for signal fifo_d(1) Information: Selecting T register equation as minimal for signal fifo_d(2) Information: Selecting T register equation as minimal for signal fifo_d(3) Information: Selecting T register equation as minimal for signal fifo_d(4) Information: Selecting T register equation as minimal for signal fifo_d(5) Information: Selecting T register equation as minimal for signal fifo_d(6) Information: Selecting T register equation as minimal for signal fifo_d(7) Information: Selecting D register equation as minimal for signal write_to_fo_req Information: Selecting T register equation as minimal for signal write_to_fo_ack Information: Selecting D register equation as minimal for signal reset_fifo Information: Selecting T register equation as minimal for signal fiber_to_ibus_buf_9 Information: Selecting T register equation as minimal for signal fiber_to_ibus_buf_8 Information: Selecting T register equation as minimal for signal fiber_to_ibus_buf_7 Information: Selecting T register equation as minimal for signal fiber_to_ibus_buf_6 Information: Selecting T register equation as minimal for signal fiber_to_ibus_buf_5 Information: Selecting T register equation as minimal for signal fiber_to_ibus_buf_4 Information: Selecting T register equation as minimal for signal fiber_to_ibus_buf_3 Information: Selecting T register equation as minimal for signal fiber_to_ibus_buf_2 Information: Selecting T register equation as minimal for signal fiber_to_ibus_buf_15 Information: Selecting T register equation as minimal for signal fiber_to_ibus_buf_14 Information: Selecting T register equation as minimal for signal fiber_to_ibus_buf_13 Information: Selecting T register equation as minimal for signal fiber_to_ibus_buf_12 Information: Selecting T register equation as minimal for signal fiber_to_ibus_buf_11 Information: Selecting T register equation as minimal for signal fiber_to_ibus_buf_10 Information: Selecting T register equation as minimal for signal fiber_to_ibus_buf_1 Information: Selecting T register equation as minimal for signal fiber_to_ibus_buf_0 Information: Selecting D register equation as minimal for signal fi_to_ibus_req Information: Selecting D register equation as minimal for signal fi_to_ibus_ack Information: Selecting T register equation as minimal for signal fi_data_9 Information: Selecting T register equation as minimal for signal fi_data_8 Information: Selecting T register equation as minimal for signal fi_data_7 Information: Selecting T register equation as minimal for signal fi_data_6 Information: Selecting T register equation as minimal for signal fi_data_5 Information: Selecting T register equation as minimal for signal fi_data_4 Information: Selecting T register equation as minimal for signal fi_data_3 Information: Selecting T register equation as minimal for signal fi_data_2 Information: Selecting T register equation as minimal for signal fi_data_15 Information: Selecting T register equation as minimal for signal fi_data_14 Information: Selecting T register equation as minimal for signal fi_data_13 Information: Selecting T register equation as minimal for signal fi_data_12 Information: Selecting T register equation as minimal for signal fi_data_11 Information: Selecting T register equation as minimal for signal fi_data_10 Information: Selecting T register equation as minimal for signal fi_data_1 Information: Selecting T register equation as minimal for signal fi_data_0 Information: Selecting T register equation as minimal for signal data_to_fo_9 Information: Selecting T register equation as minimal for signal data_to_fo_8 Information: Selecting T register equation as minimal for signal data_to_fo_7 Information: Selecting T register equation as minimal for signal data_to_fo_6 Information: Selecting T register equation as minimal for signal data_to_fo_5 Information: Selecting T register equation as minimal for signal data_to_fo_4 Information: Selecting T register equation as minimal for signal data_to_fo_3 Information: Selecting T register equation as minimal for signal data_to_fo_2 Information: Selecting T register equation as minimal for signal data_to_fo_15 Information: Selecting T register equation as minimal for signal data_to_fo_14 Information: Selecting T register equation as minimal for signal data_to_fo_13 Information: Selecting T register equation as minimal for signal data_to_fo_12 Information: Selecting T register equation as minimal for signal data_to_fo_11 Information: Selecting T register equation as minimal for signal data_to_fo_10 Information: Selecting T register equation as minimal for signal data_to_fo_1 Information: Selecting T register equation as minimal for signal data_to_fo_0 Information: Selecting D register equation as minimal for signal data_pump_word_ready Information: Selecting D register equation as minimal for signal \pump:pump_stateSBV_1\ Information: Selecting D register equation as minimal for signal \pump:pump_stateSBV_0\ Information: Selecting D register equation as minimal for signal \pump:count_1\ Information: Selecting D register equation as minimal for signal \pump:count_0\ Information: Selecting T register equation as minimal for signal \ibus_reader:timeout_3\ Information: Selecting T register equation as minimal for signal \ibus_reader:timeout_2\ Information: Selecting T register equation as minimal for signal \ibus_reader:timeout_1\ Information: Selecting D register equation as minimal for signal \ibus_reader:timeout_0\ Information: Selecting D register equation as minimal for signal \ibus_reader:iu_readSBV_1\ Information: Selecting T register equation as minimal for signal \ibus_reader:iu_readSBV_0\ Information: Selecting D register equation as minimal for signal \ibus_fo:stateSBV_2\ Information: Selecting D register equation as minimal for signal \ibus_fo:stateSBV_1\ Information: Selecting D register equation as minimal for signal \ibus_fo:stateSBV_0\ Information: Selecting T register equation as minimal for signal \ibus_fi:timeout_3\ Information: Selecting T register equation as minimal for signal \ibus_fi:timeout_2\ Information: Selecting T register equation as minimal for signal \ibus_fi:timeout_1\ Information: Selecting D register equation as minimal for signal \ibus_fi:timeout_0\ Information: Selecting T register equation as minimal for signal \ibus_fi:read_stateSBV_1\ Information: Selecting D register equation as minimal for signal \ibus_fi:read_stateSBV_0\ Information: Selecting D register equation as minimal for signal \fr_imp:fr_stateSBV_0\ Information: Selecting D register equation as minimal for signal \fi_reader:timeout_3\ Information: Selecting T register equation as minimal for signal \fi_reader:timeout_2\ Information: Selecting T register equation as minimal for signal \fi_reader:timeout_1\ Information: Selecting D register equation as minimal for signal \fi_reader:timeout_0\ Information: Selecting T register equation as minimal for signal \fi_reader:fi_read_stateSBV_2\ Information: Selecting D register equation as minimal for signal \fi_reader:fi_read_stateSBV_1\ Information: Selecting T register equation as minimal for signal \fi_reader:fi_read_stateSBV_0\ Summary: Error Count = 0 Warning Count = 0 Completed Successfully ---------------------------------------------------------------------------- PLD Compiler Software: C37KFIT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 DESIGN EQUATIONS (12:09:49) \fi_reader:fi_read_stateSBV_0\.T = \fi_reader:fi_read_stateSBV_0\.Q * \fi_reader:timeout_0\.Q * \fi_reader:timeout_1\.Q * \fi_reader:timeout_2\.Q * \fi_reader:timeout_3\.Q * /ao_from_pc_ack * fi_to_ibus_req.Q + \fi_reader:fi_read_stateSBV_0\.Q * /\fi_reader:fi_read_stateSBV_1\.Q * \fi_reader:timeout_0\.Q * \fi_reader:timeout_1\.Q * \fi_reader:timeout_2\.Q * \fi_reader:timeout_3\.Q * /ao_from_pc_ack + \fi_reader:fi_read_stateSBV_0\.Q * /\fi_reader:fi_read_stateSBV_2\.Q * \fi_reader:timeout_0\.Q * \fi_reader:timeout_1\.Q * \fi_reader:timeout_2\.Q * \fi_reader:timeout_3\.Q + /\fi_reader:fi_read_stateSBV_0\.Q * \fi_reader:fi_read_stateSBV_1\.Q * \fi_reader:fi_read_stateSBV_2\.Q * /fi_to_ibus_req.Q + \fi_reader:fi_read_stateSBV_0\.Q * /\fi_reader:fi_read_stateSBV_1\.Q * /\fi_reader:fi_read_stateSBV_2\.Q + \fi_reader:fi_read_stateSBV_0\.Q * /\fi_reader:fi_read_stateSBV_2\.Q * /ao_from_pc_ack \fi_reader:fi_read_stateSBV_0\.C = clk /\fi_reader:fi_read_stateSBV_1\.D = /\fi_reader:fi_read_stateSBV_0\.Q * \fi_reader:fi_read_stateSBV_1\.Q * \fi_reader:timeout_0\.Q * \fi_reader:timeout_1\.Q * \fi_reader:timeout_2\.Q * \fi_reader:timeout_3\.Q + /\fi_reader:fi_read_stateSBV_2\.Q * \fi_reader:timeout_0\.Q * \fi_reader:timeout_1\.Q * \fi_reader:timeout_2\.Q * \fi_reader:timeout_3\.Q + /\fi_reader:fi_read_stateSBV_0\.Q * /\fi_reader:fi_read_stateSBV_1\.Q * /fi_data_12.Q * fi_data_15.Q + /\fi_reader:fi_read_stateSBV_0\.Q * \fi_reader:fi_read_stateSBV_1\.Q * /fi_to_ibus_req.Q + /\fi_reader:fi_read_stateSBV_1\.Q * /\fi_reader:fi_read_stateSBV_2\.Q + \fi_reader:fi_read_stateSBV_0\.Q * /ao_from_pc_ack \fi_reader:fi_read_stateSBV_1\.C = clk \fi_reader:fi_read_stateSBV_2\.T = \fi_reader:fi_read_stateSBV_1\.Q * \fi_reader:fi_read_stateSBV_2\.Q * \fi_reader:timeout_0\.Q * \fi_reader:timeout_1\.Q * \fi_reader:timeout_2\.Q * \fi_reader:timeout_3\.Q * fi_to_ibus_req.Q + \fi_reader:fi_read_stateSBV_1\.Q * \fi_reader:fi_read_stateSBV_2\.Q * \fi_reader:this_is_a_ctrl_transaction\.Q * \fi_reader:timeout_0\.Q * \fi_reader:timeout_1\.Q * \fi_reader:timeout_2\.Q * \fi_reader:timeout_3\.Q + \fi_reader:fi_read_stateSBV_0\.Q * /\fi_reader:fi_read_stateSBV_1\.Q * \fi_reader:fi_read_stateSBV_2\.Q * \fi_reader:timeout_0\.Q * \fi_reader:timeout_1\.Q * \fi_reader:timeout_2\.Q * \fi_reader:timeout_3\.Q + /\fi_reader:fi_read_stateSBV_0\.Q * /\fi_reader:fi_read_stateSBV_1\.Q * \fi_reader:fi_read_stateSBV_2\.Q * /fi_data_12.Q * fi_data_15.Q + \fi_reader:fi_read_stateSBV_1\.Q * \fi_reader:fi_read_stateSBV_2\.Q * \fi_reader:this_is_a_ctrl_transaction\.Q * ao_from_pc_ack * /fi_to_ibus_req.Q + /\fi_reader:fi_read_stateSBV_0\.Q * \fi_reader:fi_read_stateSBV_1\.Q * \fi_reader:fi_read_stateSBV_2\.Q * \fi_reader:this_is_a_ctrl_transaction\.Q * /fi_to_ibus_req.Q + \fi_reader:fi_read_stateSBV_0\.Q * /\fi_reader:fi_read_stateSBV_1\.Q * \fi_reader:fi_read_stateSBV_2\.Q * ao_from_pc_ack + /\fi_reader:fi_read_stateSBV_0\.Q * /\fi_reader:fi_read_stateSBV_1\.Q * /\fi_reader:fi_read_stateSBV_2\.Q * fi_to_ibus_req.Q \fi_reader:fi_read_stateSBV_2\.C = clk \fi_reader:this_is_a_ctrl_transaction\.D = /\fi_reader:fi_read_stateSBV_0\.Q * /\fi_reader:fi_read_stateSBV_1\.Q * \fi_reader:fi_read_stateSBV_2\.Q * /fi_data_10.Q * /fi_data_11.Q * fi_data_12.Q * fi_data_15.Q * /fi_data_8.Q * fi_data_9.Q + \fi_reader:fi_read_stateSBV_1\.Q * \fi_reader:this_is_a_ctrl_transaction\.Q + \fi_reader:fi_read_stateSBV_0\.Q * \fi_reader:this_is_a_ctrl_transaction\.Q + /\fi_reader:fi_read_stateSBV_2\.Q * \fi_reader:this_is_a_ctrl_transaction\.Q + \fi_reader:this_is_a_ctrl_transaction\.Q * /fi_data_15.Q \fi_reader:this_is_a_ctrl_transaction\.AP = GND \fi_reader:this_is_a_ctrl_transaction\.AR = reset \fi_reader:this_is_a_ctrl_transaction\.C = clk \fi_reader:timeout_0\.D = \fi_reader:fi_read_stateSBV_1\.Q * \fi_reader:timeout_0\.Q * \fi_reader:timeout_1\.Q * \fi_reader:timeout_2\.Q * \fi_reader:timeout_3\.Q * fi_to_ibus_req.Q + \fi_reader:fi_read_stateSBV_1\.Q * /\fi_reader:fi_read_stateSBV_2\.Q * \fi_reader:timeout_0\.Q * \fi_reader:timeout_1\.Q * \fi_reader:timeout_2\.Q * \fi_reader:timeout_3\.Q + \fi_reader:fi_read_stateSBV_0\.Q * \fi_reader:timeout_0\.Q * \fi_reader:timeout_1\.Q * \fi_reader:timeout_2\.Q * \fi_reader:timeout_3\.Q * /ao_from_pc_ack + /\fi_reader:fi_read_stateSBV_0\.Q * /\fi_reader:fi_read_stateSBV_1\.Q * \fi_reader:fi_read_stateSBV_2\.Q * \fi_reader:timeout_0\.Q + \fi_reader:fi_read_stateSBV_0\.Q * /\fi_reader:fi_read_stateSBV_1\.Q * /\fi_reader:fi_read_stateSBV_2\.Q * \fi_reader:timeout_0\.Q + \fi_reader:fi_read_stateSBV_0\.Q * \fi_reader:fi_read_stateSBV_1\.Q * /\fi_reader:timeout_0\.Q * ao_from_pc_ack + /\fi_reader:fi_read_stateSBV_0\.Q * \fi_reader:fi_read_stateSBV_1\.Q * /\fi_reader:timeout_0\.Q * fi_to_ibus_req.Q + \fi_reader:fi_read_stateSBV_0\.Q * /\fi_reader:fi_read_stateSBV_2\.Q * \fi_reader:timeout_0\.Q * /ao_from_pc_ack + \fi_reader:fi_read_stateSBV_0\.Q * \fi_reader:fi_read_stateSBV_2\.Q * /\fi_reader:timeout_0\.Q * /ao_from_pc_ack + /\fi_reader:fi_read_stateSBV_0\.Q * \fi_reader:this_is_a_ctrl_transaction\.Q * \fi_reader:timeout_0\.Q * /fi_to_ibus_req.Q + /\fi_reader:fi_read_stateSBV_0\.Q * /\fi_reader:fi_read_stateSBV_2\.Q * \fi_reader:timeout_0\.Q * /fi_to_ibus_req.Q \fi_reader:timeout_0\.C = clk \fi_reader:timeout_1\.T = \fi_reader:fi_read_stateSBV_0\.Q * \fi_reader:fi_read_stateSBV_2\.Q * \fi_reader:timeout_0\.Q * \fi_reader:timeout_1\.Q * ao_from_pc_ack * /fi_to_ibus_req.Q + /\fi_reader:fi_read_stateSBV_0\.Q * \fi_reader:fi_read_stateSBV_1\.Q * \fi_reader:fi_read_stateSBV_2\.Q * /\fi_reader:this_is_a_ctrl_transaction\.Q * \fi_reader:timeout_1\.Q * /fi_to_ibus_req.Q + \fi_reader:fi_read_stateSBV_0\.Q * /\fi_reader:fi_read_stateSBV_1\.Q * \fi_reader:fi_read_stateSBV_2\.Q * \fi_reader:timeout_1\.Q * ao_from_pc_ack + /\fi_reader:fi_read_stateSBV_0\.Q * /\fi_reader:fi_read_stateSBV_1\.Q * /\fi_reader:fi_read_stateSBV_2\.Q * \fi_reader:timeout_1\.Q * fi_to_ibus_req.Q + \fi_reader:fi_read_stateSBV_0\.Q * \fi_reader:fi_read_stateSBV_1\.Q * \fi_reader:timeout_0\.Q * /\fi_reader:timeout_1\.Q * ao_from_pc_ack + /\fi_reader:fi_read_stateSBV_0\.Q * \fi_reader:fi_read_stateSBV_1\.Q * \fi_reader:timeout_0\.Q * /\fi_reader:timeout_1\.Q * fi_to_ibus_req.Q + \fi_reader:fi_read_stateSBV_0\.Q * \fi_reader:fi_read_stateSBV_1\.Q * \fi_reader:timeout_0\.Q * /\fi_reader:timeout_2\.Q * ao_from_pc_ack + /\fi_reader:fi_read_stateSBV_0\.Q * \fi_reader:fi_read_stateSBV_1\.Q * \fi_reader:timeout_0\.Q * /\fi_reader:timeout_2\.Q * fi_to_ibus_req.Q + \fi_reader:fi_read_stateSBV_0\.Q * \fi_reader:fi_read_stateSBV_1\.Q * \fi_reader:timeout_0\.Q * /\fi_reader:timeout_3\.Q * ao_from_pc_ack + /\fi_reader:fi_read_stateSBV_0\.Q * \fi_reader:fi_read_stateSBV_1\.Q * \fi_reader:timeout_0\.Q * /\fi_reader:timeout_3\.Q * fi_to_ibus_req.Q + \fi_reader:fi_read_stateSBV_0\.Q * \fi_reader:fi_read_stateSBV_2\.Q * \fi_reader:timeout_0\.Q * /\fi_reader:timeout_1\.Q * /ao_from_pc_ack + \fi_reader:fi_read_stateSBV_0\.Q * \fi_reader:fi_read_stateSBV_2\.Q * \fi_reader:timeout_0\.Q * /\fi_reader:timeout_2\.Q * /ao_from_pc_ack + \fi_reader:fi_read_stateSBV_0\.Q * \fi_reader:fi_read_stateSBV_2\.Q * \fi_reader:timeout_0\.Q * /\fi_reader:timeout_3\.Q * /ao_from_pc_ack \fi_reader:timeout_1\.C = clk \fi_reader:timeout_2\.T = \fi_reader:fi_read_stateSBV_0\.Q * \fi_reader:fi_read_stateSBV_2\.Q * \fi_reader:timeout_0\.Q * \fi_reader:timeout_1\.Q * \fi_reader:timeout_2\.Q * ao_from_pc_ack * /fi_to_ibus_req.Q + \fi_reader:fi_read_stateSBV_0\.Q * \fi_reader:fi_read_stateSBV_1\.Q * \fi_reader:timeout_0\.Q * \fi_reader:timeout_1\.Q * /\fi_reader:timeout_2\.Q * ao_from_pc_ack + /\fi_reader:fi_read_stateSBV_0\.Q * \fi_reader:fi_read_stateSBV_1\.Q * \fi_reader:timeout_0\.Q * \fi_reader:timeout_1\.Q * /\fi_reader:timeout_2\.Q * fi_to_ibus_req.Q + \fi_reader:fi_read_stateSBV_0\.Q * \fi_reader:fi_read_stateSBV_1\.Q * \fi_reader:timeout_0\.Q * \fi_reader:timeout_1\.Q * /\fi_reader:timeout_3\.Q * ao_from_pc_ack + /\fi_reader:fi_read_stateSBV_0\.Q * \fi_reader:fi_read_stateSBV_1\.Q * \fi_reader:timeout_0\.Q * \fi_reader:timeout_1\.Q * /\fi_reader:timeout_3\.Q * fi_to_ibus_req.Q + \fi_reader:fi_read_stateSBV_0\.Q * \fi_reader:fi_read_stateSBV_2\.Q * \fi_reader:timeout_0\.Q * \fi_reader:timeout_1\.Q * /\fi_reader:timeout_2\.Q * /ao_from_pc_ack + \fi_reader:fi_read_stateSBV_0\.Q * \fi_reader:fi_read_stateSBV_2\.Q * \fi_reader:timeout_0\.Q * \fi_reader:timeout_1\.Q * /\fi_reader:timeout_3\.Q * /ao_from_pc_ack + /\fi_reader:fi_read_stateSBV_0\.Q * \fi_reader:fi_read_stateSBV_1\.Q * \fi_reader:fi_read_stateSBV_2\.Q * /\fi_reader:this_is_a_ctrl_transaction\.Q * \fi_reader:timeout_2\.Q * /fi_to_ibus_req.Q + \fi_reader:fi_read_stateSBV_0\.Q * /\fi_reader:fi_read_stateSBV_1\.Q * \fi_reader:fi_read_stateSBV_2\.Q * \fi_reader:timeout_2\.Q * ao_from_pc_ack + /\fi_reader:fi_read_stateSBV_0\.Q * /\fi_reader:fi_read_stateSBV_1\.Q * /\fi_reader:fi_read_stateSBV_2\.Q * \fi_reader:timeout_2\.Q * fi_to_ibus_req.Q \fi_reader:timeout_2\.C = clk \fi_reader:timeout_3\.D = \fi_reader:fi_read_stateSBV_0\.Q * \fi_reader:fi_read_stateSBV_1\.Q * \fi_reader:timeout_0\.Q * \fi_reader:timeout_1\.Q * \fi_reader:timeout_2\.Q * ao_from_pc_ack + /\fi_reader:fi_read_stateSBV_0\.Q * \fi_reader:fi_read_stateSBV_1\.Q * \fi_reader:timeout_0\.Q * \fi_reader:timeout_1\.Q * \fi_reader:timeout_2\.Q * fi_to_ibus_req.Q + \fi_reader:fi_read_stateSBV_0\.Q * \fi_reader:fi_read_stateSBV_2\.Q * \fi_reader:timeout_0\.Q * \fi_reader:timeout_1\.Q * \fi_reader:timeout_2\.Q * /ao_from_pc_ack + /\fi_reader:fi_read_stateSBV_0\.Q * \fi_reader:fi_read_stateSBV_2\.Q * \fi_reader:timeout_3\.Q * fi_to_ibus_req.Q + /\fi_reader:fi_read_stateSBV_0\.Q * \fi_reader:this_is_a_ctrl_transaction\.Q * \fi_reader:timeout_3\.Q * /fi_to_ibus_req.Q + /\fi_reader:fi_read_stateSBV_0\.Q * /\fi_reader:fi_read_stateSBV_1\.Q * \fi_reader:timeout_3\.Q * /fi_to_ibus_req.Q + \fi_reader:fi_read_stateSBV_1\.Q * /\fi_reader:fi_read_stateSBV_2\.Q * \fi_reader:timeout_3\.Q + \fi_reader:fi_read_stateSBV_0\.Q * /\fi_reader:fi_read_stateSBV_2\.Q * \fi_reader:timeout_3\.Q + \fi_reader:fi_read_stateSBV_0\.Q * \fi_reader:timeout_3\.Q * /ao_from_pc_ack \fi_reader:timeout_3\.C = clk \fr_imp:fr_stateSBV_0\.D = /\fr_imp:fr_stateSBV_0\.Q * /fr_rdy_l * fr_status * /reset_fifo.Q \fr_imp:fr_stateSBV_0\.C = clk /\ibus_fi:read_stateSBV_0\.D = /\ibus_fi:read_stateSBV_1\.Q * \ibus_fi:timeout_0\.Q * \ibus_fi:timeout_1\.Q * \ibus_fi:timeout_2\.Q * \ibus_fi:timeout_3\.Q + /\ibus_fi:read_stateSBV_0\.Q * /\ibus_fi:read_stateSBV_1\.Q + /fi_to_ibus_ack.Q \ibus_fi:read_stateSBV_0\.C = clk \ibus_fi:read_stateSBV_1\.T = \ibus_fi:read_stateSBV_1\.Q * \ibus_fi:timeout_0\.Q * \ibus_fi:timeout_1\.Q * \ibus_fi:timeout_2\.Q * \ibus_fi:timeout_3\.Q + /\ibus_fi:read_stateSBV_0\.Q * /\ibus_fi:read_stateSBV_1\.Q * data_pump_word_ready.Q * /fi_to_ibus_ack.Q + \ibus_fi:read_stateSBV_1\.Q * fi_to_ibus_ack.Q \ibus_fi:read_stateSBV_1\.C = clk \ibus_fi:timeout_0\.D = \ibus_fi:read_stateSBV_0\.Q * \ibus_fi:timeout_1\.Q * \ibus_fi:timeout_2\.Q * \ibus_fi:timeout_3\.Q * fi_to_ibus_ack.Q + \ibus_fi:read_stateSBV_1\.Q * \ibus_fi:timeout_1\.Q * \ibus_fi:timeout_2\.Q * \ibus_fi:timeout_3\.Q * /fi_to_ibus_ack.Q + \ibus_fi:read_stateSBV_1\.Q * \ibus_fi:timeout_0\.Q * fi_to_ibus_ack.Q + \ibus_fi:read_stateSBV_0\.Q * /\ibus_fi:timeout_0\.Q * fi_to_ibus_ack.Q + \ibus_fi:read_stateSBV_0\.Q * \ibus_fi:timeout_0\.Q * /fi_to_ibus_ack.Q + \ibus_fi:read_stateSBV_1\.Q * /\ibus_fi:timeout_0\.Q * /fi_to_ibus_ack.Q \ibus_fi:timeout_0\.C = clk \ibus_fi:timeout_1\.T = /\ibus_fi:read_stateSBV_1\.Q * \ibus_fi:timeout_0\.Q * \ibus_fi:timeout_1\.Q * /\ibus_fi:timeout_2\.Q * fi_to_ibus_ack.Q + /\ibus_fi:read_stateSBV_1\.Q * \ibus_fi:timeout_0\.Q * \ibus_fi:timeout_1\.Q * /\ibus_fi:timeout_3\.Q * fi_to_ibus_ack.Q + /\ibus_fi:read_stateSBV_0\.Q * \ibus_fi:timeout_0\.Q * \ibus_fi:timeout_1\.Q * /\ibus_fi:timeout_2\.Q * /fi_to_ibus_ack.Q + /\ibus_fi:read_stateSBV_0\.Q * \ibus_fi:timeout_0\.Q * \ibus_fi:timeout_1\.Q * /\ibus_fi:timeout_3\.Q * /fi_to_ibus_ack.Q + \ibus_fi:read_stateSBV_0\.Q * \ibus_fi:timeout_0\.Q * /\ibus_fi:timeout_1\.Q * fi_to_ibus_ack.Q + \ibus_fi:read_stateSBV_1\.Q * \ibus_fi:timeout_0\.Q * /\ibus_fi:timeout_1\.Q * /fi_to_ibus_ack.Q + /\ibus_fi:read_stateSBV_0\.Q * /\ibus_fi:read_stateSBV_1\.Q * \ibus_fi:timeout_1\.Q \ibus_fi:timeout_1\.C = clk \ibus_fi:timeout_2\.T = /\ibus_fi:read_stateSBV_1\.Q * \ibus_fi:timeout_0\.Q * \ibus_fi:timeout_1\.Q * \ibus_fi:timeout_2\.Q * /\ibus_fi:timeout_3\.Q * fi_to_ibus_ack.Q + /\ibus_fi:read_stateSBV_0\.Q * \ibus_fi:timeout_0\.Q * \ibus_fi:timeout_1\.Q * \ibus_fi:timeout_2\.Q * /\ibus_fi:timeout_3\.Q * /fi_to_ibus_ack.Q + \ibus_fi:read_stateSBV_0\.Q * \ibus_fi:timeout_0\.Q * \ibus_fi:timeout_1\.Q * /\ibus_fi:timeout_2\.Q * fi_to_ibus_ack.Q + \ibus_fi:read_stateSBV_1\.Q * \ibus_fi:timeout_0\.Q * \ibus_fi:timeout_1\.Q * /\ibus_fi:timeout_2\.Q * /fi_to_ibus_ack.Q + /\ibus_fi:read_stateSBV_0\.Q * /\ibus_fi:read_stateSBV_1\.Q * \ibus_fi:timeout_2\.Q \ibus_fi:timeout_2\.C = clk \ibus_fi:timeout_3\.T = \ibus_fi:read_stateSBV_0\.Q * \ibus_fi:timeout_0\.Q * \ibus_fi:timeout_1\.Q * \ibus_fi:timeout_2\.Q * /\ibus_fi:timeout_3\.Q * fi_to_ibus_ack.Q + \ibus_fi:read_stateSBV_1\.Q * \ibus_fi:timeout_0\.Q * \ibus_fi:timeout_1\.Q * \ibus_fi:timeout_2\.Q * /\ibus_fi:timeout_3\.Q * /fi_to_ibus_ack.Q + /\ibus_fi:read_stateSBV_0\.Q * /\ibus_fi:read_stateSBV_1\.Q * \ibus_fi:timeout_3\.Q \ibus_fi:timeout_3\.C = clk \ibus_fo:stateSBV_0\.D = \ibus_fo:stateSBV_1\.Q * \ibus_fo:stateSBV_2\.Q \ibus_fo:stateSBV_0\.C = clk \ibus_fo:stateSBV_1\.D = /\ibus_fo:stateSBV_1\.Q * \ibus_fo:stateSBV_2\.Q * fr_ref_clk.CMB + \ibus_fo:stateSBV_1\.Q * /\ibus_fo:stateSBV_2\.Q \ibus_fo:stateSBV_1\.C = clk \ibus_fo:stateSBV_2\.D = /\ibus_fo:stateSBV_0\.Q * /\ibus_fo:stateSBV_2\.Q * write_to_fo_req.Q + /\ibus_fo:stateSBV_1\.Q * \ibus_fo:stateSBV_2\.Q * /fr_ref_clk.CMB + \ibus_fo:stateSBV_1\.Q * /\ibus_fo:stateSBV_2\.Q \ibus_fo:stateSBV_2\.C = clk \ibus_reader:iu_readSBV_0\.T = /\ibus_reader:iu_readSBV_0\.Q * \ibus_reader:iu_readSBV_1\.Q * \ibus_reader:timeout_0\.Q * \ibus_reader:timeout_1\.Q * \ibus_reader:timeout_2\.Q * \ibus_reader:timeout_3\.Q + \ibus_reader:iu_readSBV_0\.Q * \ibus_reader:timeout_0\.Q * \ibus_reader:timeout_1\.Q * \ibus_reader:timeout_2\.Q * \ibus_reader:timeout_3\.Q * /write_to_fo_ack.Q + /\ibus_reader:iu_readSBV_0\.Q * \ibus_reader:iu_readSBV_1\.Q * /ao_to_pc_strobe + \ibus_reader:iu_readSBV_0\.Q * \ibus_reader:iu_readSBV_1\.Q * /write_to_fo_ack.Q \ibus_reader:iu_readSBV_0\.C = clk /\ibus_reader:iu_readSBV_1\.D = /\ibus_reader:iu_readSBV_0\.Q * \ibus_reader:iu_readSBV_1\.Q * \ibus_reader:timeout_0\.Q * \ibus_reader:timeout_1\.Q * \ibus_reader:timeout_2\.Q * \ibus_reader:timeout_3\.Q + /\ibus_reader:iu_readSBV_0\.Q * /ao_to_pc_strobe + \ibus_reader:iu_readSBV_0\.Q * /write_to_fo_ack.Q \ibus_reader:iu_readSBV_1\.C = clk \ibus_reader:timeout_0\.D = \ibus_reader:iu_readSBV_0\.Q * \ibus_reader:timeout_0\.Q * \ibus_reader:timeout_1\.Q * \ibus_reader:timeout_2\.Q * \ibus_reader:timeout_3\.Q + /\ibus_reader:iu_readSBV_0\.Q * \ibus_reader:iu_readSBV_1\.Q * /\ibus_reader:timeout_0\.Q * ao_to_pc_strobe + /\ibus_reader:iu_readSBV_0\.Q * /\ibus_reader:iu_readSBV_1\.Q * \ibus_reader:timeout_0\.Q * /ao_to_pc_strobe + \ibus_reader:iu_readSBV_0\.Q * /\ibus_reader:iu_readSBV_1\.Q * /\ibus_reader:timeout_0\.Q * /write_to_fo_ack.Q + \ibus_reader:iu_readSBV_0\.Q * \ibus_reader:timeout_0\.Q * write_to_fo_ack.Q + \ibus_reader:iu_readSBV_0\.Q * \ibus_reader:iu_readSBV_1\.Q * \ibus_reader:timeout_0\.Q \ibus_reader:timeout_0\.C = clk \ibus_reader:timeout_1\.T = \ibus_reader:iu_readSBV_0\.Q * /\ibus_reader:iu_readSBV_1\.Q * \ibus_reader:timeout_0\.Q * /\ibus_reader:timeout_1\.Q * /write_to_fo_ack.Q + \ibus_reader:iu_readSBV_0\.Q * /\ibus_reader:iu_readSBV_1\.Q * \ibus_reader:timeout_0\.Q * /\ibus_reader:timeout_2\.Q * /write_to_fo_ack.Q + \ibus_reader:iu_readSBV_0\.Q * /\ibus_reader:iu_readSBV_1\.Q * \ibus_reader:timeout_0\.Q * /\ibus_reader:timeout_3\.Q * /write_to_fo_ack.Q + /\ibus_reader:iu_readSBV_0\.Q * \ibus_reader:iu_readSBV_1\.Q * \ibus_reader:timeout_0\.Q * ao_to_pc_strobe + /\ibus_reader:iu_readSBV_0\.Q * /\ibus_reader:iu_readSBV_1\.Q * \ibus_reader:timeout_1\.Q * ao_to_pc_strobe + /\ibus_reader:iu_readSBV_0\.Q * \ibus_reader:iu_readSBV_1\.Q * \ibus_reader:timeout_1\.Q * /ao_to_pc_strobe \ibus_reader:timeout_1\.C = clk \ibus_reader:timeout_2\.T = \ibus_reader:iu_readSBV_0\.Q * /\ibus_reader:iu_readSBV_1\.Q * \ibus_reader:timeout_0\.Q * \ibus_reader:timeout_1\.Q * /\ibus_reader:timeout_2\.Q * /write_to_fo_ack.Q + \ibus_reader:iu_readSBV_0\.Q * /\ibus_reader:iu_readSBV_1\.Q * \ibus_reader:timeout_0\.Q * \ibus_reader:timeout_1\.Q * /\ibus_reader:timeout_3\.Q * /write_to_fo_ack.Q + /\ibus_reader:iu_readSBV_0\.Q * \ibus_reader:iu_readSBV_1\.Q * \ibus_reader:timeout_0\.Q * \ibus_reader:timeout_1\.Q * ao_to_pc_strobe + /\ibus_reader:iu_readSBV_0\.Q * /\ibus_reader:iu_readSBV_1\.Q * \ibus_reader:timeout_2\.Q * ao_to_pc_strobe + /\ibus_reader:iu_readSBV_0\.Q * \ibus_reader:iu_readSBV_1\.Q * \ibus_reader:timeout_2\.Q * /ao_to_pc_strobe \ibus_reader:timeout_2\.C = clk \ibus_reader:timeout_3\.T = \ibus_reader:iu_readSBV_0\.Q * /\ibus_reader:iu_readSBV_1\.Q * \ibus_reader:timeout_0\.Q * \ibus_reader:timeout_1\.Q * \ibus_reader:timeout_2\.Q * /\ibus_reader:timeout_3\.Q * /write_to_fo_ack.Q + /\ibus_reader:iu_readSBV_0\.Q * \ibus_reader:iu_readSBV_1\.Q * \ibus_reader:timeout_0\.Q * \ibus_reader:timeout_1\.Q * \ibus_reader:timeout_2\.Q * ao_to_pc_strobe + /\ibus_reader:iu_readSBV_0\.Q * /\ibus_reader:iu_readSBV_1\.Q * \ibus_reader:timeout_3\.Q * ao_to_pc_strobe + /\ibus_reader:iu_readSBV_0\.Q * \ibus_reader:iu_readSBV_1\.Q * \ibus_reader:timeout_3\.Q * /ao_to_pc_strobe \ibus_reader:timeout_3\.C = clk \pump:count_0\.D = /\pump:count_0\.Q * \pump:pump_stateSBV_0\.Q * /\pump:pump_stateSBV_1\.Q * /fifo_out(8) + /\pump:count_1\.Q * \pump:pump_stateSBV_0\.Q * /\pump:pump_stateSBV_1\.Q * /fifo_out(8) + \pump:count_0\.Q * \pump:pump_stateSBV_1\.Q \pump:count_0\.C = clk \pump:count_1\.D = /\pump:count_0\.Q * \pump:count_1\.Q * \pump:pump_stateSBV_0\.Q * /fifo_out(8) + \pump:count_1\.Q * \pump:pump_stateSBV_1\.Q \pump:count_1\.C = clk /\pump:pump_stateSBV_0\.D = \pump:count_0\.Q * /\pump:count_1\.Q * \pump:pump_stateSBV_0\.Q * /\pump:pump_stateSBV_1\.Q + /\pump:pump_stateSBV_0\.Q * /\pump:pump_stateSBV_1\.Q * /fifo_reset_l.Q * /refill_ibus_output_buf.Q + \pump:pump_stateSBV_0\.Q * /\pump:pump_stateSBV_1\.Q * fifo_out(8) + \pump:pump_stateSBV_0\.Q * fifo_empty_l + /\pump:pump_stateSBV_1\.Q * fifo_empty_l \pump:pump_stateSBV_0\.C = clk /\pump:pump_stateSBV_1\.D = \pump:count_0\.Q * /\pump:count_1\.Q * \pump:pump_stateSBV_0\.Q * /\pump:pump_stateSBV_1\.Q * /fifo_out(8) + /\pump:pump_stateSBV_0\.Q * /fifo_reset_l.Q * /refill_ibus_output_buf.Q + /\pump:pump_stateSBV_0\.Q * \pump:pump_stateSBV_1\.Q \pump:pump_stateSBV_1\.C = clk ao_from_pc_strobe.D = \fi_reader:fi_read_stateSBV_1\.Q * \fi_reader:fi_read_stateSBV_2\.Q * /\fi_reader:this_is_a_ctrl_transaction\.Q + \fi_reader:fi_read_stateSBV_0\.Q * \fi_reader:fi_read_stateSBV_2\.Q * /ao_from_pc_ack ao_from_pc_strobe.C = clk ao_to_pc_ack.D = /\ibus_reader:iu_readSBV_0\.Q * ao_to_pc_strobe + /\ibus_reader:iu_readSBV_0\.Q * \ibus_reader:iu_readSBV_1\.Q ao_to_pc_ack.C = clk data_pump_word_ready.D = \pump:count_0\.Q * /\pump:count_1\.Q * \pump:pump_stateSBV_0\.Q * /\pump:pump_stateSBV_1\.Q * /fifo_out(8) data_pump_word_ready.C = clk data_to_fo_0.T = /\ibus_reader:iu_readSBV_0\.Q * /\ibus_reader:iu_readSBV_1\.Q * ao_to_pc_strobe * /data_to_fo_0.Q * id(16) + /\ibus_reader:iu_readSBV_0\.Q * /\ibus_reader:iu_readSBV_1\.Q * ao_to_pc_strobe * data_to_fo_0.Q * /id(16) data_to_fo_0.C = clk data_to_fo_1.T = /\ibus_reader:iu_readSBV_0\.Q * /\ibus_reader:iu_readSBV_1\.Q * ao_to_pc_strobe * /data_to_fo_1.Q * id(17) + /\ibus_reader:iu_readSBV_0\.Q * /\ibus_reader:iu_readSBV_1\.Q * ao_to_pc_strobe * data_to_fo_1.Q * /id(17) data_to_fo_1.C = clk data_to_fo_10.T = /\ibus_reader:iu_readSBV_0\.Q * /\ibus_reader:iu_readSBV_1\.Q * ao_to_pc_strobe * /data_to_fo_10.Q * id(26) + /\ibus_reader:iu_readSBV_0\.Q * /\ibus_reader:iu_readSBV_1\.Q * ao_to_pc_strobe * data_to_fo_10.Q * /id(26) data_to_fo_10.C = clk data_to_fo_11.T = /\ibus_reader:iu_readSBV_0\.Q * /\ibus_reader:iu_readSBV_1\.Q * ao_to_pc_strobe * /data_to_fo_11.Q * id(27) + /\ibus_reader:iu_readSBV_0\.Q * /\ibus_reader:iu_readSBV_1\.Q * ao_to_pc_strobe * data_to_fo_11.Q * /id(27) data_to_fo_11.C = clk data_to_fo_12.T = /\ibus_reader:iu_readSBV_0\.Q * /\ibus_reader:iu_readSBV_1\.Q * ao_to_pc_strobe * /data_to_fo_12.Q * id(28) + /\ibus_reader:iu_readSBV_0\.Q * /\ibus_reader:iu_readSBV_1\.Q * ao_to_pc_strobe * data_to_fo_12.Q * /id(28) data_to_fo_12.C = clk data_to_fo_13.T = /\ibus_reader:iu_readSBV_0\.Q * /\ibus_reader:iu_readSBV_1\.Q * ao_to_pc_strobe * /data_to_fo_13.Q * id(29) + /\ibus_reader:iu_readSBV_0\.Q * /\ibus_reader:iu_readSBV_1\.Q * ao_to_pc_strobe * data_to_fo_13.Q * /id(29) data_to_fo_13.C = clk data_to_fo_14.T = /\ibus_reader:iu_readSBV_0\.Q * /\ibus_reader:iu_readSBV_1\.Q * ao_to_pc_strobe * /data_to_fo_14.Q * id(30) + /\ibus_reader:iu_readSBV_0\.Q * /\ibus_reader:iu_readSBV_1\.Q * ao_to_pc_strobe * data_to_fo_14.Q * /id(30) data_to_fo_14.C = clk data_to_fo_15.T = /\ibus_reader:iu_readSBV_0\.Q * /\ibus_reader:iu_readSBV_1\.Q * ao_to_pc_strobe * /data_to_fo_15.Q * id(31) + /\ibus_reader:iu_readSBV_0\.Q * /\ibus_reader:iu_readSBV_1\.Q * ao_to_pc_strobe * data_to_fo_15.Q * /id(31) data_to_fo_15.C = clk data_to_fo_2.T = /\ibus_reader:iu_readSBV_0\.Q * /\ibus_reader:iu_readSBV_1\.Q * ao_to_pc_strobe * /data_to_fo_2.Q * id(18) + /\ibus_reader:iu_readSBV_0\.Q * /\ibus_reader:iu_readSBV_1\.Q * ao_to_pc_strobe * data_to_fo_2.Q * /id(18) data_to_fo_2.C = clk data_to_fo_3.T = /\ibus_reader:iu_readSBV_0\.Q * /\ibus_reader:iu_readSBV_1\.Q * ao_to_pc_strobe * /data_to_fo_3.Q * id(19) + /\ibus_reader:iu_readSBV_0\.Q * /\ibus_reader:iu_readSBV_1\.Q * ao_to_pc_strobe * data_to_fo_3.Q * /id(19) data_to_fo_3.C = clk data_to_fo_4.T = /\ibus_reader:iu_readSBV_0\.Q * /\ibus_reader:iu_readSBV_1\.Q * ao_to_pc_strobe * /data_to_fo_4.Q * id(20) + /\ibus_reader:iu_readSBV_0\.Q * /\ibus_reader:iu_readSBV_1\.Q * ao_to_pc_strobe * data_to_fo_4.Q * /id(20) data_to_fo_4.C = clk data_to_fo_5.T = /\ibus_reader:iu_readSBV_0\.Q * /\ibus_reader:iu_readSBV_1\.Q * ao_to_pc_strobe * /data_to_fo_5.Q * id(21) + /\ibus_reader:iu_readSBV_0\.Q * /\ibus_reader:iu_readSBV_1\.Q * ao_to_pc_strobe * data_to_fo_5.Q * /id(21) data_to_fo_5.C = clk data_to_fo_6.T = /\ibus_reader:iu_readSBV_0\.Q * /\ibus_reader:iu_readSBV_1\.Q * ao_to_pc_strobe * /data_to_fo_6.Q * id(22) + /\ibus_reader:iu_readSBV_0\.Q * /\ibus_reader:iu_readSBV_1\.Q * ao_to_pc_strobe * data_to_fo_6.Q * /id(22) data_to_fo_6.C = clk data_to_fo_7.T = /\ibus_reader:iu_readSBV_0\.Q * /\ibus_reader:iu_readSBV_1\.Q * ao_to_pc_strobe * /data_to_fo_7.Q * id(23) + /\ibus_reader:iu_readSBV_0\.Q * /\ibus_reader:iu_readSBV_1\.Q * ao_to_pc_strobe * data_to_fo_7.Q * /id(23) data_to_fo_7.C = clk data_to_fo_8.T = /\ibus_reader:iu_readSBV_0\.Q * /\ibus_reader:iu_readSBV_1\.Q * ao_to_pc_strobe * /data_to_fo_8.Q * id(24) + /\ibus_reader:iu_readSBV_0\.Q * /\ibus_reader:iu_readSBV_1\.Q * ao_to_pc_strobe * data_to_fo_8.Q * /id(24) data_to_fo_8.C = clk data_to_fo_9.T = /\ibus_reader:iu_readSBV_0\.Q * /\ibus_reader:iu_readSBV_1\.Q * ao_to_pc_strobe * /data_to_fo_9.Q * id(25) + /\ibus_reader:iu_readSBV_0\.Q * /\ibus_reader:iu_readSBV_1\.Q * ao_to_pc_strobe * data_to_fo_9.Q * /id(25) data_to_fo_9.C = clk debug = ao_from_pc_strobe.Q fi_data_0.T = /\ibus_fi:read_stateSBV_0\.Q * /\ibus_fi:read_stateSBV_1\.Q * data_pump_word_ready.Q * /fi_data_0.Q * /fi_to_ibus_ack.Q * fiber_to_ibus_buf_0.Q + /\ibus_fi:read_stateSBV_0\.Q * /\ibus_fi:read_stateSBV_1\.Q * data_pump_word_ready.Q * fi_data_0.Q * /fi_to_ibus_ack.Q * /fiber_to_ibus_buf_0.Q fi_data_0.C = clk fi_data_1.T = /\ibus_fi:read_stateSBV_0\.Q * /\ibus_fi:read_stateSBV_1\.Q * data_pump_word_ready.Q * /fi_data_1.Q * /fi_to_ibus_ack.Q * fiber_to_ibus_buf_1.Q + /\ibus_fi:read_stateSBV_0\.Q * /\ibus_fi:read_stateSBV_1\.Q * data_pump_word_ready.Q * fi_data_1.Q * /fi_to_ibus_ack.Q * /fiber_to_ibus_buf_1.Q fi_data_1.C = clk fi_data_10.T = /\ibus_fi:read_stateSBV_0\.Q * /\ibus_fi:read_stateSBV_1\.Q * data_pump_word_ready.Q * /fi_data_10.Q * /fi_to_ibus_ack.Q * fiber_to_ibus_buf_10.Q + /\ibus_fi:read_stateSBV_0\.Q * /\ibus_fi:read_stateSBV_1\.Q * data_pump_word_ready.Q * fi_data_10.Q * /fi_to_ibus_ack.Q * /fiber_to_ibus_buf_10.Q fi_data_10.C = clk fi_data_11.T = /\ibus_fi:read_stateSBV_0\.Q * /\ibus_fi:read_stateSBV_1\.Q * data_pump_word_ready.Q * /fi_data_11.Q * /fi_to_ibus_ack.Q * fiber_to_ibus_buf_11.Q + /\ibus_fi:read_stateSBV_0\.Q * /\ibus_fi:read_stateSBV_1\.Q * data_pump_word_ready.Q * fi_data_11.Q * /fi_to_ibus_ack.Q * /fiber_to_ibus_buf_11.Q fi_data_11.C = clk fi_data_12.T = /\ibus_fi:read_stateSBV_0\.Q * /\ibus_fi:read_stateSBV_1\.Q * data_pump_word_ready.Q * /fi_data_12.Q * /fi_to_ibus_ack.Q * fiber_to_ibus_buf_12.Q + /\ibus_fi:read_stateSBV_0\.Q * /\ibus_fi:read_stateSBV_1\.Q * data_pump_word_ready.Q * fi_data_12.Q * /fi_to_ibus_ack.Q * /fiber_to_ibus_buf_12.Q fi_data_12.C = clk fi_data_13.T = /\ibus_fi:read_stateSBV_0\.Q * /\ibus_fi:read_stateSBV_1\.Q * data_pump_word_ready.Q * /fi_data_13.Q * /fi_to_ibus_ack.Q * fiber_to_ibus_buf_13.Q + /\ibus_fi:read_stateSBV_0\.Q * /\ibus_fi:read_stateSBV_1\.Q * data_pump_word_ready.Q * fi_data_13.Q * /fi_to_ibus_ack.Q * /fiber_to_ibus_buf_13.Q fi_data_13.C = clk fi_data_14.T = /\ibus_fi:read_stateSBV_0\.Q * /\ibus_fi:read_stateSBV_1\.Q * data_pump_word_ready.Q * /fi_data_14.Q * /fi_to_ibus_ack.Q * fiber_to_ibus_buf_14.Q + /\ibus_fi:read_stateSBV_0\.Q * /\ibus_fi:read_stateSBV_1\.Q * data_pump_word_ready.Q * fi_data_14.Q * /fi_to_ibus_ack.Q * /fiber_to_ibus_buf_14.Q fi_data_14.C = clk fi_data_15.T = /\ibus_fi:read_stateSBV_0\.Q * /\ibus_fi:read_stateSBV_1\.Q * data_pump_word_ready.Q * /fi_data_15.Q * /fi_to_ibus_ack.Q * fiber_to_ibus_buf_15.Q + /\ibus_fi:read_stateSBV_0\.Q * /\ibus_fi:read_stateSBV_1\.Q * data_pump_word_ready.Q * fi_data_15.Q * /fi_to_ibus_ack.Q * /fiber_to_ibus_buf_15.Q fi_data_15.C = clk fi_data_2.T = /\ibus_fi:read_stateSBV_0\.Q * /\ibus_fi:read_stateSBV_1\.Q * data_pump_word_ready.Q * /fi_data_2.Q * /fi_to_ibus_ack.Q * fiber_to_ibus_buf_2.Q + /\ibus_fi:read_stateSBV_0\.Q * /\ibus_fi:read_stateSBV_1\.Q * data_pump_word_ready.Q * fi_data_2.Q * /fi_to_ibus_ack.Q * /fiber_to_ibus_buf_2.Q fi_data_2.C = clk fi_data_3.T = /\ibus_fi:read_stateSBV_0\.Q * /\ibus_fi:read_stateSBV_1\.Q * data_pump_word_ready.Q * /fi_data_3.Q * /fi_to_ibus_ack.Q * fiber_to_ibus_buf_3.Q + /\ibus_fi:read_stateSBV_0\.Q * /\ibus_fi:read_stateSBV_1\.Q * data_pump_word_ready.Q * fi_data_3.Q * /fi_to_ibus_ack.Q * /fiber_to_ibus_buf_3.Q fi_data_3.C = clk fi_data_4.T = /\ibus_fi:read_stateSBV_0\.Q * /\ibus_fi:read_stateSBV_1\.Q * data_pump_word_ready.Q * /fi_data_4.Q * /fi_to_ibus_ack.Q * fiber_to_ibus_buf_4.Q + /\ibus_fi:read_stateSBV_0\.Q * /\ibus_fi:read_stateSBV_1\.Q * data_pump_word_ready.Q * fi_data_4.Q * /fi_to_ibus_ack.Q * /fiber_to_ibus_buf_4.Q fi_data_4.C = clk fi_data_5.T = /\ibus_fi:read_stateSBV_0\.Q * /\ibus_fi:read_stateSBV_1\.Q * data_pump_word_ready.Q * /fi_data_5.Q * /fi_to_ibus_ack.Q * fiber_to_ibus_buf_5.Q + /\ibus_fi:read_stateSBV_0\.Q * /\ibus_fi:read_stateSBV_1\.Q * data_pump_word_ready.Q * fi_data_5.Q * /fi_to_ibus_ack.Q * /fiber_to_ibus_buf_5.Q fi_data_5.C = clk fi_data_6.T = /\ibus_fi:read_stateSBV_0\.Q * /\ibus_fi:read_stateSBV_1\.Q * data_pump_word_ready.Q * /fi_data_6.Q * /fi_to_ibus_ack.Q * fiber_to_ibus_buf_6.Q + /\ibus_fi:read_stateSBV_0\.Q * /\ibus_fi:read_stateSBV_1\.Q * data_pump_word_ready.Q * fi_data_6.Q * /fi_to_ibus_ack.Q * /fiber_to_ibus_buf_6.Q fi_data_6.C = clk fi_data_7.T = /\ibus_fi:read_stateSBV_0\.Q * /\ibus_fi:read_stateSBV_1\.Q * data_pump_word_ready.Q * /fi_data_7.Q * /fi_to_ibus_ack.Q * fiber_to_ibus_buf_7.Q + /\ibus_fi:read_stateSBV_0\.Q * /\ibus_fi:read_stateSBV_1\.Q * data_pump_word_ready.Q * fi_data_7.Q * /fi_to_ibus_ack.Q * /fiber_to_ibus_buf_7.Q fi_data_7.C = clk fi_data_8.T = /\ibus_fi:read_stateSBV_0\.Q * /\ibus_fi:read_stateSBV_1\.Q * data_pump_word_ready.Q * /fi_data_8.Q * /fi_to_ibus_ack.Q * fiber_to_ibus_buf_8.Q + /\ibus_fi:read_stateSBV_0\.Q * /\ibus_fi:read_stateSBV_1\.Q * data_pump_word_ready.Q * fi_data_8.Q * /fi_to_ibus_ack.Q * /fiber_to_ibus_buf_8.Q fi_data_8.C = clk fi_data_9.T = /\ibus_fi:read_stateSBV_0\.Q * /\ibus_fi:read_stateSBV_1\.Q * data_pump_word_ready.Q * /fi_data_9.Q * /fi_to_ibus_ack.Q * fiber_to_ibus_buf_9.Q + /\ibus_fi:read_stateSBV_0\.Q * /\ibus_fi:read_stateSBV_1\.Q * data_pump_word_ready.Q * fi_data_9.Q * /fi_to_ibus_ack.Q * /fiber_to_ibus_buf_9.Q fi_data_9.C = clk fi_to_ibus_ack.D = /\fi_reader:fi_read_stateSBV_0\.Q * \fi_reader:fi_read_stateSBV_1\.Q fi_to_ibus_ack.C = clk fi_to_ibus_req.D = /\ibus_fi:read_stateSBV_0\.Q * /\ibus_fi:read_stateSBV_1\.Q * data_pump_word_ready.Q * /fi_to_ibus_ack.Q fi_to_ibus_req.C = clk fiber_to_ibus_buf_0.T = \pump:pump_stateSBV_0\.Q * /\pump:pump_stateSBV_1\.Q * /fiber_to_ibus_buf_0.Q * fiber_to_ibus_buf_8.Q * /fifo_out(8) + \pump:pump_stateSBV_0\.Q * /\pump:pump_stateSBV_1\.Q * fiber_to_ibus_buf_0.Q * /fiber_to_ibus_buf_8.Q * /fifo_out(8) fiber_to_ibus_buf_0.C = clk fiber_to_ibus_buf_1.T = \pump:pump_stateSBV_0\.Q * /\pump:pump_stateSBV_1\.Q * /fiber_to_ibus_buf_1.Q * fiber_to_ibus_buf_9.Q * /fifo_out(8) + \pump:pump_stateSBV_0\.Q * /\pump:pump_stateSBV_1\.Q * fiber_to_ibus_buf_1.Q * /fiber_to_ibus_buf_9.Q * /fifo_out(8) fiber_to_ibus_buf_1.C = clk fiber_to_ibus_buf_10.T = \pump:pump_stateSBV_0\.Q * /\pump:pump_stateSBV_1\.Q * /fiber_to_ibus_buf_10.Q * fifo_out(2) * /fifo_out(8) + \pump:pump_stateSBV_0\.Q * /\pump:pump_stateSBV_1\.Q * fiber_to_ibus_buf_10.Q * /fifo_out(2) * /fifo_out(8) fiber_to_ibus_buf_10.C = clk fiber_to_ibus_buf_11.T = \pump:pump_stateSBV_0\.Q * /\pump:pump_stateSBV_1\.Q * /fiber_to_ibus_buf_11.Q * fifo_out(3) * /fifo_out(8) + \pump:pump_stateSBV_0\.Q * /\pump:pump_stateSBV_1\.Q * fiber_to_ibus_buf_11.Q * /fifo_out(3) * /fifo_out(8) fiber_to_ibus_buf_11.C = clk fiber_to_ibus_buf_12.T = \pump:pump_stateSBV_0\.Q * /\pump:pump_stateSBV_1\.Q * /fiber_to_ibus_buf_12.Q * fifo_out(4) * /fifo_out(8) + \pump:pump_stateSBV_0\.Q * /\pump:pump_stateSBV_1\.Q * fiber_to_ibus_buf_12.Q * /fifo_out(4) * /fifo_out(8) fiber_to_ibus_buf_12.C = clk fiber_to_ibus_buf_13.T = \pump:pump_stateSBV_0\.Q * /\pump:pump_stateSBV_1\.Q * /fiber_to_ibus_buf_13.Q * fifo_out(5) * /fifo_out(8) + \pump:pump_stateSBV_0\.Q * /\pump:pump_stateSBV_1\.Q * fiber_to_ibus_buf_13.Q * /fifo_out(5) * /fifo_out(8) fiber_to_ibus_buf_13.C = clk fiber_to_ibus_buf_14.T = \pump:pump_stateSBV_0\.Q * /\pump:pump_stateSBV_1\.Q * /fiber_to_ibus_buf_14.Q * fifo_out(6) * /fifo_out(8) + \pump:pump_stateSBV_0\.Q * /\pump:pump_stateSBV_1\.Q * fiber_to_ibus_buf_14.Q * /fifo_out(6) * /fifo_out(8) fiber_to_ibus_buf_14.C = clk fiber_to_ibus_buf_15.T = \pump:pump_stateSBV_0\.Q * /\pump:pump_stateSBV_1\.Q * /fiber_to_ibus_buf_15.Q * fifo_out(7) * /fifo_out(8) + \pump:pump_stateSBV_0\.Q * /\pump:pump_stateSBV_1\.Q * fiber_to_ibus_buf_15.Q * /fifo_out(7) * /fifo_out(8) fiber_to_ibus_buf_15.C = clk fiber_to_ibus_buf_2.T = \pump:pump_stateSBV_0\.Q * /\pump:pump_stateSBV_1\.Q * /fiber_to_ibus_buf_10.Q * fiber_to_ibus_buf_2.Q * /fifo_out(8) + \pump:pump_stateSBV_0\.Q * /\pump:pump_stateSBV_1\.Q * fiber_to_ibus_buf_10.Q * /fiber_to_ibus_buf_2.Q * /fifo_out(8) fiber_to_ibus_buf_2.C = clk fiber_to_ibus_buf_3.T = \pump:pump_stateSBV_0\.Q * /\pump:pump_stateSBV_1\.Q * /fiber_to_ibus_buf_11.Q * fiber_to_ibus_buf_3.Q * /fifo_out(8) + \pump:pump_stateSBV_0\.Q * /\pump:pump_stateSBV_1\.Q * fiber_to_ibus_buf_11.Q * /fiber_to_ibus_buf_3.Q * /fifo_out(8) fiber_to_ibus_buf_3.C = clk fiber_to_ibus_buf_4.T = \pump:pump_stateSBV_0\.Q * /\pump:pump_stateSBV_1\.Q * /fiber_to_ibus_buf_12.Q * fiber_to_ibus_buf_4.Q * /fifo_out(8) + \pump:pump_stateSBV_0\.Q * /\pump:pump_stateSBV_1\.Q * fiber_to_ibus_buf_12.Q * /fiber_to_ibus_buf_4.Q * /fifo_out(8) fiber_to_ibus_buf_4.C = clk fiber_to_ibus_buf_5.T = \pump:pump_stateSBV_0\.Q * /\pump:pump_stateSBV_1\.Q * /fiber_to_ibus_buf_13.Q * fiber_to_ibus_buf_5.Q * /fifo_out(8) + \pump:pump_stateSBV_0\.Q * /\pump:pump_stateSBV_1\.Q * fiber_to_ibus_buf_13.Q * /fiber_to_ibus_buf_5.Q * /fifo_out(8) fiber_to_ibus_buf_5.C = clk fiber_to_ibus_buf_6.T = \pump:pump_stateSBV_0\.Q * /\pump:pump_stateSBV_1\.Q * /fiber_to_ibus_buf_14.Q * fiber_to_ibus_buf_6.Q * /fifo_out(8) + \pump:pump_stateSBV_0\.Q * /\pump:pump_stateSBV_1\.Q * fiber_to_ibus_buf_14.Q * /fiber_to_ibus_buf_6.Q * /fifo_out(8) fiber_to_ibus_buf_6.C = clk fiber_to_ibus_buf_7.T = \pump:pump_stateSBV_0\.Q * /\pump:pump_stateSBV_1\.Q * /fiber_to_ibus_buf_15.Q * fiber_to_ibus_buf_7.Q * /fifo_out(8) + \pump:pump_stateSBV_0\.Q * /\pump:pump_stateSBV_1\.Q * fiber_to_ibus_buf_15.Q * /fiber_to_ibus_buf_7.Q * /fifo_out(8) fiber_to_ibus_buf_7.C = clk fiber_to_ibus_buf_8.T = \pump:pump_stateSBV_0\.Q * /\pump:pump_stateSBV_1\.Q * /fiber_to_ibus_buf_8.Q * fifo_out(0) * /fifo_out(8) + \pump:pump_stateSBV_0\.Q * /\pump:pump_stateSBV_1\.Q * fiber_to_ibus_buf_8.Q * /fifo_out(0) * /fifo_out(8) fiber_to_ibus_buf_8.C = clk fiber_to_ibus_buf_9.T = \pump:pump_stateSBV_0\.Q * /\pump:pump_stateSBV_1\.Q * /fiber_to_ibus_buf_9.Q * fifo_out(1) * /fifo_out(8) + \pump:pump_stateSBV_0\.Q * /\pump:pump_stateSBV_1\.Q * fiber_to_ibus_buf_9.Q * /fifo_out(1) * /fifo_out(8) fiber_to_ibus_buf_9.C = clk fifo_d(0).T = /\fr_imp:fr_stateSBV_0\.Q * /fifo_d(0).Q * fr_d(0) * /fr_rdy_l * fr_status * /reset_fifo.Q + /\fr_imp:fr_stateSBV_0\.Q * fifo_d(0).Q * /fr_d(0) * /fr_rdy_l * fr_status * /reset_fifo.Q fifo_d(0).C = clk fifo_d(1).T = /\fr_imp:fr_stateSBV_0\.Q * /fifo_d(1).Q * fr_d(1) * /fr_rdy_l * fr_status * /reset_fifo.Q + /\fr_imp:fr_stateSBV_0\.Q * fifo_d(1).Q * /fr_d(1) * /fr_rdy_l * fr_status * /reset_fifo.Q fifo_d(1).C = clk fifo_d(2).T = /\fr_imp:fr_stateSBV_0\.Q * /fifo_d(2).Q * fr_d(2) * /fr_rdy_l * fr_status * /reset_fifo.Q + /\fr_imp:fr_stateSBV_0\.Q * fifo_d(2).Q * /fr_d(2) * /fr_rdy_l * fr_status * /reset_fifo.Q fifo_d(2).C = clk fifo_d(3).T = /\fr_imp:fr_stateSBV_0\.Q * /fifo_d(3).Q * fr_d(3) * /fr_rdy_l * fr_status * /reset_fifo.Q + /\fr_imp:fr_stateSBV_0\.Q * fifo_d(3).Q * /fr_d(3) * /fr_rdy_l * fr_status * /reset_fifo.Q fifo_d(3).C = clk fifo_d(4).T = /\fr_imp:fr_stateSBV_0\.Q * /fifo_d(4).Q * fr_d(4) * /fr_rdy_l * fr_status * /reset_fifo.Q + /\fr_imp:fr_stateSBV_0\.Q * fifo_d(4).Q * /fr_d(4) * /fr_rdy_l * fr_status * /reset_fifo.Q fifo_d(4).C = clk fifo_d(5).T = /\fr_imp:fr_stateSBV_0\.Q * /fifo_d(5).Q * fr_d(5) * /fr_rdy_l * fr_status * /reset_fifo.Q + /\fr_imp:fr_stateSBV_0\.Q * fifo_d(5).Q * /fr_d(5) * /fr_rdy_l * fr_status * /reset_fifo.Q fifo_d(5).C = clk fifo_d(6).T = /\fr_imp:fr_stateSBV_0\.Q * /fifo_d(6).Q * fr_d(6) * /fr_rdy_l * fr_status * /reset_fifo.Q + /\fr_imp:fr_stateSBV_0\.Q * fifo_d(6).Q * /fr_d(6) * /fr_rdy_l * fr_status * /reset_fifo.Q fifo_d(6).C = clk fifo_d(7).T = /\fr_imp:fr_stateSBV_0\.Q * /fifo_d(7).Q * fr_d(7) * /fr_rdy_l * fr_status * /reset_fifo.Q + /\fr_imp:fr_stateSBV_0\.Q * fifo_d(7).Q * /fr_d(7) * /fr_rdy_l * fr_status * /reset_fifo.Q fifo_d(7).C = clk fifo_d(8).T = /\fr_imp:fr_stateSBV_0\.Q * /fifo_d(8).Q * fr_d(8) * /fr_rdy_l * fr_status * /reset_fifo.Q + /\fr_imp:fr_stateSBV_0\.Q * fifo_d(8).Q * /fr_d(8) * /fr_rdy_l * fr_status * /reset_fifo.Q fifo_d(8).C = clk /fifo_read_l.D = /\pump:pump_stateSBV_0\.Q * \pump:pump_stateSBV_1\.Q fifo_read_l.AP = GND fifo_read_l.AR = reset fifo_read_l.C = clk fifo_reset_l.D = /\fr_imp:fr_stateSBV_0\.Q * /fr_rdy_l * fr_status * /reset_fifo.Q + fifo_reset_l.Q * /reset_fifo.Q fifo_reset_l.AP = reset_fifo.Q fifo_reset_l.AR = GND fifo_reset_l.C = clk fifo_write_l.T = /\fr_imp:fr_stateSBV_0\.Q * fifo_write_l.Q * /fr_rdy_l * fr_status * /reset_fifo.Q + \fr_imp:fr_stateSBV_0\.Q * /fifo_write_l.Q * /reset_fifo.Q fifo_write_l.AP = reset_fifo.Q fifo_write_l.AR = GND fifo_write_l.C = clk fo_ckw.D = /fo_ckw.Q fo_ckw.C = clk fo_d(0).T = /\ibus_fo:stateSBV_0\.Q * /\ibus_fo:stateSBV_1\.Q * /\ibus_fo:stateSBV_2\.Q * /data_to_fo_0.Q * fo_d(0).Q * write_to_fo_req.Q + /\ibus_fo:stateSBV_0\.Q * /\ibus_fo:stateSBV_1\.Q * /\ibus_fo:stateSBV_2\.Q * data_to_fo_0.Q * /fo_d(0).Q * write_to_fo_req.Q + /\ibus_fo:stateSBV_0\.Q * \ibus_fo:stateSBV_1\.Q * \ibus_fo:stateSBV_2\.Q * /data_to_fo_8.Q * fo_d(0).Q + \ibus_fo:stateSBV_1\.Q * \ibus_fo:stateSBV_2\.Q * data_to_fo_8.Q * /fo_d(0).Q fo_d(0).C = clk fo_d(1).T = /\ibus_fo:stateSBV_0\.Q * /\ibus_fo:stateSBV_1\.Q * /\ibus_fo:stateSBV_2\.Q * /data_to_fo_1.Q * fo_d(1).Q * write_to_fo_req.Q + /\ibus_fo:stateSBV_0\.Q * /\ibus_fo:stateSBV_1\.Q * /\ibus_fo:stateSBV_2\.Q * data_to_fo_1.Q * /fo_d(1).Q * write_to_fo_req.Q + /\ibus_fo:stateSBV_0\.Q * \ibus_fo:stateSBV_1\.Q * \ibus_fo:stateSBV_2\.Q * /data_to_fo_9.Q * fo_d(1).Q + \ibus_fo:stateSBV_1\.Q * \ibus_fo:stateSBV_2\.Q * data_to_fo_9.Q * /fo_d(1).Q fo_d(1).C = clk fo_d(2).T = /\ibus_fo:stateSBV_0\.Q * /\ibus_fo:stateSBV_1\.Q * /\ibus_fo:stateSBV_2\.Q * /data_to_fo_2.Q * fo_d(2).Q * write_to_fo_req.Q + /\ibus_fo:stateSBV_0\.Q * /\ibus_fo:stateSBV_1\.Q * /\ibus_fo:stateSBV_2\.Q * data_to_fo_2.Q * /fo_d(2).Q * write_to_fo_req.Q + /\ibus_fo:stateSBV_0\.Q * \ibus_fo:stateSBV_1\.Q * \ibus_fo:stateSBV_2\.Q * /data_to_fo_10.Q * fo_d(2).Q + \ibus_fo:stateSBV_1\.Q * \ibus_fo:stateSBV_2\.Q * data_to_fo_10.Q * /fo_d(2).Q fo_d(2).C = clk fo_d(3).T = /\ibus_fo:stateSBV_0\.Q * /\ibus_fo:stateSBV_1\.Q * /\ibus_fo:stateSBV_2\.Q * /data_to_fo_3.Q * fo_d(3).Q * write_to_fo_req.Q + /\ibus_fo:stateSBV_0\.Q * /\ibus_fo:stateSBV_1\.Q * /\ibus_fo:stateSBV_2\.Q * data_to_fo_3.Q * /fo_d(3).Q * write_to_fo_req.Q + /\ibus_fo:stateSBV_0\.Q * \ibus_fo:stateSBV_1\.Q * \ibus_fo:stateSBV_2\.Q * /data_to_fo_11.Q * fo_d(3).Q + \ibus_fo:stateSBV_1\.Q * \ibus_fo:stateSBV_2\.Q * data_to_fo_11.Q * /fo_d(3).Q fo_d(3).C = clk fo_d(4).T = /\ibus_fo:stateSBV_0\.Q * /\ibus_fo:stateSBV_1\.Q * /\ibus_fo:stateSBV_2\.Q * /data_to_fo_4.Q * fo_d(4).Q * write_to_fo_req.Q + /\ibus_fo:stateSBV_0\.Q * /\ibus_fo:stateSBV_1\.Q * /\ibus_fo:stateSBV_2\.Q * data_to_fo_4.Q * /fo_d(4).Q * write_to_fo_req.Q + /\ibus_fo:stateSBV_0\.Q * \ibus_fo:stateSBV_1\.Q * \ibus_fo:stateSBV_2\.Q * /data_to_fo_12.Q * fo_d(4).Q + \ibus_fo:stateSBV_1\.Q * \ibus_fo:stateSBV_2\.Q * data_to_fo_12.Q * /fo_d(4).Q fo_d(4).C = clk fo_d(5).T = /\ibus_fo:stateSBV_0\.Q * /\ibus_fo:stateSBV_1\.Q * /\ibus_fo:stateSBV_2\.Q * /data_to_fo_5.Q * fo_d(5).Q * write_to_fo_req.Q + /\ibus_fo:stateSBV_0\.Q * /\ibus_fo:stateSBV_1\.Q * /\ibus_fo:stateSBV_2\.Q * data_to_fo_5.Q * /fo_d(5).Q * write_to_fo_req.Q + /\ibus_fo:stateSBV_0\.Q * \ibus_fo:stateSBV_1\.Q * \ibus_fo:stateSBV_2\.Q * /data_to_fo_13.Q * fo_d(5).Q + \ibus_fo:stateSBV_1\.Q * \ibus_fo:stateSBV_2\.Q * data_to_fo_13.Q * /fo_d(5).Q fo_d(5).C = clk fo_d(6).T = /\ibus_fo:stateSBV_0\.Q * /\ibus_fo:stateSBV_1\.Q * /\ibus_fo:stateSBV_2\.Q * /data_to_fo_6.Q * fo_d(6).Q * write_to_fo_req.Q + /\ibus_fo:stateSBV_0\.Q * /\ibus_fo:stateSBV_1\.Q * /\ibus_fo:stateSBV_2\.Q * data_to_fo_6.Q * /fo_d(6).Q * write_to_fo_req.Q + /\ibus_fo:stateSBV_0\.Q * \ibus_fo:stateSBV_1\.Q * \ibus_fo:stateSBV_2\.Q * /data_to_fo_14.Q * fo_d(6).Q + \ibus_fo:stateSBV_1\.Q * \ibus_fo:stateSBV_2\.Q * data_to_fo_14.Q * /fo_d(6).Q fo_d(6).C = clk fo_d(7).T = /\ibus_fo:stateSBV_0\.Q * /\ibus_fo:stateSBV_1\.Q * /\ibus_fo:stateSBV_2\.Q * /data_to_fo_7.Q * fo_d(7).Q * write_to_fo_req.Q + /\ibus_fo:stateSBV_0\.Q * /\ibus_fo:stateSBV_1\.Q * /\ibus_fo:stateSBV_2\.Q * data_to_fo_7.Q * /fo_d(7).Q * write_to_fo_req.Q + /\ibus_fo:stateSBV_0\.Q * \ibus_fo:stateSBV_1\.Q * \ibus_fo:stateSBV_2\.Q * /data_to_fo_15.Q * fo_d(7).Q + \ibus_fo:stateSBV_1\.Q * \ibus_fo:stateSBV_2\.Q * data_to_fo_15.Q * /fo_d(7).Q fo_d(7).C = clk fo_d(8).T = /\ibus_fo:stateSBV_0\.Q * /\ibus_fo:stateSBV_1\.Q * /\ibus_fo:stateSBV_2\.Q * fo_d(8).Q fo_d(8).C = clk fo_d(9).T = /\ibus_fo:stateSBV_0\.Q * /\ibus_fo:stateSBV_1\.Q * /\ibus_fo:stateSBV_2\.Q * fo_d(9).Q fo_d(9).C = clk fo_ena_l.D = /\ibus_fo:stateSBV_1\.Q * /\ibus_fo:stateSBV_2\.Q * fo_ena_l.Q + /\ibus_fo:stateSBV_1\.Q * fo_ena_l.Q * /fr_ref_clk.CMB fo_ena_l.C = clk fo_enn_l = VCC fo_foto = GND fo_mode = GND fr_mode = GND fr_ref_clk = fo_ckw.Q fr_rf = VCC id(0).T = /\fi_reader:fi_read_stateSBV_0\.Q * /\fi_reader:fi_read_stateSBV_1\.Q * /\fi_reader:fi_read_stateSBV_2\.Q * /fi_data_0.Q * fi_to_ibus_req.Q * id(0).Q + /\fi_reader:fi_read_stateSBV_0\.Q * /\fi_reader:fi_read_stateSBV_1\.Q * /\fi_reader:fi_read_stateSBV_2\.Q * fi_data_0.Q * fi_to_ibus_req.Q * /id(0).Q id(0).C = clk id(1).T = /\fi_reader:fi_read_stateSBV_0\.Q * /\fi_reader:fi_read_stateSBV_1\.Q * /\fi_reader:fi_read_stateSBV_2\.Q * /fi_data_1.Q * fi_to_ibus_req.Q * id(1).Q + /\fi_reader:fi_read_stateSBV_0\.Q * /\fi_reader:fi_read_stateSBV_1\.Q * /\fi_reader:fi_read_stateSBV_2\.Q * fi_data_1.Q * fi_to_ibus_req.Q * /id(1).Q id(1).C = clk id(10).T = /\fi_reader:fi_read_stateSBV_0\.Q * /\fi_reader:fi_read_stateSBV_1\.Q * /\fi_reader:fi_read_stateSBV_2\.Q * /fi_data_10.Q * fi_to_ibus_req.Q * id(10).Q + /\fi_reader:fi_read_stateSBV_0\.Q * /\fi_reader:fi_read_stateSBV_1\.Q * /\fi_reader:fi_read_stateSBV_2\.Q * fi_data_10.Q * fi_to_ibus_req.Q * /id(10).Q id(10).C = clk id(11).T = /\fi_reader:fi_read_stateSBV_0\.Q * /\fi_reader:fi_read_stateSBV_1\.Q * /\fi_reader:fi_read_stateSBV_2\.Q * /fi_data_11.Q * fi_to_ibus_req.Q * id(11).Q + /\fi_reader:fi_read_stateSBV_0\.Q * /\fi_reader:fi_read_stateSBV_1\.Q * /\fi_reader:fi_read_stateSBV_2\.Q * fi_data_11.Q * fi_to_ibus_req.Q * /id(11).Q id(11).C = clk id(12).T = /\fi_reader:fi_read_stateSBV_0\.Q * /\fi_reader:fi_read_stateSBV_1\.Q * /\fi_reader:fi_read_stateSBV_2\.Q * /fi_data_12.Q * fi_to_ibus_req.Q * id(12).Q + /\fi_reader:fi_read_stateSBV_0\.Q * /\fi_reader:fi_read_stateSBV_1\.Q * /\fi_reader:fi_read_stateSBV_2\.Q * fi_data_12.Q * fi_to_ibus_req.Q * /id(12).Q id(12).C = clk id(13).T = /\fi_reader:fi_read_stateSBV_0\.Q * /\fi_reader:fi_read_stateSBV_1\.Q * /\fi_reader:fi_read_stateSBV_2\.Q * /fi_data_13.Q * fi_to_ibus_req.Q * id(13).Q + /\fi_reader:fi_read_stateSBV_0\.Q * /\fi_reader:fi_read_stateSBV_1\.Q * /\fi_reader:fi_read_stateSBV_2\.Q * fi_data_13.Q * fi_to_ibus_req.Q * /id(13).Q id(13).C = clk id(14).T = /\fi_reader:fi_read_stateSBV_0\.Q * /\fi_reader:fi_read_stateSBV_1\.Q * /\fi_reader:fi_read_stateSBV_2\.Q * /fi_data_14.Q * fi_to_ibus_req.Q * id(14).Q + /\fi_reader:fi_read_stateSBV_0\.Q * /\fi_reader:fi_read_stateSBV_1\.Q * /\fi_reader:fi_read_stateSBV_2\.Q * fi_data_14.Q * fi_to_ibus_req.Q * /id(14).Q id(14).C = clk id(15).T = /\fi_reader:fi_read_stateSBV_0\.Q * /\fi_reader:fi_read_stateSBV_1\.Q * /\fi_reader:fi_read_stateSBV_2\.Q * /fi_data_15.Q * fi_to_ibus_req.Q * id(15).Q + /\fi_reader:fi_read_stateSBV_0\.Q * /\fi_reader:fi_read_stateSBV_1\.Q * /\fi_reader:fi_read_stateSBV_2\.Q * fi_data_15.Q * fi_to_ibus_req.Q * /id(15).Q id(15).C = clk id(2).T = /\fi_reader:fi_read_stateSBV_0\.Q * /\fi_reader:fi_read_stateSBV_1\.Q * /\fi_reader:fi_read_stateSBV_2\.Q * /fi_data_2.Q * fi_to_ibus_req.Q * id(2).Q + /\fi_reader:fi_read_stateSBV_0\.Q * /\fi_reader:fi_read_stateSBV_1\.Q * /\fi_reader:fi_read_stateSBV_2\.Q * fi_data_2.Q * fi_to_ibus_req.Q * /id(2).Q id(2).C = clk id(3).T = /\fi_reader:fi_read_stateSBV_0\.Q * /\fi_reader:fi_read_stateSBV_1\.Q * /\fi_reader:fi_read_stateSBV_2\.Q * /fi_data_3.Q * fi_to_ibus_req.Q * id(3).Q + /\fi_reader:fi_read_stateSBV_0\.Q * /\fi_reader:fi_read_stateSBV_1\.Q * /\fi_reader:fi_read_stateSBV_2\.Q * fi_data_3.Q * fi_to_ibus_req.Q * /id(3).Q id(3).C = clk id(4).T = /\fi_reader:fi_read_stateSBV_0\.Q * /\fi_reader:fi_read_stateSBV_1\.Q * /\fi_reader:fi_read_stateSBV_2\.Q * /fi_data_4.Q * fi_to_ibus_req.Q * id(4).Q + /\fi_reader:fi_read_stateSBV_0\.Q * /\fi_reader:fi_read_stateSBV_1\.Q * /\fi_reader:fi_read_stateSBV_2\.Q * fi_data_4.Q * fi_to_ibus_req.Q * /id(4).Q id(4).C = clk id(5).T = /\fi_reader:fi_read_stateSBV_0\.Q * /\fi_reader:fi_read_stateSBV_1\.Q * /\fi_reader:fi_read_stateSBV_2\.Q * /fi_data_5.Q * fi_to_ibus_req.Q * id(5).Q + /\fi_reader:fi_read_stateSBV_0\.Q * /\fi_reader:fi_read_stateSBV_1\.Q * /\fi_reader:fi_read_stateSBV_2\.Q * fi_data_5.Q * fi_to_ibus_req.Q * /id(5).Q id(5).C = clk id(6).T = /\fi_reader:fi_read_stateSBV_0\.Q * /\fi_reader:fi_read_stateSBV_1\.Q * /\fi_reader:fi_read_stateSBV_2\.Q * /fi_data_6.Q * fi_to_ibus_req.Q * id(6).Q + /\fi_reader:fi_read_stateSBV_0\.Q * /\fi_reader:fi_read_stateSBV_1\.Q * /\fi_reader:fi_read_stateSBV_2\.Q * fi_data_6.Q * fi_to_ibus_req.Q * /id(6).Q id(6).C = clk id(7).T = /\fi_reader:fi_read_stateSBV_0\.Q * /\fi_reader:fi_read_stateSBV_1\.Q * /\fi_reader:fi_read_stateSBV_2\.Q * /fi_data_7.Q * fi_to_ibus_req.Q * id(7).Q + /\fi_reader:fi_read_stateSBV_0\.Q * /\fi_reader:fi_read_stateSBV_1\.Q * /\fi_reader:fi_read_stateSBV_2\.Q * fi_data_7.Q * fi_to_ibus_req.Q * /id(7).Q id(7).C = clk id(8).T = /\fi_reader:fi_read_stateSBV_0\.Q * /\fi_reader:fi_read_stateSBV_1\.Q * /\fi_reader:fi_read_stateSBV_2\.Q * /fi_data_8.Q * fi_to_ibus_req.Q * id(8).Q + /\fi_reader:fi_read_stateSBV_0\.Q * /\fi_reader:fi_read_stateSBV_1\.Q * /\fi_reader:fi_read_stateSBV_2\.Q * fi_data_8.Q * fi_to_ibus_req.Q * /id(8).Q id(8).C = clk id(9).T = /\fi_reader:fi_read_stateSBV_0\.Q * /\fi_reader:fi_read_stateSBV_1\.Q * /\fi_reader:fi_read_stateSBV_2\.Q * /fi_data_9.Q * fi_to_ibus_req.Q * id(9).Q + /\fi_reader:fi_read_stateSBV_0\.Q * /\fi_reader:fi_read_stateSBV_1\.Q * /\fi_reader:fi_read_stateSBV_2\.Q * fi_data_9.Q * fi_to_ibus_req.Q * /id(9).Q id(9).C = clk refill_ibus_output_buf.D = fi_to_ibus_ack.Q + /\ibus_fi:read_stateSBV_0\.Q refill_ibus_output_buf.AP = GND refill_ibus_output_buf.AR = reset refill_ibus_output_buf.C = clk reset_fifo.D = /\fi_reader:fi_read_stateSBV_0\.Q * /\fi_reader:fi_read_stateSBV_1\.Q * \fi_reader:fi_read_stateSBV_2\.Q * /fi_data_10.Q * /fi_data_11.Q * fi_data_12.Q * fi_data_15.Q * fi_data_5.Q * /fi_data_8.Q * fi_data_9.Q reset_fifo.C = clk write_to_fo_ack.T = /\ibus_fo:stateSBV_0\.Q * /\ibus_fo:stateSBV_1\.Q * /\ibus_fo:stateSBV_2\.Q * write_to_fo_ack.Q + /\ibus_fo:stateSBV_1\.Q * \ibus_fo:stateSBV_2\.Q * fr_ref_clk.CMB * /write_to_fo_ack.Q write_to_fo_ack.C = clk write_to_fo_req.D = \ibus_reader:iu_readSBV_0\.Q * /\ibus_reader:iu_readSBV_1\.Q * /write_to_fo_ack.Q + /\ibus_reader:iu_readSBV_0\.Q * \ibus_reader:iu_readSBV_1\.Q write_to_fo_req.C = clk Completed Successfully ---------------------------------------------------------------------------- PLD Compiler Software: C37KFIT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 DESIGN RULE CHECK (12:09:51) Messages: None. Summary: Error Count = 0 Warning Count = 0 Completed Successfully ---------------------------------------------------------------------------- PLD Compiler Software: C37KFIT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 PARTITION LOGIC (12:09:52) Messages: Information: Initializing Logic Block structures. Information: Forming input seeds. Information: Checking for duplicate NODE logic. Information: Forming input seeds. Information: Assigning fixed logic to Logic Blocks. Information: Processing banked global preset, reset and output enable. Information: Separating output logic set to GND/VCC. Information: Validating Logic Block's with pre-placed signals. Information: Separating input register logic. Information: Assigning initializing equations to empty Logic Blocks. Information: Separating output combinatorial logic. Information: Separating disjoint output logic. Information: Separating output node logic. Information: Assigning floating outputs to Logic Blocks. Information: Compacting Logic Block interconnect. .+...+..........+.....................................................+ ...+................................................................... .............................................. Information: Separating disjoint output logic. Information: Separating output node logic. Information: Assigning floating outputs to Logic Blocks. Information: Assigning floating outputs to Logic Blocks. Information: Minimizing interconnect between Logic Blocks. .+...+............++...............++............... Start=12:09:55 End=12:09:57 Summary: Error Count = 0 Warning Count = 0 Completed Successfully ---------------------------------------------------------------------------- PLD Compiler Software: C37KFIT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 DESIGN SIGNAL PLACEMENT (12:09:57) Messages: Information: Fitting signals to Logic Block A. Information: Assigning Signals to Macrocells. Information: Improving Macrocell Assignment ................ Information: Assigning Product Terms to Allocator Information: Combining 'fi_data_9' definition with input pin 'fifo_empty_l'. Information: Combining 'fiber_to_ibus_buf_8' definition with input pin 'fifo_out(8)'. Information: Fitting signals to Logic Block B. Information: Assigning Signals to Macrocells. Information: Improving Macrocell Assignment ................ Information: Assigning Product Terms to Allocator Information: Combining 'fiber_to_ibus_buf_10' definition with input pin 'fifo_out(3)'. Information: Combining 'fiber_to_ibus_buf_11' definition with input pin 'fifo_out(4)'. Information: Combining 'fiber_to_ibus_buf_14' definition with input pin 'fifo_out(2)'. Information: Combining 'fiber_to_ibus_buf_15' definition with input pin 'fifo_out(5)'. Information: Combining 'fiber_to_ibus_buf_6' definition with input pin 'fifo_out(0)'. Information: Fitting signals to Logic Block C. Information: Assigning Signals to Macrocells. Information: Improving Macrocell Assignment ................ Information: Assigning Product Terms to Allocator Information: Fitting signals to Logic Block D. Information: Assigning Signals to Macrocells. Information: Improving Macrocell Assignment ................ Information: Assigning Product Terms to Allocator Information: Fitting signals to Logic Block E. Information: Assigning Signals to Macrocells. Information: Improving Macrocell Assignment ................ Information: Assigning Product Terms to Allocator Information: Combining '\ibus_reader:timeout_1\' definition with input pin 'id(16)'. Information: Combining '\ibus_reader:iu_readSBV_0\' definition with input pin 'id(17)'. Information: Combining '\ibus_reader:timeout_3\' definition with input pin 'id(18)'. Information: Fitting signals to Logic Block F. Information: Fitting signals to Logic Block G. Information: Assigning Signals to Macrocells. Information: Assigning Product Terms to Allocator Information: Fitting signals to Logic Block H. Information: Assigning Signals to Macrocells. Information: Improving Macrocell Assignment ..+.............................. Information: Assigning Product Terms to Allocator Information: Assigning Signals to Macrocells. Information: Improving Macrocell Assignment ................ Information: Assigning Product Terms to Allocator Information: Assigning Signals to Macrocells. Information: Improving Macrocell Assignment ................ Information: Assigning Product Terms to Allocator Information: Combining '\fi_reader:fi_read_stateSBV_2\' definition with input pin 'ao_to_pc_strobe'. Information: Combining 'data_to_fo_8' definition with input pin 'ao_from_pc_ack'. Information: Fitting signals to Logic Block I. Information: Fitting signals to Logic Block J. Information: Assigning Signals to Macrocells. Information: Assigning Product Terms to Allocator Information: Fitting signals to Logic Block K. Information: Assigning Signals to Macrocells. Information: Improving Macrocell Assignment ................ Information: Assigning Product Terms to Allocator Information: Combining 'fi_data_1' definition with input pin 'fr_status'. Information: Fitting signals to Logic Block L. Information: Fitting signals to Logic Block M. Information: Assigning Signals to Macrocells. Information: Improving Macrocell Assignment ................ Information: Assigning Product Terms to Allocator Information: Fitting signals to Logic Block N. Information: Assigning Signals to Macrocells. Information: Improving Macrocell Assignment ................ Information: Assigning Product Terms to Allocator Information: Fitting signals to Logic Block O. Information: Assigning Signals to Macrocells. Information: Improving Macrocell Assignment ................ Information: Assigning Product Terms to Allocator Information: Fitting signals to Logic Block P. Information: Assigning Signals to Macrocells. Information: Improving Macrocell Assignment ................ Information: Assigning Product Terms to Allocator Information: Routing signals to Logic Blocks. Summary: Error Count = 0 Warning Count = 0 Completed Successfully ---------------------------------------------------------------------------- PLD Compiler Software: C37KFIT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 LOGIC BLOCK A PLACEMENT (12:09:57) Messages: ________________________________________________________________________________ 1111111111222222222233333333334444444444555555555566666666667777777777 01234567890123456789012345678901234567890123456789012345678901234567890123456789 ________________________________________________________________________________ | 0 |(fiber_to_ibus_buf_9) XX++++++++++++++................................................................ | 1 |(fiber_to_ibus_buf_7) ......XX++++++++++++++.......................................................... | 2 |(fiber_to_ibus_buf_0) ..........XX++++++++++++++...................................................... | 3 |(\pump:pump_stateSBV_0\) ..............XXXXX+++++++++++.................................................. | 4 |(data_pump_word_ready) ..................++++X+++++++++++.............................................. | 5 |(\pump:pump_stateSBV_1\) ......................XX++X+++++++++++.......................................... | 6>|fifo_read_l ..........................X+++++++++++++++...................................... | 7 |(\fi_reader:this_is_a_ctrl_transaction\) ..............................XXXX+X++++++++++.................................. | 8 |(\pump:count_0\) ..................................X+XX++++++++++++.............................. | 9 |(\pump:count_1\) ......................................XX++++++++++++++.......................... |10 |(fi_data_15) ..........................................XX++++++++++++++...................... |11 |(fi_data_8) ..............................................XX++++++++++++++.................. |12 |(fi_data_9)fifo_empty_l ..................................................XX++++++++++++++.............. |13 |(fiber_to_ibus_buf_1) ......................................................XX++++++++++++++.......... |14 |(fiber_to_ibus_buf_8)fifo_out(8) ..........................................................XX++++++++++++++...... |15 |(reset_fifo) ................................................................++X+++++++++++++ ________________________________________________________________________________ Total count of outputs placed = 16 Total count of unique Product Terms = 35 Total Product Terms to be assigned = 37 Max Product Terms used / available = 35 / 80 = 43.76 % Control Signals for Logic Block A --------------------------------- CLK pin 19 : CLK pin 22 : clk CLK pin 99 : CLK pin 102 : CLK PT : AH : PRESET : AH : GND RESET : AH : reset OE 0 : AH : OE 1 : AH : OE 2 : AH : OE 3 : AH : Logic Block A ____________________________________________ | |= >fiber_to_ib.. | | | |= >\pump:pump_.. | | | |= >fiber_to_ib.. | | | |= >fifo_out(8) | | | |= >\fi_reader:.. |143|= (fiber_to_ibus_buf_9) | |= >fiber_to_ib.. | | | |> not used:268 (fiber_to_ibus_buf_7) =| | | |= >fifo_out(0) | | | |= >reset |144|= (fiber_to_ibus_buf_0) | |= >\pump:pump_.. | | | |= >fi_data_8.Q (\pump:pump_stateSBV_0\) =| | | |= >fi_data_9.Q | | | |= >fifo_empty_l |145|= (data_pump_word_ready) | |= >fi_data_12.Q | | | |= >\fi_reader:.. (\pump:pump_stateSBV_1\) =| | | |> not used:277 | | | |= >fiber_to_ib.. |146|= fifo_read_l | |= >\pump:count.. | | | |= >fifo_reset_.. (\fi_reader:this_is_a_ctrl_transaction\) =| | | |= >\pump:count.. | | | |= >fi_data_15.Q |147|= (\pump:count_0\) | |= >fi_data_5.Q | | | |= >fifo_out(1) (\pump:count_1\) =| | | |= >\ibus_fi:re.. | | | |= >data_pump_w.. |148|= (fi_data_15) | |= >refill_ibus.. | | | |> not used:288 (fi_data_8) =| | | |= >\ibus_fi:re.. | | | |= >\fi_reader:.. |149|= (fi_data_9)fifo_empty_l | |= >fi_data_11.Q | | | |= >fiber_to_ib.. (fiber_to_ibus_buf_1) =| | | |> not used:293 | | | |= >\fi_reader:.. |150|= (fiber_to_ibus_buf_8)fifo_out(8) | |= >fiber_to_ib.. | | | |= >fi_to_ibus_.. (reset_fifo) =| | | |> not used:297 | | | |> not used:298 | | | |> not used:299 | | | |= >fi_data_10.Q | | ____________________________________________ Information: Macrocell Utilization. Description Used Max ______________________________________ | I/O Macrocells | 8 | 8 | | Buried Macrocells | 8 | 8 | | PIM Input Connects | 32 | 36 | ______________________________________ 48 / 52 = 92 % ---------------------------------------------------------------------------- PLD Compiler Software: C37KFIT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 LOGIC BLOCK B PLACEMENT (12:09:57) Messages: ________________________________________________________________________________ 1111111111222222222233333333334444444444555555555566666666667777777777 01234567890123456789012345678901234567890123456789012345678901234567890123456789 ________________________________________________________________________________ | 0 |(fiber_to_ibus_buf_6)fifo_out(0) XX++++++++++++++................................................................ | 1 |UNUSED ......++++++++++++++++.......................................................... | 2 |[i/p] ..........++++++++++++++++...................................................... | 3 |(fiber_to_ibus_buf_2) ..............XX++++++++++++++.................................................. | 4 |(fiber_to_ibus_buf_14)fifo_out(2) ..................XX++++++++++++++.............................................. | 5 |(fiber_to_ibus_buf_12) ......................XX++++++++++++++.......................................... | 6 |(fiber_to_ibus_buf_10)fifo_out(3) ..........................XX++++++++++++++...................................... | 7 |(fiber_to_ibus_buf_4) ..............................XX++++++++++++++.................................. | 8 |(fiber_to_ibus_buf_11)fifo_out(4) ..................................XX++++++++++++++.............................. | 9 |(fiber_to_ibus_buf_13) ......................................XX++++++++++++++.......................... |10 |(fiber_to_ibus_buf_15)fifo_out(5) ..........................................XX++++++++++++++...................... |11 |(fiber_to_ibus_buf_3) ..............................................XX++++++++++++++.................. |12 |[i/p] ..................................................++++++++++++++++.............. |13 |UNUSED ......................................................++++++++++++++++.......... |14 |[i/p] ..........................................................++++++++++++++++...... |15 |(fiber_to_ibus_buf_5) ................................................................XX++++++++++++++ ________________________________________________________________________________ Total count of outputs placed = 11 Total count of unique Product Terms = 22 Total Product Terms to be assigned = 22 Max Product Terms used / available = 22 / 80 = 27.51 % Control Signals for Logic Block B --------------------------------- CLK pin 19 : CLK pin 22 : clk CLK pin 99 : CLK pin 102 : CLK PT : AH : PRESET : AH : RESET : AH : OE 0 : AH : OE 1 : AH : OE 2 : AH : OE 3 : AH : Logic Block B ____________________________________________ | |> not used:301 | | | |= >fiber_to_ib.. | | | |= >fifo_out(2) | | | |= >fifo_out(8) | | | |= >fiber_to_ib.. |152|= (fiber_to_ibus_buf_6)fifo_out(0) | |= >fifo_out(7) | | | |= >fiber_to_ib.. not used:903 >| | | |= >fiber_to_ib.. | | | |= >fifo_out(4) |153|= fifo_out(1) | |= >\pump:pump_.. | | | |= >fiber_to_ib.. (fiber_to_ibus_buf_2) =| | | |= >fifo_out(5) | | | |= >fiber_to_ib.. |154|= (fiber_to_ibus_buf_14)fifo_out(2) | |= >fiber_to_ib.. | | | |> not used:315 (fiber_to_ibus_buf_12) =| | | |= >fifo_out(3) | | | |= >fiber_to_ib.. |155|= (fiber_to_ibus_buf_10)fifo_out(3) | |> not used:318 | | | |> not used:319 (fiber_to_ibus_buf_4) =| | | |= >fiber_to_ib.. | | | |> not used:321 |156|= (fiber_to_ibus_buf_11)fifo_out(4) | |> not used:322 | | | |= >fiber_to_ib.. (fiber_to_ibus_buf_13) =| | | |= >fifo_out(6) | | | |> not used:325 |157|= (fiber_to_ibus_buf_15)fifo_out(5) | |> not used:326 | | | |> not used:327 (fiber_to_ibus_buf_3) =| | | |> not used:328 | | | |> not used:329 |158|= fifo_out(6) | |> not used:330 | | | |> not used:331 not used:915 >| | | |> not used:332 | | | |> not used:333 |159|= fifo_out(7) | |> not used:334 | | | |> not used:335 (fiber_to_ibus_buf_5) =| | | |> not used:336 | | | |> not used:337 | | | |= >fiber_to_ib.. | | | |= >\pump:pump_.. | | ____________________________________________ Information: Macrocell Utilization. Description Used Max ______________________________________ | I/O Macrocells | 8 | 8 | | Buried Macrocells | 6 | 8 | | PIM Input Connects | 20 | 36 | ______________________________________ 34 / 52 = 65 % ---------------------------------------------------------------------------- PLD Compiler Software: C37KFIT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 LOGIC BLOCK C PLACEMENT (12:09:58) Messages: ________________________________________________________________________________ 1111111111222222222233333333334444444444555555555566666666667777777777 01234567890123456789012345678901234567890123456789012345678901234567890123456789 ________________________________________________________________________________ | 0>|id(0) XX++++++++++++++................................................................ | 1 |UNUSED ......++++++++++++++++.......................................................... | 2>|id(1) ..........XX++++++++++++++...................................................... | 3 |(data_to_fo_0) ..............XX++++++++++++++.................................................. | 4>|id(2) ..................XX++++++++++++++.............................................. | 5 |(data_to_fo_1) ......................XX++++++++++++++.......................................... | 6>|id(3) ..........................XX++++++++++++++...................................... | 7 |(data_to_fo_10) ..............................XX++++++++++++++.................................. | 8 |(data_to_fo_13) ..................................XX++++++++++++++.............................. | 9 |(data_to_fo_11) ......................................XX++++++++++++++.......................... |10>|id(4) ..........................................XX++++++++++++++...................... |11 |(data_to_fo_12) ..............................................XX++++++++++++++.................. |12>|id(5) ..................................................XX++++++++++++++.............. |13 |(data_to_fo_14) ......................................................XX++++++++++++++.......... |14>|id(6) ..........................................................XX++++++++++++++...... |15 |UNUSED ................................................................++++++++++++++++ ________________________________________________________________________________ Total count of outputs placed = 14 Total count of unique Product Terms = 28 Total Product Terms to be assigned = 28 Max Product Terms used / available = 28 / 80 = 35.1 % Control Signals for Logic Block C --------------------------------- CLK pin 19 : CLK pin 22 : clk CLK pin 99 : CLK pin 102 : CLK PT : AH : PRESET : AH : RESET : AH : OE 0 : AH : OE 1 : AH : OE 2 : AH : OE 3 : AH : Logic Block C ____________________________________________ | |= >ao_to_pc_st.. | | | |= >fi_data_2.Q | | | |= >fi_data_3.Q | | | |= >id(2).Q | | | |= >id(16) | 2|= id(0) | |= >fi_data_5.Q | | | |= >fi_data_1.Q not used:919 >| | | |= >\ibus_reade.. | | | |= >id(0).Q | 3|= id(1) | |= >id(29) | | | |> not used:350 (data_to_fo_0) =| | | |= >fi_to_ibus_.. | | | |= >id(1).Q | 4|= id(2) | |= >data_to_fo_.. | | | |= >id(3).Q (data_to_fo_1) =| | | |> not used:355 | | | |= >data_to_fo_.. | 5|= id(3) | |= >data_to_fo_.. | | | |= >\fi_reader:.. (data_to_fo_10) =| | | |= >data_to_fo_.. | | | |= >id(4).Q | 6|= (data_to_fo_13) | |= >data_to_fo_.. | | | |= >data_to_fo_.. (data_to_fo_11) =| | | |= >fi_data_6.Q | | | |= >data_to_fo_.. | 7|= id(4) | |= >id(17) | | | |= >id(30) (data_to_fo_12) =| | | |> not used:367 | | | |= >id(26) | 8|= id(5) | |= >id(5).Q | | | |= >\ibus_reade.. (data_to_fo_14) =| | | |= >id(27) | | | |= >\fi_reader:.. | 9|= id(6) | |= >id(6).Q | | | |= >id(28) not used:933 >| | | |> not used:375 | | | |= >fi_data_4.Q | | | |= >\fi_reader:.. | | | |= >fi_data_0.Q | | ____________________________________________ Information: Macrocell Utilization. Description Used Max ______________________________________ | I/O Macrocells | 8 | 8 | | Buried Macrocells | 6 | 8 | | PIM Input Connects | 35 | 36 | ______________________________________ 49 / 52 = 94 % ---------------------------------------------------------------------------- PLD Compiler Software: C37KFIT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 LOGIC BLOCK D PLACEMENT (12:09:58) Messages: ________________________________________________________________________________ 1111111111222222222233333333334444444444555555555566666666667777777777 01234567890123456789012345678901234567890123456789012345678901234567890123456789 ________________________________________________________________________________ | 0>|id(7) XX++++++++++++++................................................................ | 1 |(fi_data_10) ......XX++++++++++++++.......................................................... | 2>|id(8) ..........XX++++++++++++++...................................................... | 3 |(\ibus_fi:read_stateSBV_1\) ..............XXX+++++++++++++.................................................. | 4>|id(9) ..................XX++++++++++++++.............................................. | 5 |(\ibus_fi:timeout_1\) ......................XXXX++XXX+++++++.......................................... | 6>|id(10) ..........................XX++++++++++++++...................................... | 7 |(\ibus_fi:timeout_0\) ..............................++XX++XX++XX++++.................................. | 8>|id(11) ..................................XX++++++++++++++.............................. | 9 |(\ibus_fi:timeout_2\) ......................................XX++X+XX++++++++.......................... |10>|id(12) ..........................................+X+++X++++++++++...................... |11 |(\ibus_fi:read_stateSBV_0\) ..............................................X+XX++++++++++++.................. |12>|id(13) ..................................................XX++++++++++++++.............. |13 |(\ibus_fi:timeout_3\) ......................................................XXX+++++++++++++.......... |14>|id(14) ..........................................................XX++++++++++++++...... |15 |(fi_to_ibus_ack) ................................................................++X+++++++++++++ ________________________________________________________________________________ Total count of outputs placed = 16 Total count of unique Product Terms = 46 Total Product Terms to be assigned = 46 Max Product Terms used / available = 46 / 80 = 57.51 % Control Signals for Logic Block D --------------------------------- CLK pin 19 : CLK pin 22 : clk CLK pin 99 : CLK pin 102 : CLK PT : AH : PRESET : AH : RESET : AH : OE 0 : AH : OE 1 : AH : OE 2 : AH : OE 3 : AH : Logic Block D ____________________________________________ | |= >fi_data_7.Q | | | |= >\ibus_fi:ti.. | | | |= >id(8).Q | | | |> not used:382 | | | |= >fiber_to_ib.. | 11|= id(7) | |= >id(13).Q | | | |= >id(9).Q (fi_data_10) =| | | |= >\ibus_fi:ti.. | | | |= >fi_data_11.Q | 12|= id(8) | |= >id(10).Q | | | |= >fi_data_8.Q (\ibus_fi:read_stateSBV_1\) =| | | |= >id(7).Q | | | |= >\fi_reader:.. | 13|= id(9) | |= >fi_data_12.Q | | | |= >id(14).Q (\ibus_fi:timeout_1\) =| | | |= >fi_data_13.Q | | | |= >fi_data_14.Q | 14|= id(10) | |= >\ibus_fi:ti.. | | | |= >id(11).Q (\ibus_fi:timeout_0\) =| | | |= >fi_data_10.Q | | | |= >id(12).Q | 15|= id(11) | |> not used:400 | | | |= >\ibus_fi:re.. (\ibus_fi:timeout_2\) =| | | |= >fi_data_9.Q | | | |= >data_pump_w.. | 16|= id(12) | |> not used:404 | | | |> not used:405 (\ibus_fi:read_stateSBV_0\) =| | | |> not used:406 | | | |= >\fi_reader:.. | 17|= id(13) | |= >\ibus_fi:re.. | | | |= >fi_to_ibus_.. (\ibus_fi:timeout_3\) =| | | |> not used:410 | | | |> not used:411 | 18|= id(14) | |= >\ibus_fi:ti.. | | | |= >fi_to_ibus_.. (fi_to_ibus_ack) =| | | |> not used:414 | | | |> not used:415 | | | |= >\fi_reader:.. | | | |> not used:417 | | ____________________________________________ Information: Macrocell Utilization. Description Used Max ______________________________________ | I/O Macrocells | 8 | 8 | | Buried Macrocells | 8 | 8 | | PIM Input Connects | 29 | 36 | ______________________________________ 45 / 52 = 86 % ---------------------------------------------------------------------------- PLD Compiler Software: C37KFIT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 LOGIC BLOCK E PLACEMENT (12:09:58) Messages: ________________________________________________________________________________ 1111111111222222222233333333334444444444555555555566666666667777777777 01234567890123456789012345678901234567890123456789012345678901234567890123456789 ________________________________________________________________________________ | 0>|id(15) XX++++++++++++++................................................................ | 1 |(\ibus_reader:timeout_0\) ......XXXXXX++++++++++.......................................................... | 2 |(\ibus_reader:timeout_1\)id(16) ..........++XX++XX++XX++++...................................................... | 3 |(\ibus_reader:timeout_2\) ..............XX++X+++++XX++++.................................................. | 4 |(\ibus_reader:iu_readSBV_0\)id(17) ..................+X++XX++X+++++++.............................................. | 5 |(\ibus_reader:iu_readSBV_1\) ......................X++++X++X+++++++.......................................... | 6 |(\ibus_reader:timeout_3\)id(18) ..........................++XX++XX++++++++...................................... | 7 |UNUSED ..............................++++++++++++++++.................................. | 8 |[i/p] ..................................++++++++++++++++.............................. | 9 |UNUSED ......................................++++++++++++++++.......................... |10 |[i/p] ..........................................++++++++++++++++...................... |11 |UNUSED ..............................................++++++++++++++++.................. |12 |[i/p] ..................................................++++++++++++++++.............. |13 |UNUSED ......................................................++++++++++++++++.......... |14 |[i/p] ..........................................................++++++++++++++++...... |15 |UNUSED ................................................................++++++++++++++++ ________________________________________________________________________________ Total count of outputs placed = 7 Total count of unique Product Terms = 29 Total Product Terms to be assigned = 30 Max Product Terms used / available = 29 / 80 = 36.26 % Control Signals for Logic Block E --------------------------------- CLK pin 19 : CLK pin 22 : clk CLK pin 99 : CLK pin 102 : CLK PT : AH : PRESET : AH : RESET : AH : OE 0 : AH : OE 1 : AH : OE 2 : AH : OE 3 : AH : Logic Block E ____________________________________________ | |= >ao_to_pc_st.. | | | |= >\ibus_reade.. | | | |> not used:420 | | | |= >\ibus_reade.. | | | |= >\fi_reader:.. | 23|= id(15) | |= >\ibus_reade.. | | | |> not used:424 (\ibus_reader:timeout_0\) =| | | |= >\ibus_reade.. | | | |= >write_to_fo.. | 24|= (\ibus_reader:timeout_1\)id(16) | |= >\ibus_reade.. | | | |= >\ibus_reade.. (\ibus_reader:timeout_2\) =| | | |= >fi_to_ibus_.. | | | |= >\fi_reader:.. | 25|= (\ibus_reader:iu_readSBV_0\)id(17) | |> not used:431 | | | |> not used:432 (\ibus_reader:iu_readSBV_1\) =| | | |> not used:433 | | | |> not used:434 | 26|= (\ibus_reader:timeout_3\)id(18) | |= >id(15).Q | | | |= >\fi_reader:.. not used:957 >| | | |> not used:437 | | | |= >fi_data_15.Q | 27|= id(19) | |> not used:439 | | | |> not used:440 not used:959 >| | | |> not used:441 | | | |> not used:442 | 28|= id(20) | |> not used:443 | | | |> not used:444 not used:961 >| | | |> not used:445 | | | |> not used:446 | 29|= id(21) | |> not used:447 | | | |> not used:448 not used:963 >| | | |> not used:449 | | | |> not used:450 | 30|= id(22) | |> not used:451 | | | |> not used:452 not used:965 >| | | |> not used:453 | | | |> not used:454 | | | |> not used:455 | | | |> not used:456 | | ____________________________________________ Information: Macrocell Utilization. Description Used Max ______________________________________ | I/O Macrocells | 8 | 8 | | Buried Macrocells | 3 | 8 | | PIM Input Connects | 14 | 36 | ______________________________________ 25 / 52 = 48 % ---------------------------------------------------------------------------- PLD Compiler Software: C37KFIT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 LOGIC BLOCK F PLACEMENT (12:09:58) Messages: ________________________________________________________________________________ 1111111111222222222233333333334444444444555555555566666666667777777777 01234567890123456789012345678901234567890123456789012345678901234567890123456789 ________________________________________________________________________________ | 0 |[i/p] ++++++++++++++++................................................................ | 1 |UNUSED ......++++++++++++++++.......................................................... | 2 |[i/p] ..........++++++++++++++++...................................................... | 3 |UNUSED ..............++++++++++++++++.................................................. | 4 |[i/p] ..................++++++++++++++++.............................................. | 5 |UNUSED ......................++++++++++++++++.......................................... | 6 |[i/p] ..........................++++++++++++++++...................................... | 7 |UNUSED ..............................++++++++++++++++.................................. | 8 |[i/p] ..................................++++++++++++++++.............................. | 9 |UNUSED ......................................++++++++++++++++.......................... |10 |[i/p] ..........................................++++++++++++++++...................... |11 |UNUSED ..............................................++++++++++++++++.................. |12 |[i/p] ..................................................++++++++++++++++.............. |13 |UNUSED ......................................................++++++++++++++++.......... |14 |[i/p] ..........................................................++++++++++++++++...... |15 |UNUSED ................................................................++++++++++++++++ ________________________________________________________________________________ Total count of outputs placed = 0 Total count of unique Product Terms = 0 Total Product Terms to be assigned = 0 Max Product Terms used / available = 0 / 80 = 0.0 % Control Signals for Logic Block F --------------------------------- CLK pin 19 : CLK pin 22 : CLK pin 99 : CLK pin 102 : CLK PT : AH : PRESET : AH : RESET : AH : OE 0 : AH : OE 1 : AH : OE 2 : AH : OE 3 : AH : Logic Block F ____________________________________________ | |> not used:457 | | | |> not used:458 | | | |> not used:459 | | | |> not used:460 | | | |> not used:461 | 32|= id(23) | |> not used:462 | | | |> not used:463 not used:967 >| | | |> not used:464 | | | |> not used:465 | 33|= id(24) | |> not used:466 | | | |> not used:467 not used:969 >| | | |> not used:468 | | | |> not used:469 | 34|= id(25) | |> not used:470 | | | |> not used:471 not used:971 >| | | |> not used:472 | | | |> not used:473 | 35|= id(26) | |> not used:474 | | | |> not used:475 not used:973 >| | | |> not used:476 | | | |> not used:477 | 36|= id(27) | |> not used:478 | | | |> not used:479 not used:975 >| | | |> not used:480 | | | |> not used:481 | 37|= id(28) | |> not used:482 | | | |> not used:483 not used:977 >| | | |> not used:484 | | | |> not used:485 | 38|= id(29) | |> not used:486 | | | |> not used:487 not used:979 >| | | |> not used:488 | | | |> not used:489 | 39|= id(30) | |> not used:490 | | | |> not used:491 not used:981 >| | | |> not used:492 | | | |> not used:493 | | | |> not used:494 | | | |> not used:495 | | ____________________________________________ Information: Macrocell Utilization. Description Used Max ______________________________________ | I/O Macrocells | 8 | 8 | | Buried Macrocells | 0 | 8 | | PIM Input Connects | 0 | 36 | ______________________________________ 8 / 52 = 15 % ---------------------------------------------------------------------------- PLD Compiler Software: C37KFIT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 LOGIC BLOCK G PLACEMENT (12:09:58) Messages: ________________________________________________________________________________ 1111111111222222222233333333334444444444555555555566666666667777777777 01234567890123456789012345678901234567890123456789012345678901234567890123456789 ________________________________________________________________________________ | 0 |[i/p] ++++++++++++++++................................................................ | 1 |UNUSED ......++++++++++++++++.......................................................... | 2 |[i/p] ..........++++++++++++++++...................................................... | 3 |UNUSED ..............++++++++++++++++.................................................. | 4>|debug ..................X+++++++++++++++.............................................. | 5 |UNUSED ......................++++++++++++++++.......................................... | 6 |UNUSED ..........................++++++++++++++++...................................... | 7 |UNUSED ..............................++++++++++++++++.................................. | 8 |UNUSED ..................................++++++++++++++++.............................. | 9 |UNUSED ......................................++++++++++++++++.......................... |10 |UNUSED ..........................................++++++++++++++++...................... |11 |UNUSED ..............................................++++++++++++++++.................. |12 |UNUSED ..................................................++++++++++++++++.............. |13 |UNUSED ......................................................++++++++++++++++.......... |14 |UNUSED ..........................................................++++++++++++++++...... |15 |UNUSED ................................................................++++++++++++++++ ________________________________________________________________________________ Total count of outputs placed = 1 Total count of unique Product Terms = 1 Total Product Terms to be assigned = 1 Max Product Terms used / available = 1 / 80 = 1.26 % Control Signals for Logic Block G --------------------------------- CLK pin 19 : CLK pin 22 : CLK pin 99 : CLK pin 102 : CLK PT : AH : PRESET : AH : RESET : AH : OE 0 : AH : OE 1 : AH : OE 2 : AH : OE 3 : AH : Logic Block G ____________________________________________ | |> not used:496 | | | |> not used:497 | | | |> not used:498 | | | |> not used:499 | | | |> not used:500 | 42|= id(31) | |> not used:501 | | | |= >ao_from_pc_.. not used:983 >| | | |> not used:503 | | | |> not used:504 | 43|= reset | |> not used:505 | | | |> not used:506 not used:985 >| | | |> not used:507 | | | |> not used:508 | 44|= debug | |> not used:509 | | | |> not used:510 not used:987 >| | | |> not used:511 | | | |> not used:512 | 45|* not used | |> not used:513 | | | |> not used:514 not used:989 >| | | |> not used:515 | | | |> not used:516 | 46|* not used | |> not used:517 | | | |> not used:518 not used:991 >| | | |> not used:519 | | | |> not used:520 | 47|* not used | |> not used:521 | | | |> not used:522 not used:993 >| | | |> not used:523 | | | |> not used:524 | 48|* not used | |> not used:525 | | | |> not used:526 not used:995 >| | | |> not used:527 | | | |> not used:528 | 49|* not used | |> not used:529 | | | |> not used:530 not used:997 >| | | |> not used:531 | | | |> not used:532 | | | |> not used:533 | | | |> not used:534 | | ____________________________________________ Information: Macrocell Utilization. Description Used Max ______________________________________ | I/O Macrocells | 3 | 8 | | Buried Macrocells | 0 | 8 | | PIM Input Connects | 1 | 36 | ______________________________________ 4 / 52 = 7 % ---------------------------------------------------------------------------- PLD Compiler Software: C37KFIT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 LOGIC BLOCK H PLACEMENT (12:09:58) Messages: ________________________________________________________________________________ 1111111111222222222233333333334444444444555555555566666666667777777777 01234567890123456789012345678901234567890123456789012345678901234567890123456789 ________________________________________________________________________________ | 0 |(\fi_reader:timeout_1\) XXXXXXXXXXX+XX++................................................................ | 1 |(\fi_reader:timeout_3\) ......+++++X++XXXXXXXX.......................................................... | 2 |(data_to_fo_9) ..........++++++++++++++XX...................................................... | 3 |(\fi_reader:fi_read_stateSBV_1\) ..............++++++++XX++XXXX.................................................. | 4>|ao_from_pc_strobe ..................++++++++++++++XX.............................................. | 5 |(\fi_reader:fi_read_stateSBV_0\) ......................++++++++XX++XXXX.......................................... | 6 |(data_to_fo_8)ao_from_pc_ack ..........................++++++++++++++XX...................................... | 7 |(data_to_fo_7) ..............................++++++++++++++XX.................................. | 8 |(\fi_reader:fi_read_stateSBV_2\)ao_to_pc_strobe ..................................++++XX++XX++XXXX.............................. | 9 |(write_to_fo_req) ......................................++++++++++++XX++.......................... |10>|ao_to_pc_ack ..........................................++++++++X+++X+++...................... |11 |(data_to_fo_6) ..............................................++++++XX++++++++.................. |12 |(\fi_reader:timeout_0\) ..................................................+++++XXXXXXXXXXX.............. |13 |(data_to_fo_5) ......................................................++++++++++++++XX.......... |14 |(data_to_fo_4) ..........................................................++++++++++++++XX...... |15 |(\fi_reader:timeout_2\) ................................................................++XX++XX++XXXXXX ________________________________________________________________________________ Total count of outputs placed = 16 Total count of unique Product Terms = 80 Total Product Terms to be assigned = 81 Max Product Terms used / available = 80 / 80 = 100.0 % Control Signals for Logic Block H --------------------------------- CLK pin 19 : CLK pin 22 : clk CLK pin 99 : CLK pin 102 : CLK PT : AH : PRESET : AH : RESET : AH : OE 0 : AH : OE 1 : AH : OE 2 : AH : OE 3 : AH : Logic Block H ____________________________________________ | |= >ao_to_pc_st.. | | | |> not used:536 | | | |= >data_to_fo_.. | | | |> not used:538 | | | |= >id(20) | 51|= (\fi_reader:timeout_1\) | |= >\fi_reader:.. | | | |= >id(24) (\fi_reader:timeout_3\) =| | | |= >\ibus_reade.. | | | |= >\fi_reader:.. | 52|= (data_to_fo_9) | |= >data_to_fo_.. | | | |= >ao_from_pc_.. (\fi_reader:fi_read_stateSBV_1\) =| | | |= >id(22) | | | |= >\fi_reader:.. | 53|= ao_from_pc_strobe | |= >fi_data_12.Q | | | |= >fi_to_ibus_.. (\fi_reader:fi_read_stateSBV_0\) =| | | |> not used:550 | | | |= >\fi_reader:.. | 54|= (data_to_fo_8)ao_from_pc_ack | |= >id(23) | | | |= >data_to_fo_.. (data_to_fo_7) =| | | |> not used:554 | | | |= >fi_data_15.Q | 55|= (\fi_reader:fi_read_stateSBV_2\)ao_to_pc_strobe | |= >data_to_fo_.. | | | |= >\fi_reader:.. (write_to_fo_req) =| | | |= >id(21) | | | |> not used:559 | 56|= ao_to_pc_ack | |= >id(25) | | | |> not used:561 (data_to_fo_6) =| | | |> not used:562 | | | |> not used:563 | 57|= (\fi_reader:timeout_0\) | |= >\fi_reader:.. | | | |= >\ibus_reade.. (data_to_fo_5) =| | | |> not used:566 | | | |= >write_to_fo.. | 58|= (data_to_fo_4) | |= >\fi_reader:.. | | | |> not used:569 (\fi_reader:timeout_2\) =| | | |= >data_to_fo_.. | | | |> not used:571 | | | |= >\fi_reader:.. | | | |= >data_to_fo_.. | | ____________________________________________ Information: Macrocell Utilization. Description Used Max ______________________________________ | I/O Macrocells | 8 | 8 | | Buried Macrocells | 8 | 8 | | PIM Input Connects | 28 | 36 | ______________________________________ 44 / 52 = 84 % ---------------------------------------------------------------------------- PLD Compiler Software: C37KFIT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 LOGIC BLOCK I PLACEMENT (12:09:58) Messages: ________________________________________________________________________________ 1111111111222222222233333333334444444444555555555566666666667777777777 01234567890123456789012345678901234567890123456789012345678901234567890123456789 ________________________________________________________________________________ | 0 |[i/p] ++++++++++++++++................................................................ | 1 |UNUSED ......++++++++++++++++.......................................................... | 2 |[i/p] ..........++++++++++++++++...................................................... | 3 |UNUSED ..............++++++++++++++++.................................................. | 4 |[i/p] ..................++++++++++++++++.............................................. | 5 |UNUSED ......................++++++++++++++++.......................................... | 6 |[i/p] ..........................++++++++++++++++...................................... | 7 |UNUSED ..............................++++++++++++++++.................................. | 8 |[i/p] ..................................++++++++++++++++.............................. | 9 |UNUSED ......................................++++++++++++++++.......................... |10 |[i/p] ..........................................++++++++++++++++...................... |11 |UNUSED ..............................................++++++++++++++++.................. |12 |[i/p] ..................................................++++++++++++++++.............. |13 |UNUSED ......................................................++++++++++++++++.......... |14 |[i/p] ..........................................................++++++++++++++++...... |15 |UNUSED ................................................................++++++++++++++++ ________________________________________________________________________________ Total count of outputs placed = 0 Total count of unique Product Terms = 0 Total Product Terms to be assigned = 0 Max Product Terms used / available = 0 / 80 = 0.0 % Control Signals for Logic Block I --------------------------------- CLK pin 19 : CLK pin 22 : CLK pin 99 : CLK pin 102 : CLK PT : AH : PRESET : AH : RESET : AH : OE 0 : AH : OE 1 : AH : OE 2 : AH : OE 3 : AH : Logic Block I ____________________________________________ | |> not used:574 | | | |> not used:575 | | | |> not used:576 | | | |> not used:577 | | | |> not used:578 | 63|= fr_d(0) | |> not used:579 | | | |> not used:580 not used:1015 >| | | |> not used:581 | | | |> not used:582 | 64|= fr_d(1) | |> not used:583 | | | |> not used:584 not used:1017 >| | | |> not used:585 | | | |> not used:586 | 65|= fr_d(2) | |> not used:587 | | | |> not used:588 not used:1019 >| | | |> not used:589 | | | |> not used:590 | 66|= fr_d(3) | |> not used:591 | | | |> not used:592 not used:1021 >| | | |> not used:593 | | | |> not used:594 | 67|= fr_d(4) | |> not used:595 | | | |> not used:596 not used:1023 >| | | |> not used:597 | | | |> not used:598 | 68|= fr_d(5) | |> not used:599 | | | |> not used:600 not used:1025 >| | | |> not used:601 | | | |> not used:602 | 69|= fr_d(6) | |> not used:603 | | | |> not used:604 not used:1027 >| | | |> not used:605 | | | |> not used:606 | 70|= fr_d(7) | |> not used:607 | | | |> not used:600 not used:1029 >| | | |> not used:606 | | | |> not used:610 | | | |> not used:611 | | | |> not used:612 | | ____________________________________________ Information: Macrocell Utilization. Description Used Max ______________________________________ | I/O Macrocells | 8 | 8 | | Buried Macrocells | 0 | 8 | | PIM Input Connects | 0 | 36 | ______________________________________ 8 / 52 = 15 % ---------------------------------------------------------------------------- PLD Compiler Software: C37KFIT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 LOGIC BLOCK J PLACEMENT (12:09:58) Messages: ________________________________________________________________________________ 1111111111222222222233333333334444444444555555555566666666667777777777 01234567890123456789012345678901234567890123456789012345678901234567890123456789 ________________________________________________________________________________ | 0 |[i/p] ++++++++++++++++................................................................ | 1 |UNUSED ......++++++++++++++++.......................................................... | 2 |UNUSED ..........++++++++++++++++...................................................... | 3 |UNUSED ..............++++++++++++++++.................................................. | 4 |UNUSED ..................++++++++++++++++.............................................. | 5 |UNUSED ......................++++++++++++++++.......................................... | 6 |UNUSED ..........................++++++++++++++++...................................... | 7 |UNUSED ..............................++++++++++++++++.................................. | 8 |UNUSED ..................................++++++++++++++++.............................. | 9 |UNUSED ......................................++++++++++++++++.......................... |10>|fr_ref_clk ..........................................X+++++++++++++++...................... |11 |UNUSED ..............................................++++++++++++++++.................. |12 |UNUSED ..................................................++++++++++++++++.............. |13 |UNUSED ......................................................++++++++++++++++.......... |14 |UNUSED ..........................................................++++++++++++++++...... |15 |UNUSED ................................................................++++++++++++++++ ________________________________________________________________________________ Total count of outputs placed = 1 Total count of unique Product Terms = 1 Total Product Terms to be assigned = 1 Max Product Terms used / available = 1 / 80 = 1.26 % Control Signals for Logic Block J --------------------------------- CLK pin 19 : CLK pin 22 : CLK pin 99 : CLK pin 102 : CLK PT : AH : PRESET : AH : RESET : AH : OE 0 : AH : OE 1 : AH : OE 2 : AH : OE 3 : AH : Logic Block J ____________________________________________ | |> not used:613 | | | |> not used:614 | | | |= >fo_ckw.Q | | | |> not used:616 | | | |> not used:617 | 72|= fr_d(8) | |> not used:618 | | | |> not used:619 not used:1031 >| | | |> not used:620 | | | |> not used:621 | 73|* not used | |> not used:622 | | | |> not used:623 not used:1033 >| | | |> not used:624 | | | |> not used:625 | 74|* not used | |> not used:626 | | | |> not used:627 not used:1035 >| | | |> not used:628 | | | |> not used:629 | 75|* not used | |> not used:630 | | | |> not used:631 not used:1037 >| | | |> not used:632 | | | |> not used:633 | 76|* not used | |> not used:634 | | | |> not used:635 not used:1039 >| | | |> not used:636 | | | |> not used:637 | 77|= fr_ref_clk | |> not used:638 | | | |> not used:639 not used:1041 >| | | |> not used:640 | | | |> not used:641 | 78|* not used | |> not used:642 | | | |> not used:643 not used:1043 >| | | |> not used:644 | | | |> not used:645 | 79|* not used | |> not used:646 | | | |> not used:647 not used:1045 >| | | |> not used:648 | | | |> not used:649 | | | |> not used:650 | | | |> not used:651 | | ____________________________________________ Information: Macrocell Utilization. Description Used Max ______________________________________ | I/O Macrocells | 2 | 8 | | Buried Macrocells | 0 | 8 | | PIM Input Connects | 1 | 36 | ______________________________________ 3 / 52 = 5 % ---------------------------------------------------------------------------- PLD Compiler Software: C37KFIT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 LOGIC BLOCK K PLACEMENT (12:09:58) Messages: ________________________________________________________________________________ 1111111111222222222233333333334444444444555555555566666666667777777777 01234567890123456789012345678901234567890123456789012345678901234567890123456789 ________________________________________________________________________________ | 0>|fr_rf ++X+++++++++++++................................................................ | 1 |(fi_data_7) ......XX++++++++++++++.......................................................... | 2>|fr_mode ..........X+++++++++++++++...................................................... | 3 |(fi_data_0) ..............XX++++++++++++++.................................................. | 4 |(fi_data_1)fr_status ..................XX++++++++++++++.............................................. | 5 |(fi_data_11) ......................XX++++++++++++++.......................................... | 6 |(fi_data_12) ..........................XX++++++++++++++...................................... | 7 |(fi_data_13) ..............................XX++++++++++++++.................................. | 8 |(fi_data_14) ..................................XX++++++++++++++.............................. | 9 |(fi_data_2) ......................................XX++++++++++++++.......................... |10 |(fi_data_3) ..........................................XX++++++++++++++...................... |11 |(fi_data_4) ..............................................XX++++++++++++++.................. |12 |(fi_data_5) ..................................................XX++++++++++++++.............. |13 |(fi_data_6) ......................................................XX++++++++++++++.......... |14 |(refill_ibus_output_buf) ..........................................................XX++++++++++++++...... |15 |(fi_to_ibus_req) ................................................................++X+++++++++++++ ________________________________________________________________________________ Total count of outputs placed = 16 Total count of unique Product Terms = 29 Total Product Terms to be assigned = 29 Max Product Terms used / available = 29 / 80 = 36.26 % Control Signals for Logic Block K --------------------------------- CLK pin 19 : CLK pin 22 : clk CLK pin 99 : CLK pin 102 : CLK PT : AH : PRESET : AH : GND RESET : AH : reset OE 0 : AH : OE 1 : AH : OE 2 : AH : OE 3 : AH : Logic Block K ____________________________________________ | |= >fiber_to_ib.. | | | |= >fiber_to_ib.. | | | |= >fi_data_3.Q | | | |= >fiber_to_ib.. | | | |= >\ibus_fi:re.. | 82|= fr_rf | |= >fiber_to_ib.. | | | |= >fi_data_1.Q (fi_data_7) =| | | |= >fiber_to_ib.. | | | |= >reset | 83|= fr_mode | |= >fiber_to_ib.. | | | |> not used:662 (fi_data_0) =| | | |= >fi_to_ibus_.. | | | |= >fiber_to_ib.. | 84|= (fi_data_1)fr_status | |= >fi_data_12.Q | | | |> not used:666 (fi_data_11) =| | | |= >fi_data_13.Q | | | |= >fi_data_14.Q | 85|= (fi_data_12) | |= >fiber_to_ib.. | | | |> not used:670 (fi_data_13) =| | | |> not used:671 | | | |= >fi_data_4.Q | 86|= (fi_data_14) | |= >fi_data_5.Q | | | |= >\ibus_fi:re.. (fi_data_2) =| | | |= >fi_data_6.Q | | | |= >data_pump_w.. | 87|= (fi_data_3) | |= >fi_data_11.Q | | | |= >fiber_to_ib.. (fi_data_4) =| | | |= >fiber_to_ib.. | | | |> not used:680 | 88|= (fi_data_5) | |> not used:681 | | | |> not used:682 (fi_data_6) =| | | |> not used:683 | | | |= >fiber_to_ib.. | 89|= (refill_ibus_output_buf) | |= >fi_data_2.Q | | | |= >fi_data_7.Q (fi_to_ibus_req) =| | | |> not used:687 | | | |> not used:688 | | | |= >fiber_to_ib.. | | | |= >fi_data_0.Q | | ____________________________________________ Information: Macrocell Utilization. Description Used Max ______________________________________ | I/O Macrocells | 8 | 8 | | Buried Macrocells | 8 | 8 | | PIM Input Connects | 29 | 36 | ______________________________________ 45 / 52 = 86 % ---------------------------------------------------------------------------- PLD Compiler Software: C37KFIT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 LOGIC BLOCK L PLACEMENT (12:09:58) Messages: ________________________________________________________________________________ 1111111111222222222233333333334444444444555555555566666666667777777777 01234567890123456789012345678901234567890123456789012345678901234567890123456789 ________________________________________________________________________________ | 0 |UNUSED ++++++++++++++++................................................................ | 1 |UNUSED ......++++++++++++++++.......................................................... | 2 |UNUSED ..........++++++++++++++++...................................................... | 3 |UNUSED ..............++++++++++++++++.................................................. | 4 |UNUSED ..................++++++++++++++++.............................................. | 5 |UNUSED ......................++++++++++++++++.......................................... | 6 |UNUSED ..........................++++++++++++++++...................................... | 7 |UNUSED ..............................++++++++++++++++.................................. | 8 |UNUSED ..................................++++++++++++++++.............................. | 9 |UNUSED ......................................++++++++++++++++.......................... |10 |UNUSED ..........................................++++++++++++++++...................... |11 |UNUSED ..............................................++++++++++++++++.................. |12 |UNUSED ..................................................++++++++++++++++.............. |13 |UNUSED ......................................................++++++++++++++++.......... |14 |UNUSED ..........................................................++++++++++++++++...... |15 |UNUSED ................................................................++++++++++++++++ ________________________________________________________________________________ Total count of outputs placed = 0 Total count of unique Product Terms = 0 Total Product Terms to be assigned = 0 Max Product Terms used / available = 0 / 80 = 0.0 % Control Signals for Logic Block L --------------------------------- CLK pin 19 : CLK pin 22 : CLK pin 99 : CLK pin 102 : CLK PT : AH : PRESET : AH : RESET : AH : OE 0 : AH : OE 1 : AH : OE 2 : AH : OE 3 : AH : Logic Block L ____________________________________________ | |> not used:691 | | | |> not used:692 | | | |> not used:693 | | | |> not used:694 | | | |> not used:695 | 91|* not used | |> not used:696 | | | |> not used:697 not used:1063 >| | | |> not used:698 | | | |> not used:699 | 92|* not used | |> not used:700 | | | |> not used:701 not used:1065 >| | | |> not used:702 | | | |> not used:703 | 93|* not used | |> not used:704 | | | |> not used:705 not used:1067 >| | | |> not used:706 | | | |> not used:707 | 94|* not used | |> not used:708 | | | |> not used:709 not used:1069 >| | | |> not used:710 | | | |> not used:711 | 95|* not used | |> not used:712 | | | |> not used:713 not used:1071 >| | | |> not used:714 | | | |> not used:715 | 96|* not used | |> not used:716 | | | |> not used:717 not used:1073 >| | | |> not used:718 | | | |> not used:719 | 97|* not used | |> not used:720 | | | |> not used:721 not used:1075 >| | | |> not used:722 | | | |> not used:723 | 98|* not used | |> not used:724 | | | |> not used:725 not used:1077 >| | | |> not used:726 | | | |> not used:727 | | | |> not used:728 | | | |> not used:729 | | ____________________________________________ Information: Macrocell Utilization. Description Used Max ______________________________________ | I/O Macrocells | 0 | 8 | | Buried Macrocells | 0 | 8 | | PIM Input Connects | 0 | 36 | ______________________________________ 0 / 52 = 0 % ---------------------------------------------------------------------------- PLD Compiler Software: C37KFIT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 LOGIC BLOCK M PLACEMENT (12:09:58) Messages: ________________________________________________________________________________ 1111111111222222222233333333334444444444555555555566666666667777777777 01234567890123456789012345678901234567890123456789012345678901234567890123456789 ________________________________________________________________________________ | 0>|fo_d(0) XXXX++++++++++++................................................................ | 1 |UNUSED ......++++++++++++++++.......................................................... | 2>|fo_d(1) ..........XXXX++++++++++++...................................................... | 3 |(\ibus_fo:stateSBV_2\) ..............XXX+++++++++++++.................................................. | 4>|fo_d(2) ..................XXXX++++++++++++.............................................. | 5 |(data_to_fo_15) ......................XX++++++++++++++.......................................... | 6>|fo_d(3) ..........................XXXX++++++++++++...................................... | 7 |(data_to_fo_2) ..............................XX++++++++++++++.................................. | 8>|fo_d(4) ..................................XXXX++++++++++++.............................. | 9 |(data_to_fo_3) ......................................XX++++++++++++++.......................... |10>|fo_d(5) ..........................................XXXX++++++++++++...................... |11 |(write_to_fo_ack) ..............................................XX++++++++++++++.................. |12>|fo_d(6) ..................................................XXXX++++++++++++.............. |13 |(\ibus_fo:stateSBV_0\) ......................................................X+++++++++++++++.......... |14>|fo_d(7) ..........................................................XXXX++++++++++++...... |15 |UNUSED ................................................................++++++++++++++++ ________________________________________________________________________________ Total count of outputs placed = 14 Total count of unique Product Terms = 44 Total Product Terms to be assigned = 44 Max Product Terms used / available = 44 / 80 = 55.1 % Control Signals for Logic Block M --------------------------------- CLK pin 19 : CLK pin 22 : clk CLK pin 99 : CLK pin 102 : CLK PT : AH : PRESET : AH : RESET : AH : OE 0 : AH : OE 1 : AH : OE 2 : AH : OE 3 : AH : Logic Block M ____________________________________________ | |= >fo_d(3).Q | | | |= >data_to_fo_.. | | | |= >fo_d(0).Q | | | |= >fo_d(4).Q | | | |= >id(31) |103|= fo_d(0) | |= >data_to_fo_.. | | | |= >fo_d(1).Q not used:1079 >| | | |= >\ibus_reade.. | | | |= >\ibus_fo:st.. |104|= fo_d(1) | |= >data_to_fo_.. | | | |= >fo_d(2).Q (\ibus_fo:stateSBV_2\) =| | | |= >data_to_fo_.. | | | |= >data_to_fo_.. |105|= fo_d(2) | |= >data_to_fo_.. | | | |= >data_to_fo_.. (data_to_fo_15) =| | | |= >id(18) | | | |= >data_to_fo_.. |106|= fo_d(3) | |= >data_to_fo_.. | | | |= >fo_d(5).Q (data_to_fo_2) =| | | |= >data_to_fo_.. | | | |= >\ibus_fo:st.. |107|= fo_d(4) | |= >fo_d(6).Q | | | |= >ao_to_pc_st.. (data_to_fo_3) =| | | |= >write_to_fo.. | | | |= >fo_d(7).Q |108|= fo_d(5) | |= >data_to_fo_.. | | | |> not used:756 (write_to_fo_ack) =| | | |= >data_to_fo_.. | | | |= >data_to_fo_.. |109|= fo_d(6) | |= >data_to_fo_.. | | | |= >\ibus_reade.. (\ibus_fo:stateSBV_0\) =| | | |= >data_to_fo_.. | | | |= >write_to_fo.. |110|= fo_d(7) | |= >id(19) | | | |> not used:764 not used:1093 >| | | |= >\ibus_fo:st.. | | | |= >fr_ref_clk... | | | |= >data_to_fo_.. | | | |> not used:768 | | ____________________________________________ Information: Macrocell Utilization. Description Used Max ______________________________________ | I/O Macrocells | 8 | 8 | | Buried Macrocells | 6 | 8 | | PIM Input Connects | 36 | 36 | ______________________________________ 50 / 52 = 96 % ---------------------------------------------------------------------------- PLD Compiler Software: C37KFIT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 LOGIC BLOCK N PLACEMENT (12:09:58) Messages: ________________________________________________________________________________ 1111111111222222222233333333334444444444555555555566666666667777777777 01234567890123456789012345678901234567890123456789012345678901234567890123456789 ________________________________________________________________________________ | 0>|fo_d(8) ++X+++++++++++++................................................................ | 1 |UNUSED ......++++++++++++++++.......................................................... | 2>|fo_d(9) ..........X+++++++++++++++...................................................... | 3 |UNUSED ..............++++++++++++++++.................................................. | 4 |UNUSED ..................++++++++++++++++.............................................. | 5 |UNUSED ......................++++++++++++++++.......................................... | 6 |UNUSED ..........................++++++++++++++++...................................... | 7 |UNUSED ..............................++++++++++++++++.................................. | 8 |UNUSED ..................................++++++++++++++++.............................. | 9 |UNUSED ......................................++++++++++++++++.......................... |10>|fo_enn_l ..........................................X+++++++++++++++...................... |11 |(\ibus_fo:stateSBV_1\) ..............................................XX++++++++++++++.................. |12>|fo_ena_l ..................................................XX++++++++++++++.............. |13 |UNUSED ......................................................++++++++++++++++.......... |14>|fo_ckw ..........................................................X+++++++++++++++...... |15 |UNUSED ................................................................++++++++++++++++ ________________________________________________________________________________ Total count of outputs placed = 6 Total count of unique Product Terms = 8 Total Product Terms to be assigned = 8 Max Product Terms used / available = 8 / 80 = 10.1 % Control Signals for Logic Block N --------------------------------- CLK pin 19 : CLK pin 22 : clk CLK pin 99 : CLK pin 102 : CLK PT : AH : PRESET : AH : RESET : AH : OE 0 : AH : OE 1 : AH : OE 2 : AH : OE 3 : AH : Logic Block N ____________________________________________ | |= >fr_ref_clk... | | | |> not used:770 | | | |= >fo_ckw.Q | | | |> not used:772 | | | |= >fo_d(8).Q |112|= fo_d(8) | |> not used:774 | | | |> not used:775 not used:1095 >| | | |> not used:776 | | | |= >fo_d(9).Q |113|= fo_d(9) | |> not used:778 | | | |= >\ibus_fo:st.. not used:1097 >| | | |= >fo_ena_l.Q | | | |> not used:781 |114|* not used | |> not used:782 | | | |> not used:783 not used:1099 >| | | |> not used:784 | | | |> not used:785 |115|* not used | |> not used:786 | | | |> not used:787 not used:1101 >| | | |> not used:788 | | | |> not used:789 |116|* not used | |= >\ibus_fo:st.. | | | |> not used:791 not used:1103 >| | | |= >\ibus_fo:st.. | | | |> not used:793 |117|= fo_enn_l | |> not used:794 | | | |> not used:795 (\ibus_fo:stateSBV_1\) =| | | |> not used:796 | | | |> not used:797 |118|= fo_ena_l | |> not used:798 | | | |> not used:799 not used:1107 >| | | |> not used:800 | | | |> not used:801 |119|= fo_ckw | |> not used:802 | | | |> not used:803 not used:1109 >| | | |> not used:804 | | | |> not used:805 | | | |> not used:806 | | | |> not used:807 | | ____________________________________________ Information: Macrocell Utilization. Description Used Max ______________________________________ | I/O Macrocells | 5 | 8 | | Buried Macrocells | 1 | 8 | | PIM Input Connects | 8 | 36 | ______________________________________ 14 / 52 = 26 % ---------------------------------------------------------------------------- PLD Compiler Software: C37KFIT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 LOGIC BLOCK O PLACEMENT (12:09:58) Messages: ________________________________________________________________________________ 1111111111222222222233333333334444444444555555555566666666667777777777 01234567890123456789012345678901234567890123456789012345678901234567890123456789 ________________________________________________________________________________ | 0>|fo_mode ++++++++++X+++++................................................................ | 1 |UNUSED ......++++++++++++++++.......................................................... | 2>|fo_foto ..........X+++++++++++++++...................................................... | 3 |UNUSED ..............++++++++++++++++.................................................. | 4 |UNUSED ..................++++++++++++++++.............................................. | 5 |UNUSED ......................++++++++++++++++.......................................... | 6 |UNUSED ..........................++++++++++++++++...................................... | 7 |UNUSED ..............................++++++++++++++++.................................. | 8 |UNUSED ..................................++++++++++++++++.............................. | 9 |(\fr_imp:fr_stateSBV_0\) ......................................++++X+++++++++++.......................... |10>|fifo_reset_l ..........................................XX++++++++++++++...................... |11 |UNUSED ..............................................++++++++++++++++.................. |12>|fifo_write_l ..................................................XX++++++++++++++.............. |13 |UNUSED ......................................................++++++++++++++++.......... |14>|fifo_d(8) ..........................................................XX++++++++++++++...... |15 |UNUSED ................................................................++++++++++++++++ ________________________________________________________________________________ Total count of outputs placed = 6 Total count of unique Product Terms = 7 Total Product Terms to be assigned = 9 Max Product Terms used / available = 7 / 80 = 8.76 % Control Signals for Logic Block O --------------------------------- CLK pin 19 : CLK pin 22 : clk CLK pin 99 : CLK pin 102 : CLK PT : AH : PRESET : AH : reset_fifo.Q RESET : AH : GND OE 0 : AH : OE 1 : AH : OE 2 : AH : OE 3 : AH : Logic Block O ____________________________________________ | |= >fifo_write_.. | | | |> not used:809 | | | |> not used:810 | | | |> not used:811 | | | |= >fifo_d(8).Q |122|= fo_mode | |> not used:813 | | | |> not used:814 not used:1111 >| | | |= >fr_status | | | |= >fr_rdy_l |123|= fo_foto | |= >\fr_imp:fr_.. | | | |= >fifo_reset_.. not used:1113 >| | | |> not used:819 | | | |> not used:820 |124|* not used | |> not used:821 | | | |> not used:822 not used:1115 >| | | |= >reset_fifo.Q | | | |> not used:824 |125|* not used | |= >fr_d(8) | | | |> not used:826 not used:1117 >| | | |> not used:827 | | | |> not used:828 |126|* not used | |> not used:829 | | | |> not used:830 (\fr_imp:fr_stateSBV_0\) =| | | |> not used:831 | | | |> not used:832 |127|= fifo_reset_l | |> not used:833 | | | |> not used:834 not used:1121 >| | | |> not used:835 | | | |> not used:836 |128|= fifo_write_l | |> not used:837 | | | |> not used:838 not used:1123 >| | | |> not used:839 | | | |> not used:840 |129|= fifo_d(8) | |> not used:841 | | | |> not used:842 not used:1125 >| | | |> not used:843 | | | |> not used:844 | | | |> not used:845 | | | |> not used:846 | | ____________________________________________ Information: Macrocell Utilization. Description Used Max ______________________________________ | I/O Macrocells | 5 | 8 | | Buried Macrocells | 1 | 8 | | PIM Input Connects | 8 | 36 | ______________________________________ 14 / 52 = 26 % ---------------------------------------------------------------------------- PLD Compiler Software: C37KFIT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 LOGIC BLOCK P PLACEMENT (12:09:58) Messages: ________________________________________________________________________________ 1111111111222222222233333333334444444444555555555566666666667777777777 01234567890123456789012345678901234567890123456789012345678901234567890123456789 ________________________________________________________________________________ | 0>|fifo_d(0) XX++++++++++++++................................................................ | 1 |UNUSED ......++++++++++++++++.......................................................... | 2>|fifo_d(1) ..........XX++++++++++++++...................................................... | 3 |UNUSED ..............++++++++++++++++.................................................. | 4>|fifo_d(2) ..................XX++++++++++++++.............................................. | 5 |UNUSED ......................++++++++++++++++.......................................... | 6>|fifo_d(3) ..........................XX++++++++++++++...................................... | 7 |UNUSED ..............................++++++++++++++++.................................. | 8>|fifo_d(4) ..................................XX++++++++++++++.............................. | 9 |UNUSED ......................................++++++++++++++++.......................... |10>|fifo_d(5) ..........................................XX++++++++++++++...................... |11 |UNUSED ..............................................++++++++++++++++.................. |12>|fifo_d(6) ..................................................XX++++++++++++++.............. |13 |UNUSED ......................................................++++++++++++++++.......... |14>|fifo_d(7) ..........................................................XX++++++++++++++...... |15 |UNUSED ................................................................++++++++++++++++ ________________________________________________________________________________ Total count of outputs placed = 8 Total count of unique Product Terms = 16 Total Product Terms to be assigned = 16 Max Product Terms used / available = 16 / 80 = 20.1 % Control Signals for Logic Block P --------------------------------- CLK pin 19 : CLK pin 22 : clk CLK pin 99 : CLK pin 102 : CLK PT : AH : PRESET : AH : RESET : AH : OE 0 : AH : OE 1 : AH : OE 2 : AH : OE 3 : AH : Logic Block P ____________________________________________ | |> not used:847 | | | |> not used:848 | | | |= >fifo_d(1).Q | | | |= >fr_d(2) | | | |= >reset_fifo.Q |131|= fifo_d(0) | |= >fifo_d(6).Q | | | |= >fr_d(0) not used:1127 >| | | |= >fr_status | | | |= >fr_rdy_l |132|= fifo_d(1) | |= >fifo_d(3).Q | | | |= >fifo_d(0).Q not used:1129 >| | | |> not used:858 | | | |= >fifo_d(4).Q |133|= fifo_d(2) | |= >fr_d(7) | | | |= >fr_d(3) not used:1131 >| | | |> not used:862 | | | |> not used:863 |134|= fifo_d(3) | |= >fr_d(4) | | | |> not used:865 not used:1133 >| | | |> not used:866 | | | |= >fifo_d(5).Q |135|= fifo_d(4) | |= >fr_d(1) | | | |= >fr_d(6) not used:1135 >| | | |> not used:870 | | | |> not used:871 |136|= fifo_d(5) | |= >fifo_d(2).Q | | | |> not used:873 not used:1137 >| | | |> not used:874 | | | |= >fr_d(5) |137|= fifo_d(6) | |> not used:876 | | | |> not used:877 not used:1139 >| | | |> not used:878 | | | |= >fifo_d(7).Q |138|= fifo_d(7) | |> not used:880 | | | |> not used:881 not used:1141 >| | | |> not used:882 | | | |> not used:883 | | | |> not used:884 | | | |= >\fr_imp:fr_.. | | ____________________________________________ Information: Macrocell Utilization. Description Used Max ______________________________________ | I/O Macrocells | 8 | 8 | | Buried Macrocells | 0 | 8 | | PIM Input Connects | 20 | 36 | ______________________________________ 28 / 52 = 53 % ---------------------------------------------------------------------------- PLD Compiler Software: C37KFIT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 PINOUT INFORMATION (12:09:58) Device: cy37256p160 Package: cy37256p160-125ac 1 : GND > 2 : id(0) > 3 : id(1) > 4 : id(2) > 5 : id(3) 6 : (data_to_fo_13) > 7 : id(4) > 8 : id(5) > 9 : id(6) 10 : GND > 11 : id(7) > 12 : id(8) > 13 : id(9) > 14 : id(10) > 15 : id(11) > 16 : id(12) > 17 : id(13) > 18 : id(14) 19 : Not Used 20 : VCC 21 : GND > 22 : clk > 23 : id(15) > 24 : (\ibus_reader:timeout_1\)id(16) > 25 : (\ibus_reader:iu_readSBV_0\)id(17) > 26 : (\ibus_reader:timeout_3\)id(18) > 27 : id(19) > 28 : id(20) > 29 : id(21) > 30 : id(22) 31 : GND > 32 : id(23) > 33 : id(24) > 34 : id(25) > 35 : id(26) > 36 : id(27) > 37 : id(28) > 38 : id(29) > 39 : id(30) 40 : VCC 41 : GND > 42 : id(31) > 43 : reset > 44 : debug 45 : Not Used 46 : Not Used 47 : Not Used 48 : Not Used 49 : Not Used 50 : GND 51 : (\fi_reader:timeout_1\) 52 : (data_to_fo_9) > 53 : ao_from_pc_strobe > 54 : (data_to_fo_8)ao_from_pc_ack > 55 : (\fi_reader:fi_read_stateSBV_2\)ao_to_pc_strobe > 56 : ao_to_pc_ack 57 : (\fi_reader:timeout_0\) 58 : (data_to_fo_4) 59 : Not Used 60 : VCC 61 : GND 62 : VCC > 63 : fr_d(0) > 64 : fr_d(1) > 65 : fr_d(2) > 66 : fr_d(3) > 67 : fr_d(4) > 68 : fr_d(5) > 69 : fr_d(6) > 70 : fr_d(7) 71 : GND > 72 : fr_d(8) 73 : Not Used 74 : Not Used 75 : Not Used 76 : Not Used > 77 : fr_ref_clk 78 : Not Used 79 : Not Used 80 : VCC 81 : GND > 82 : fr_rf > 83 : fr_mode > 84 : (fi_data_1)fr_status 85 : (fi_data_12) 86 : (fi_data_14) 87 : (fi_data_3) 88 : (fi_data_5) 89 : (refill_ibus_output_buf) 90 : GND 91 : Not Used 92 : Not Used 93 : Not Used 94 : Not Used 95 : Not Used 96 : Not Used 97 : Not Used 98 : Not Used > 99 : fr_rdy_l 100 : VCC 101 : GND 102 : Not Used > 103 : fo_d(0) > 104 : fo_d(1) > 105 : fo_d(2) > 106 : fo_d(3) > 107 : fo_d(4) > 108 : fo_d(5) > 109 : fo_d(6) > 110 : fo_d(7) 111 : GND > 112 : fo_d(8) > 113 : fo_d(9) 114 : Not Used 115 : Not Used 116 : Not Used > 117 : fo_enn_l > 118 : fo_ena_l > 119 : fo_ckw 120 : VCC 121 : GND > 122 : fo_mode > 123 : fo_foto 124 : Not Used 125 : Not Used 126 : Not Used > 127 : fifo_reset_l > 128 : fifo_write_l > 129 : fifo_d(8) 130 : GND > 131 : fifo_d(0) > 132 : fifo_d(1) > 133 : fifo_d(2) > 134 : fifo_d(3) > 135 : fifo_d(4) > 136 : fifo_d(5) > 137 : fifo_d(6) > 138 : fifo_d(7) 139 : Not Used 140 : VCC 141 : GND 142 : VCC 143 : (fiber_to_ibus_buf_9) 144 : (fiber_to_ibus_buf_0) 145 : (data_pump_word_ready) > 146 : fifo_read_l 147 : (\pump:count_0\) 148 : (fi_data_15) > 149 : (fi_data_9)fifo_empty_l > 150 : (fiber_to_ibus_buf_8)fifo_out(8) 151 : GND > 152 : (fiber_to_ibus_buf_6)fifo_out(0) > 153 : fifo_out(1) > 154 : (fiber_to_ibus_buf_14)fifo_out(2) > 155 : (fiber_to_ibus_buf_10)fifo_out(3) > 156 : (fiber_to_ibus_buf_11)fifo_out(4) > 157 : (fiber_to_ibus_buf_15)fifo_out(5) > 158 : fifo_out(6) > 159 : fifo_out(7) 160 : VCC ---------------------------------------------------------------------------- PLD Compiler Software: C37KFIT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 RESOURCE UTILIZATION (12:09:58) Information: Macrocell Utilization. Description Used Max ______________________________________ | Dedicated Inputs | 0 | 1 | | Clock/Inputs | 2 | 4 | | I/O Macrocells | 103 | 128 | | Buried Macrocells | 55 | 128 | | PIM Input Connects | 261 | 624 | ______________________________________ 421 / 885 = 47 % Required Max (Available) CLOCK/LATCH ENABLE signals 1 20 Input REG/LATCH signals 0 133 Input PIN signals 2 5 Input PINs using I/O cells 26 26 Output PIN signals 77 102 Total PIN signals 105 133 Macrocells Used 132 256 Unique Product Terms 342 1280 ---------------------------------------------------------------------------- PLD Compiler Software: C37KFIT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 PRESET/RESET AND OUTPUT ENABLE COMBINATIONS PRESET: GND RESET : reset CLOCK PT : NULL Used by Logic Blocks: AK Total unique inputs = 15 count of output equations = 3 ==>OE: GND or VCC count of OE equations = 3 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 161 count of output equations = 120 ==>OE: GND or VCC count of OE equations = 120 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 2 count of output equations = 7 ==>OE: GND or VCC count of OE equations = 7 PRESET: reset_fifo.Q RESET : GND CLOCK PT : NULL Used by Logic Blocks: O Total unique inputs = 6 count of output equations = 2 ==>OE: GND or VCC count of OE equations = 2 ---------------------------------------------------------------------------- PLD Compiler Software: C37KFIT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 JEDEC ASSEMBLE (12:09:58) Messages: Information: Processing JEDEC for Logic Block 1. Information: Processing JEDEC for Logic Block 2. Information: Processing JEDEC for Logic Block 3. Information: Processing JEDEC for Logic Block 4. Information: Processing JEDEC for Logic Block 5. Information: Processing JEDEC for Logic Block 6. Information: Processing JEDEC for Logic Block 7. Information: Processing JEDEC for Logic Block 8. Information: Processing JEDEC for Logic Block 9. Information: Processing JEDEC for Logic Block 10. Information: Processing JEDEC for Logic Block 11. Information: Processing JEDEC for Logic Block 12. Information: Processing JEDEC for Logic Block 13. Information: Processing JEDEC for Logic Block 14. Information: Processing JEDEC for Logic Block 15. Information: Processing JEDEC for Logic Block 16. Information: JEDEC output file 'pc_remote_fiber.pin' created. Information: JEDEC output file 'pc_remote_fiber.jed' created. Summary: Error Count = 0 Warning Count = 0 Completed Successfully at 12:09:59 ---------------------------------------------------------------------------- PLD Compiler Software: C37KFIT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 TIMING PATH ANALYSIS (12:09:59) using Package: cy37256p160-125ac Messages: ---------------------------------------------------------------------------- Signal Name | Delay Type | tmax | Path Description ---------------------------------------------------------------------------- reg::id(0)[2] inp::\fi_reader:fi_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::id(0) tCO 6.5 ns ---------------------------------------------------------------------------- reg::id(1)[3] inp::\fi_reader:fi_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::id(1) tCO 6.5 ns ---------------------------------------------------------------------------- reg::id(2)[4] inp::\fi_reader:fi_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::id(2) tCO 6.5 ns ---------------------------------------------------------------------------- reg::id(3)[5] inp::\fi_reader:fi_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::id(3) tCO 6.5 ns ---------------------------------------------------------------------------- reg::(data_to_fo_13)[6] inp::ao_to_pc_strobe ---->ao_to_pc_strobe tS 4.0 ns 1 pass inp::\ibus_reader:iu_readSBV_0\.Q tSCS 8.0 ns 1 pass out::data_to_fo_13 tCO 6.5 ns ---------------------------------------------------------------------------- reg::id(4)[7] inp::\fi_reader:fi_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::id(4) tCO 6.5 ns ---------------------------------------------------------------------------- reg::id(5)[8] inp::\fi_reader:fi_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::id(5) tCO 6.5 ns ---------------------------------------------------------------------------- reg::id(6)[9] inp::\fi_reader:fi_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::id(6) tCO 6.5 ns ---------------------------------------------------------------------------- reg::id(7)[11] inp::\fi_reader:fi_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::id(7) tCO 6.5 ns ---------------------------------------------------------------------------- reg::id(8)[12] inp::\fi_reader:fi_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::id(8) tCO 6.5 ns ---------------------------------------------------------------------------- reg::id(9)[13] inp::\fi_reader:fi_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::id(9) tCO 6.5 ns ---------------------------------------------------------------------------- reg::id(10)[14] inp::\fi_reader:fi_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::id(10) tCO 6.5 ns ---------------------------------------------------------------------------- reg::id(11)[15] inp::\fi_reader:fi_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::id(11) tCO 6.5 ns ---------------------------------------------------------------------------- reg::id(12)[16] inp::\fi_reader:fi_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::id(12) tCO 6.5 ns ---------------------------------------------------------------------------- reg::id(13)[17] inp::\fi_reader:fi_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::id(13) tCO 6.5 ns ---------------------------------------------------------------------------- reg::id(14)[18] inp::\fi_reader:fi_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::id(14) tCO 6.5 ns ---------------------------------------------------------------------------- reg::id(15)[23] inp::\fi_reader:fi_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::id(15) tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\ibus_reader:timeout_1\)id(16)[24] inp::ao_to_pc_strobe ---->ao_to_pc_strobe tS 4.0 ns 1 pass inp::\ibus_reader:iu_readSBV_0\.Q tSCS 8.0 ns 1 pass out::\ibus_reader:timeout_1\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\ibus_reader:iu_readSBV_0\)id(17)[25] inp::ao_to_pc_strobe ---->ao_to_pc_strobe tS 4.0 ns 1 pass inp::\ibus_reader:iu_readSBV_0\.Q tSCS 8.0 ns 1 pass out::\ibus_reader:iu_readSBV_0\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\ibus_reader:timeout_3\)id(18)[26] inp::ao_to_pc_strobe ---->ao_to_pc_strobe tS 4.0 ns 1 pass inp::\ibus_reader:iu_readSBV_0\.Q tSCS 8.0 ns 1 pass out::\ibus_reader:timeout_3\ tCO 6.5 ns ---------------------------------------------------------------------------- cmb::debug[44] inp::ao_from_pc_strobe.Q tCO 12.5 ns 1 pass ---------------------------------------------------------------------------- reg::(\fi_reader:timeout_1\)[51] inp::ao_from_pc_ack ---->ao_from_pc_ack tS 4.0 ns 1 pass inp::\fi_reader:fi_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::\fi_reader:timeout_1\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::(data_to_fo_9)[52] inp::ao_to_pc_strobe ---->ao_to_pc_strobe tS 4.0 ns 1 pass inp::\ibus_reader:iu_readSBV_0\.Q tSCS 8.0 ns 1 pass out::data_to_fo_9 tCO 6.5 ns ---------------------------------------------------------------------------- reg::ao_from_pc_strobe[53] inp::ao_from_pc_ack ---->ao_from_pc_ack tS 4.0 ns 1 pass inp::\fi_reader:fi_read_stateSBV_1\.Q tSCS 8.0 ns 1 pass out::debug tCO 12.5 ns 1 pass ---------------------------------------------------------------------------- reg::(data_to_fo_8)ao_from_pc_ack[54] inp::ao_to_pc_strobe ---->ao_to_pc_strobe tS 4.0 ns 1 pass inp::\ibus_reader:iu_readSBV_0\.Q tSCS 8.0 ns 1 pass out::data_to_fo_8 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\fi_reader:fi_read_stateSBV_2\)ao_to_pc_strobe[55] inp::ao_from_pc_ack ---->ao_from_pc_ack tS 4.0 ns 1 pass inp::\fi_reader:fi_read_stateSBV_1\.Q tSCS 8.0 ns 1 pass out::\fi_reader:fi_read_stateSBV_2\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::ao_to_pc_ack[56] inp::ao_to_pc_strobe ---->ao_to_pc_strobe tS 4.0 ns 1 pass inp::\ibus_reader:iu_readSBV_0\.Q tSCS 8.0 ns 1 pass out::ao_to_pc_ack tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\fi_reader:timeout_0\)[57] inp::ao_from_pc_ack ---->ao_from_pc_ack tS 4.0 ns 1 pass inp::\fi_reader:fi_read_stateSBV_1\.Q tSCS 8.0 ns 1 pass out::\fi_reader:timeout_0\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::(data_to_fo_4)[58] inp::ao_to_pc_strobe ---->ao_to_pc_strobe tS 4.0 ns 1 pass inp::\ibus_reader:iu_readSBV_0\.Q tSCS 8.0 ns 1 pass out::data_to_fo_4 tCO 6.5 ns ---------------------------------------------------------------------------- cmb::fr_ref_clk[77] inp::fo_ckw.Q tCO 12.5 ns 1 pass ---------------------------------------------------------------------------- cmb::fr_rf[82] ---------------------------------------------------------------------------- cmb::fr_mode[83] ---------------------------------------------------------------------------- reg::(fi_data_1)fr_status[84] inp::\ibus_fi:read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::fi_data_1 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(fi_data_12)[85] inp::\ibus_fi:read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::fi_data_12 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(fi_data_14)[86] inp::\ibus_fi:read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::fi_data_14 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(fi_data_3)[87] inp::\ibus_fi:read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::fi_data_3 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(fi_data_5)[88] inp::\ibus_fi:read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::fi_data_5 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(refill_ibus_output_buf)[89] inp::fi_to_ibus_ack.Q tSCS 8.0 ns 1 pass inp::reset tRO 13.5 ns 1 pass out::refill_ibus_output_buf tCO 6.5 ns ---------------------------------------------------------------------------- reg::fo_d(0)[103] inp::\ibus_fo:stateSBV_0\.Q tSCS 8.0 ns 1 pass out::fo_d(0) tCO 6.5 ns ---------------------------------------------------------------------------- reg::fo_d(1)[104] inp::\ibus_fo:stateSBV_0\.Q tSCS 8.0 ns 1 pass out::fo_d(1) tCO 6.5 ns ---------------------------------------------------------------------------- reg::fo_d(2)[105] inp::\ibus_fo:stateSBV_0\.Q tSCS 8.0 ns 1 pass out::fo_d(2) tCO 6.5 ns ---------------------------------------------------------------------------- reg::fo_d(3)[106] inp::\ibus_fo:stateSBV_0\.Q tSCS 8.0 ns 1 pass out::fo_d(3) tCO 6.5 ns ---------------------------------------------------------------------------- reg::fo_d(4)[107] inp::\ibus_fo:stateSBV_0\.Q tSCS 8.0 ns 1 pass out::fo_d(4) tCO 6.5 ns ---------------------------------------------------------------------------- reg::fo_d(5)[108] inp::\ibus_fo:stateSBV_0\.Q tSCS 8.0 ns 1 pass out::fo_d(5) tCO 6.5 ns ---------------------------------------------------------------------------- reg::fo_d(6)[109] inp::\ibus_fo:stateSBV_0\.Q tSCS 8.0 ns 1 pass out::fo_d(6) tCO 6.5 ns ---------------------------------------------------------------------------- reg::fo_d(7)[110] inp::\ibus_fo:stateSBV_0\.Q tSCS 8.0 ns 1 pass out::fo_d(7) tCO 6.5 ns ---------------------------------------------------------------------------- reg::fo_d(8)[112] inp::\ibus_fo:stateSBV_0\.Q tSCS 8.0 ns 1 pass out::fo_d(8) tCO 6.5 ns ---------------------------------------------------------------------------- reg::fo_d(9)[113] inp::\ibus_fo:stateSBV_0\.Q tSCS 8.0 ns 1 pass out::fo_d(9) tCO 6.5 ns ---------------------------------------------------------------------------- cmb::fo_enn_l[117] ---------------------------------------------------------------------------- reg::fo_ena_l[118] inp::fo_ckw.Q ---->fr_ref_clk tSCS 14.0 ns 2 passes out::fo_ena_l tCO 6.5 ns ---------------------------------------------------------------------------- reg::fo_ckw[119] inp::fo_ckw.Q tSCS 8.0 ns 1 pass out::fo_ckw tCO 6.5 ns ---------------------------------------------------------------------------- cmb::fo_mode[122] ---------------------------------------------------------------------------- cmb::fo_foto[123] ---------------------------------------------------------------------------- reg::fifo_reset_l[127] inp::fr_rdy_l tS 5.5 ns 1 pass inp::\fr_imp:fr_stateSBV_0\.Q tSCS 8.0 ns 1 pass inp::reset_fifo.Q tPO 17.5 ns 1 pass out::fifo_reset_l tCO 6.5 ns ---------------------------------------------------------------------------- reg::fifo_write_l[128] inp::fr_rdy_l tS 5.5 ns 1 pass inp::\fr_imp:fr_stateSBV_0\.Q tSCS 8.0 ns 1 pass inp::reset_fifo.Q tPO 17.5 ns 1 pass out::fifo_write_l tCO 6.5 ns ---------------------------------------------------------------------------- reg::fifo_d(8)[129] inp::fr_rdy_l tS 5.5 ns 1 pass inp::\fr_imp:fr_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::fifo_d(8) tCO 6.5 ns ---------------------------------------------------------------------------- reg::fifo_d(0)[131] inp::fr_rdy_l tS 5.5 ns 1 pass inp::\fr_imp:fr_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::fifo_d(0) tCO 6.5 ns ---------------------------------------------------------------------------- reg::fifo_d(1)[132] inp::fr_rdy_l tS 5.5 ns 1 pass inp::\fr_imp:fr_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::fifo_d(1) tCO 6.5 ns ---------------------------------------------------------------------------- reg::fifo_d(2)[133] inp::fr_rdy_l tS 5.5 ns 1 pass inp::\fr_imp:fr_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::fifo_d(2) tCO 6.5 ns ---------------------------------------------------------------------------- reg::fifo_d(3)[134] inp::fr_rdy_l tS 5.5 ns 1 pass inp::\fr_imp:fr_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::fifo_d(3) tCO 6.5 ns ---------------------------------------------------------------------------- reg::fifo_d(4)[135] inp::fr_rdy_l tS 5.5 ns 1 pass inp::\fr_imp:fr_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::fifo_d(4) tCO 6.5 ns ---------------------------------------------------------------------------- reg::fifo_d(5)[136] inp::fr_rdy_l tS 5.5 ns 1 pass inp::\fr_imp:fr_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::fifo_d(5) tCO 6.5 ns ---------------------------------------------------------------------------- reg::fifo_d(6)[137] inp::fr_rdy_l tS 5.5 ns 1 pass inp::\fr_imp:fr_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::fifo_d(6) tCO 6.5 ns ---------------------------------------------------------------------------- reg::fifo_d(7)[138] inp::fr_rdy_l tS 5.5 ns 1 pass inp::\fr_imp:fr_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::fifo_d(7) tCO 6.5 ns ---------------------------------------------------------------------------- reg::(fiber_to_ibus_buf_9)[143] inp::fifo_out(1) tS 4.0 ns 1 pass inp::\pump:pump_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::fiber_to_ibus_buf_9 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(fiber_to_ibus_buf_0)[144] inp::fifo_out(8) ---->fifo_out(8) tS 4.0 ns 1 pass inp::\pump:pump_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::fiber_to_ibus_buf_0 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(data_pump_word_ready)[145] inp::fifo_out(8) ---->fifo_out(8) tS 4.0 ns 1 pass inp::\pump:count_0\.Q tSCS 8.0 ns 1 pass out::data_pump_word_ready tCO 6.5 ns ---------------------------------------------------------------------------- reg::fifo_read_l[146] inp::\pump:pump_stateSBV_0\.Q tSCS 8.0 ns 1 pass inp::reset tRO 13.5 ns 1 pass out::fifo_read_l tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\pump:count_0\)[147] inp::fifo_out(8) ---->fifo_out(8) tS 4.0 ns 1 pass inp::\pump:count_0\.Q tSCS 8.0 ns 1 pass out::\pump:count_0\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::(fi_data_15)[148] inp::\ibus_fi:read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::fi_data_15 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(fi_data_9)fifo_empty_l[149] inp::\ibus_fi:read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::fi_data_9 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(fiber_to_ibus_buf_8)fifo_out(8)[150] inp::fifo_out(0) ---->fifo_out(0) tS 4.0 ns 1 pass inp::\pump:pump_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::fiber_to_ibus_buf_8 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(fiber_to_ibus_buf_6)fifo_out(0)[152] inp::fifo_out(8) ---->fifo_out(8) tS 4.0 ns 1 pass inp::\pump:pump_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::fiber_to_ibus_buf_6 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(fiber_to_ibus_buf_14)fifo_out(2)[154] inp::fifo_out(6) tS 4.0 ns 1 pass inp::\pump:pump_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::fiber_to_ibus_buf_14 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(fiber_to_ibus_buf_10)fifo_out(3)[155] inp::fifo_out(2) ---->fifo_out(2) tS 4.0 ns 1 pass inp::\pump:pump_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::fiber_to_ibus_buf_10 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(fiber_to_ibus_buf_11)fifo_out(4)[156] inp::fifo_out(3) ---->fifo_out(3) tS 4.0 ns 1 pass inp::\pump:pump_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::fiber_to_ibus_buf_11 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(fiber_to_ibus_buf_15)fifo_out(5)[157] inp::fifo_out(7) tS 4.0 ns 1 pass inp::\pump:pump_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::fiber_to_ibus_buf_15 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(fiber_to_ibus_buf_7)[887] inp::fifo_out(8) ---->fifo_out(8) tS 4.0 ns 1 pass inp::\pump:pump_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::fiber_to_ibus_buf_7 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\pump:pump_stateSBV_0\)[889] inp::fifo_out(8) ---->fifo_out(8) tS 4.0 ns 1 pass inp::\pump:count_0\.Q tSCS 8.0 ns 1 pass out::\pump:pump_stateSBV_0\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\pump:pump_stateSBV_1\)[891] inp::fifo_out(8) ---->fifo_out(8) tS 4.0 ns 1 pass inp::\pump:count_0\.Q tSCS 8.0 ns 1 pass out::\pump:pump_stateSBV_1\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\fi_reader:this_is_a_ctrl_transaction\)[893] inp::\fi_reader:fi_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass inp::reset tRO 13.5 ns 1 pass out::\fi_reader:this_is_a_ctrl_transaction\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\pump:count_1\)[895] inp::fifo_out(8) ---->fifo_out(8) tS 4.0 ns 1 pass inp::\pump:count_0\.Q tSCS 8.0 ns 1 pass out::\pump:count_1\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::(fi_data_8)[897] inp::\ibus_fi:read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::fi_data_8 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(fiber_to_ibus_buf_1)[899] inp::fifo_out(8) ---->fifo_out(8) tS 4.0 ns 1 pass inp::\pump:pump_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::fiber_to_ibus_buf_1 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(reset_fifo)[901] inp::\fi_reader:fi_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::reset_fifo tCO 6.5 ns ---------------------------------------------------------------------------- reg::(fiber_to_ibus_buf_2)[905] inp::fifo_out(8) ---->fifo_out(8) tS 4.0 ns 1 pass inp::\pump:pump_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::fiber_to_ibus_buf_2 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(fiber_to_ibus_buf_12)[907] inp::fifo_out(4) ---->fifo_out(4) tS 4.0 ns 1 pass inp::\pump:pump_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::fiber_to_ibus_buf_12 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(fiber_to_ibus_buf_4)[909] inp::fifo_out(8) ---->fifo_out(8) tS 4.0 ns 1 pass inp::\pump:pump_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::fiber_to_ibus_buf_4 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(fiber_to_ibus_buf_13)[911] inp::fifo_out(5) ---->fifo_out(5) tS 4.0 ns 1 pass inp::\pump:pump_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::fiber_to_ibus_buf_13 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(fiber_to_ibus_buf_3)[913] inp::fifo_out(8) ---->fifo_out(8) tS 4.0 ns 1 pass inp::\pump:pump_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::fiber_to_ibus_buf_3 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(fiber_to_ibus_buf_5)[917] inp::fifo_out(8) ---->fifo_out(8) tS 4.0 ns 1 pass inp::\pump:pump_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::fiber_to_ibus_buf_5 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(data_to_fo_0)[921] inp::ao_to_pc_strobe ---->ao_to_pc_strobe tS 4.0 ns 1 pass inp::\ibus_reader:iu_readSBV_0\.Q tSCS 8.0 ns 1 pass out::data_to_fo_0 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(data_to_fo_1)[923] inp::ao_to_pc_strobe ---->ao_to_pc_strobe tS 4.0 ns 1 pass inp::\ibus_reader:iu_readSBV_0\.Q tSCS 8.0 ns 1 pass out::data_to_fo_1 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(data_to_fo_10)[925] inp::ao_to_pc_strobe ---->ao_to_pc_strobe tS 4.0 ns 1 pass inp::\ibus_reader:iu_readSBV_0\.Q tSCS 8.0 ns 1 pass out::data_to_fo_10 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(data_to_fo_11)[927] inp::ao_to_pc_strobe ---->ao_to_pc_strobe tS 4.0 ns 1 pass inp::\ibus_reader:iu_readSBV_0\.Q tSCS 8.0 ns 1 pass out::data_to_fo_11 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(data_to_fo_12)[929] inp::ao_to_pc_strobe ---->ao_to_pc_strobe tS 4.0 ns 1 pass inp::\ibus_reader:iu_readSBV_0\.Q tSCS 8.0 ns 1 pass out::data_to_fo_12 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(data_to_fo_14)[931] inp::ao_to_pc_strobe ---->ao_to_pc_strobe tS 4.0 ns 1 pass inp::\ibus_reader:iu_readSBV_0\.Q tSCS 8.0 ns 1 pass out::data_to_fo_14 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(fi_data_10)[935] inp::\ibus_fi:read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::fi_data_10 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\ibus_fi:read_stateSBV_1\)[937] inp::\ibus_fi:read_stateSBV_1\.Q tSCS 8.0 ns 1 pass out::\ibus_fi:read_stateSBV_1\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\ibus_fi:timeout_1\)[939] inp::\ibus_fi:read_stateSBV_1\.Q tSCS 8.0 ns 1 pass out::\ibus_fi:timeout_1\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\ibus_fi:timeout_0\)[941] inp::\ibus_fi:read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::\ibus_fi:timeout_0\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\ibus_fi:timeout_2\)[943] inp::\ibus_fi:read_stateSBV_1\.Q tSCS 8.0 ns 1 pass out::\ibus_fi:timeout_2\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\ibus_fi:read_stateSBV_0\)[945] inp::\ibus_fi:read_stateSBV_1\.Q tSCS 8.0 ns 1 pass out::\ibus_fi:read_stateSBV_0\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\ibus_fi:timeout_3\)[947] inp::\ibus_fi:read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::\ibus_fi:timeout_3\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::(fi_to_ibus_ack)[949] inp::\fi_reader:fi_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::fi_to_ibus_ack tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\ibus_reader:timeout_0\)[951] inp::ao_to_pc_strobe ---->ao_to_pc_strobe tS 4.0 ns 1 pass inp::\ibus_reader:iu_readSBV_0\.Q tSCS 8.0 ns 1 pass out::\ibus_reader:timeout_0\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\ibus_reader:timeout_2\)[953] inp::ao_to_pc_strobe ---->ao_to_pc_strobe tS 4.0 ns 1 pass inp::\ibus_reader:iu_readSBV_0\.Q tSCS 8.0 ns 1 pass out::\ibus_reader:timeout_2\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\ibus_reader:iu_readSBV_1\)[955] inp::ao_to_pc_strobe ---->ao_to_pc_strobe tS 4.0 ns 1 pass inp::\ibus_reader:iu_readSBV_0\.Q tSCS 8.0 ns 1 pass out::\ibus_reader:iu_readSBV_1\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\fi_reader:timeout_3\)[999] inp::ao_from_pc_ack ---->ao_from_pc_ack tS 4.0 ns 1 pass inp::\fi_reader:fi_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::\fi_reader:timeout_3\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\fi_reader:fi_read_stateSBV_1\)[1001] inp::ao_from_pc_ack ---->ao_from_pc_ack tS 4.0 ns 1 pass inp::\fi_reader:fi_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::\fi_reader:fi_read_stateSBV_1\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\fi_reader:fi_read_stateSBV_0\)[1003] inp::ao_from_pc_ack ---->ao_from_pc_ack tS 4.0 ns 1 pass inp::\fi_reader:fi_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::\fi_reader:fi_read_stateSBV_0\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::(data_to_fo_7)[1005] inp::ao_to_pc_strobe ---->ao_to_pc_strobe tS 4.0 ns 1 pass inp::\ibus_reader:iu_readSBV_0\.Q tSCS 8.0 ns 1 pass out::data_to_fo_7 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(write_to_fo_req)[1007] inp::\ibus_reader:iu_readSBV_0\.Q tSCS 8.0 ns 1 pass out::write_to_fo_req tCO 6.5 ns ---------------------------------------------------------------------------- reg::(data_to_fo_6)[1009] inp::ao_to_pc_strobe ---->ao_to_pc_strobe tS 4.0 ns 1 pass inp::\ibus_reader:iu_readSBV_0\.Q tSCS 8.0 ns 1 pass out::data_to_fo_6 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(data_to_fo_5)[1011] inp::ao_to_pc_strobe ---->ao_to_pc_strobe tS 4.0 ns 1 pass inp::\ibus_reader:iu_readSBV_0\.Q tSCS 8.0 ns 1 pass out::data_to_fo_5 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\fi_reader:timeout_2\)[1013] inp::ao_from_pc_ack ---->ao_from_pc_ack tS 4.0 ns 1 pass inp::\fi_reader:fi_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::\fi_reader:timeout_2\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::(fi_data_7)[1047] inp::\ibus_fi:read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::fi_data_7 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(fi_data_0)[1049] inp::\ibus_fi:read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::fi_data_0 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(fi_data_11)[1051] inp::\ibus_fi:read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::fi_data_11 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(fi_data_13)[1053] inp::\ibus_fi:read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::fi_data_13 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(fi_data_2)[1055] inp::\ibus_fi:read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::fi_data_2 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(fi_data_4)[1057] inp::\ibus_fi:read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::fi_data_4 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(fi_data_6)[1059] inp::\ibus_fi:read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::fi_data_6 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(fi_to_ibus_req)[1061] inp::\ibus_fi:read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::fi_to_ibus_req tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\ibus_fo:stateSBV_2\)[1081] inp::fo_ckw.Q ---->fr_ref_clk tSCS 14.0 ns 2 passes out::\ibus_fo:stateSBV_2\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::(data_to_fo_15)[1083] inp::ao_to_pc_strobe ---->ao_to_pc_strobe tS 4.0 ns 1 pass inp::\ibus_reader:iu_readSBV_0\.Q tSCS 8.0 ns 1 pass out::data_to_fo_15 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(data_to_fo_2)[1085] inp::ao_to_pc_strobe ---->ao_to_pc_strobe tS 4.0 ns 1 pass inp::\ibus_reader:iu_readSBV_0\.Q tSCS 8.0 ns 1 pass out::data_to_fo_2 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(data_to_fo_3)[1087] inp::ao_to_pc_strobe ---->ao_to_pc_strobe tS 4.0 ns 1 pass inp::\ibus_reader:iu_readSBV_0\.Q tSCS 8.0 ns 1 pass out::data_to_fo_3 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(write_to_fo_ack)[1089] inp::fo_ckw.Q ---->fr_ref_clk tSCS 14.0 ns 2 passes out::write_to_fo_ack tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\ibus_fo:stateSBV_0\)[1091] inp::\ibus_fo:stateSBV_1\.Q tSCS 8.0 ns 1 pass out::\ibus_fo:stateSBV_0\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\ibus_fo:stateSBV_1\)[1105] inp::fo_ckw.Q ---->fr_ref_clk tSCS 14.0 ns 2 passes out::\ibus_fo:stateSBV_1\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\fr_imp:fr_stateSBV_0\)[1119] inp::fr_rdy_l tS 5.5 ns 1 pass inp::\fr_imp:fr_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::\fr_imp:fr_stateSBV_0\ tCO 6.5 ns ---------------------------------------------------------------------------- Worst Case Path Summary ----------------------- tS = 5.5 ns for fifo_reset_l.D tSCS = 14.0 ns for fo_ena_l.D tCO = 12.5 ns for debug tPO = 17.5 ns for fifo_reset_l.AP tRO = 13.5 ns for refill_ibus_output_buf.AR Summary: Error Count = 0 Warning Count = 0 Completed Successfully