--Signal naming conventions -- ON- chip signals are not preficed -- Upper part of the on-board bus signale preficed with iu_ -- Lower part of the on-board bus signals preficed with il_ -- Upper part of pc bus pu_ -- Lower part of pc bus pl_ -- Backplane bus bp_ -- fiber output fo_ -- fiber input fi_ -- -- -- take care of reading data from the onboard bus -- direction: ibus_upper (BP data read) to FO_action -- library ieee; use ieee.std_logic_1164.all; use work.numeric_std.all; entity read_from_ibus is port ( clk : in std_logic; reset : in std_logic; iu_req : in std_logic; iu_ack : buffer std_logic; iu_io : in std_logic_vector(15 downto 0); data : out std_logic_vector(15 downto 0); req : out std_logic; ack : in std_logic); end read_from_ibus; architecture read_from_ibus_arch of read_from_ibus is type iu_read_state is (idle,hs,iu_hs1,iu_hs2); signal iu_read : iu_read_state; signal timeout : unsigned(3 downto 0); begin -- write_to_ibus_arch iu_reader: process (clk, reset) begin -- process iu_writer if reset = '1' then -- asynchronous reset (active low) elsif clk'event and clk = '1' then -- rising clock edge req <= '0'; iu_ack <= '0'; case iu_read is when idle => if (iu_req = '1') then data <= iu_io; iu_ack <= '1'; iu_read <= hs; timeout <= "0000"; else iu_read <= idle; end if; when hs => iu_ack <= '1'; req <= '1'; if (iu_req = '0') then iu_read <= iu_hs1; timeout <= "0000"; else if (timeout = "1111") then iu_read <= iu_hs1; timeout <= "0000"; else timeout <= timeout+1; end if; end if; when iu_hs1 => req <= '1'; if (ack = '1') then req <= '0'; iu_read <= iu_hs2; else if (timeout = "1111") then iu_read <= idle; else timeout <= timeout+1; end if; end if; when iu_hs2 => -- no timeout here because by this -- stage we know there is something -- at the other end if (ack = '0') then iu_read <= idle; end if; when others => iu_read <= idle; end case; end if; end process iu_reader; end read_from_ibus_arch; -- This block reads data from the FI when addressed. It captures and -- acts on command data and places other data or address info in the on -- chip buffers. -- Each transaction typically consists of two transfers, an address transfer -- followed by a data transfer. There are a few exceptions where only an -- address transfer is required, namelly a soft reset and switching to -- loopback mode. -- When the code detects an address transfer it check to see if it is being -- addressed. If it is then enables itself. Thie chip stays enabled untill -- another address transfer occurs. In this way the chip can accept follow -- up data transfers. -- library ieee; use ieee.std_logic_1164.all; use work.numeric_std.all; entity read_from_FI is -- to BP direction -- note internal upper bus is used - from FI=PC=upper port ( clk : in std_logic; reset : in std_logic; req : in std_logic; ack : out std_logic; data : in std_logic_vector(15 downto 0); il_io : out std_logic_vector(15 downto 0); address : buffer std_logic_vector(7 downto 0); il_req : buffer std_logic; il_ack : in std_logic; i_am_remote:in std_logic; my_data_address:in std_logic_vector(3 downto 0); my_ctrl_address:in std_logic_vector(3 downto 0); loopback_state:buffer std_logic; request_reset:out std_logic; FI_i_am_addressed: buffer std_logic; receive_enabled : buffer std_logic ); end read_from_FI; architecture read_from_FI_arch of read_from_FI is type FI_read_type is (idle,am_i_addressed,FI_hs_for_address,FI_hs_for_data, FI_use_ctrl_data,internal_ack1,internal_ack2); signal FI_read_state : FI_read_type; signal timeout : unsigned(3 downto 0); signal this_is_a_ctrl_transaction : std_logic; begin -- read_from_FI_arch -- purpose: read from the fiber receiver -- type : sequential -- inputs : clk, reset -- outputs: read_FI: process (clk, reset) begin -- process read_ibus if reset = '1' then -- asynchronous reset (active low) FI_i_am_addressed <= '0'; this_is_a_ctrl_transaction <= '0'; -- by default load counter -- counter_start <= "11111111"; -- counter_end <= "11111111"; -- for i in 7 downto 0 loop -- -- end loop; -- i elsif clk'event and clk = '1' then -- rising clock edge ack <= '0'; il_req <= '0'; request_reset <= '0'; receive_enabled <= '1'; -- this side is always enabled loopback_state <= '0'; -- disable loopback case (FI_read_state) is when idle => ack <= '0'; if (req = '1') then il_io <= data; FI_read_state <= am_i_addressed; timeout <= "0000"; end if; when am_i_addressed => FI_read_state <= idle; if (data(15) = '1') then -- this is an address FI_i_am_addressed <= '0'; -- any addtress transaction should -- reset select bits on all chips this_is_a_ctrl_transaction <= '0'; if (data(12) = i_am_remote) then if (data(11 downto 8) = my_ctrl_address) then this_is_a_ctrl_transaction <= '1'; -- FI_i_am_addressed <= '1'; -- don't loopback loopback_state <= data(4); request_reset <= data(5); -- this side is always enabled -- receive_enabled <= data(0); address <= data(7 downto 0); FI_read_state <= FI_hs_for_address; else if (data(11 downto 8) = my_data_address) then -- FI_i_am_addressed <= '1'; address <= data(7 downto 0); FI_read_state <= FI_hs_for_address; end if; end if; -- -- This is not an address, but if this chip is already addressed -- then this will be a data transaction to complete the previous -- address transaction -- -- if (FI_i_am_addressed = '1') then FI_read_state <= FI_hs_for_data; -- else -- FI_read_state <= internal_ack1; -- -- end if; end if; else FI_read_state <= FI_hs_for_data; end if; when FI_hs_for_address => ack <= '1'; if (req = '0') then FI_read_state <= idle; else if (timeout = "1111") then -- Hmm this timeout will lead to a spurious transaction, but not -- to worry, there must be a serious problem somewhere else in -- this case FI_read_state <= idle; else timeout <= timeout+1; end if; end if; when FI_hs_for_data => ack <= '1'; if (req = '0') then -- -- things to do once the external transaction has completed -- if (this_is_a_ctrl_transaction = '1') then FI_read_state <= FI_use_ctrl_data; else FI_read_state <= internal_ack1; timeout <= "0000"; end if; else if (timeout = "1111") then -- -- If this timeout is triggered we are likely to keep looping. -- By gong to an idle state we ensure that only 1 data transaction -- can take place anyway, thought there is a possibility of -- losing a transaction as well. -- FI_read_state <= idle; else timeout <= timeout+1; end if; end if; if (this_is_a_ctrl_transaction = '0') then -- -- Get a jump start on completing internal transactions -- il_req <= '1'; -- attempt to transfer data out end if; when FI_use_ctrl_data => -- -- What we do with the control data is completely dependent on the -- chip all of the rest of this code should be fairly generic, if -- a littl over elaborate in most cases -- --if (address(1 downto 0) = "01") then --c1: for i in 0 to 7 loop --* put reset fifo here --counter_start(i) <= data(i); --counter_end(i) <= data(i+8); --end loop c1; --end if; FI_read_state <= idle; when internal_ack1 => il_req <= '1'; if (il_ack = '1') then timeout <= "0000"; il_req <= '0'; FI_read_state <= internal_ack2; else if (timeout = "1111") then FI_read_state <= idle; else timeout <= timeout+1; end if; end if; when internal_ack2 => il_req <= '0'; if (il_ack = '0') then FI_read_state <= idle; else if (timeout = "1111") then FI_read_state <= idle; else timeout <= timeout+1; end if; end if; when others => FI_read_state <= idle; end case; end if; end process read_FI; end read_from_FI_arch; library ieee; use ieee.std_logic_1164.all; use work.numeric_std.all; entity ibus_FO_action is port ( clk : in std_logic; reset : in std_logic; il_i_am_addressed: in std_logic; fo_req : in std_logic; fo_ack : buffer std_logic; data : in std_logic_vector(15 downto 0); fiber_clk: in std_logic; fo_d: out std_logic_vector(9 downto 0); fo_ENA_l: out std_logic ); end ibus_FO_action; architecture arch_ibus_FO_action of ibus_FO_action is -- purpose: type states is (fo_idle,fo_byte1,fo_wait1,fo_byte2,fo_wait2); signal state : states; signal fiber_out_buf : std_logic_vector(15 downto 0); signal byte_buf : std_logic_vector(7 downto 0); signal fo_send : std_logic; -- alias sc : std_logic is fo_d(8); alias svs : std_logic is fo_d(9); -- purpose: performs the actual monitor action -- type: memorizing -- inputs: clk, reset -- outputs: begin FO_action : process (clk, reset) begin -- process FO_action if reset = '1' then -- if reset_l = '0' then -- activities triggered by rising edge of clock elsif clk'event and clk = '1' then fo_send <= '0'; -- enable needs to stay low for both bytes case state is when fo_idle => fo_d(8) <= '0'; -- command channel flag sc <= '0'; svs <= '0'; fo_ack <= '0'; if (fo_req = '1') then -- if (il_i_am_addressed = '0') then fo_d(7 downto 0) <= data(7 downto 0); state <= fo_byte1; -- if (fiber_clk = '1') then -- -- if fiber clock is high it is now -- -- transitioning to low, which -- -- means data will be tranmitted -- -- on next cycle. since that -- -- will present a rising edge -- --fo_not_strobe -- state <= fo_wait1; -- -- -- -- Hmm appears to be a bug in the component desciption -- -- it appears that a low on ena any time that the -- -- clock is high sends the data, rather than -- -- the rising edge as written. -- -- fo_send <= '1'; -- fo_send <= '1'; -- else -- state <= fo_byte1; -- end if; -- else -- state <= fo_idle; -- end if; end if; when fo_byte1 => if (fiber_clk = '1') then fo_ENA_l <= '0'; -- fo_send <= '1'; state <= fo_wait1; fo_ack <= '1'; -- so other side has time to see it else state <= fo_byte1; end if; when fo_wait1 => -- fo_send <= '1'; fo_ENA_l <= '0'; state <= fo_byte2; when fo_byte2 => fo_ENA_l <= '0'; -- -- here fiber clock transitioning from high to low -- -- fo_send <= '1'; fo_d(7 downto 0) <= data(15 downto 8); state <= fo_wait2; when fo_wait2 => -- final low to high -- -- -- Give this fiber strobe time tp get back to high -- -- fo_send <= '1'; state <= fo_idle; when others => state <= fo_idle; end case; end if; end process FO_action; -- fo_ENA_l <= '0' when (fo_send = '1') else '1'; end arch_ibus_FO_action; library ieee; use ieee.std_logic_1164.all; use work.numeric_std.all; entity ibus_FI_port is port ( clk: in std_logic; reset : in std_logic; data : buffer std_logic_vector(15 downto 0); req : buffer std_logic; ack : in std_logic; fiber_to_ibus_buf : in std_logic_vector(15 downto 0); data_pump_word_ready : in std_logic; refill_ibus_output_buf : out std_logic ); end ibus_FI_port; architecture arch_ibus_FI_port of ibus_FI_port is type read_states is (idle,read_req,end_cycle); signal read_state: read_states; signal timeout : unsigned(3 downto 0); begin ibus_FI_read : process (clk, reset) begin if reset = '1' then -- refill_ibus_output_buf <= '1'; refill_ibus_output_buf <= '0'; -- asynchronous reset (active low) elsif clk'event and clk = '1' then req <= '0'; refill_ibus_output_buf <= '1'; case read_state is when idle => req <= '0'; timeout <= "0000"; if (data_pump_word_ready = '1') then if (ack = '0') then data(15 downto 0) <= fiber_to_ibus_buf(15 downto 0); req <= '1'; -- refill_ibus_output_buf <= '0'; read_state <= read_req; else read_state <= idle; end if; end if; when read_req => if (ack = '1') then req <= '0'; read_state <= end_cycle; else if (timeout = "1111") then read_state <= idle; else timeout <= timeout+1; read_state <= read_req; end if; end if; when end_cycle => refill_ibus_output_buf <= '1'; if (ack = '0') then -- refill_ibus_output_buf <= '1'; refill_ibus_output_buf <= '0'; read_state <= idle; else if (timeout = "1111") then read_state <= idle; else timeout <= timeout+1; read_state <= end_cycle; end if; end if; when others => read_state <= idle; end case; end if; end process ibus_FI_read; end arch_ibus_FI_port; library ieee; use ieee.std_logic_1164.all; use work.numeric_std.all; entity fiber_rec is port (clk : in std_logic; fr_d: in std_logic_vector(11 downto 0); -- data bus from fiber rec fr_RDY_l: in std_logic; -- from fiber rec RDY fr_status: in std_logic; -- from fiber rec SO receive_enabled: in std_logic; increment_fifo_count: buffer std_logic; violation_count: buffer unsigned(7 downto 0); fifo_reset_l: buffer std_logic; -- output to FIFO reset fifo_D: out std_logic_vector(8 downto 0); -- output to FIFO d inputs fifo_WRITE_l: out std_logic; -- FIFO write strobe reset_fifo_request: in std_logic ); end fiber_rec; -- purpose: manages recept of fiber data and its storage in the fifo architecture arch_fiber_rec of fiber_rec is type fr_states is (idle,fifo_latch);-- handshake states signal fr_state : fr_states; -- handshake alias code_violation : std_logic is fr_d(9); alias control_byte : std_logic is fr_d(8); begin -- fiber_rec_arch -- type: memorizing -- inputs: clk, reset -- outputs: fr : process (clk, fr_RDY_l,reset_fifo_request) begin -- process fr if (reset_fifo_request = '1') then fifo_WRITE_l <= '1'; fifo_reset_l <= '1'; -- activities triggered by asynchronous reset (active low) elsif clk'event and clk = '1' then -- fifo_reset_l <= '1'; -- increment_fifo_count <= '0'; -- fifo_reset_l <= '1'; case fr_state is when idle => if (reset_fifo_request = '1') then fifo_reset_l <= '0'; violation_count <= (others => '0'); else if (fr_status = '1' and receive_enabled = '1') then if (fr_RDY_l = '0') then -- if (code_violation = '1') then -- violation_count <= violation_count+1; -- end if; fifo_D <= fr_d(8 downto 0); fr_state <= fifo_latch; increment_fifo_count <= '1'; fifo_reset_l <= '1'; fifo_WRITE_l <= '0'; end if; end if; end if; when fifo_latch => if (reset_fifo_request = '1') then fifo_reset_l <= '0'; else fifo_WRITE_l <= '1'; -- fifo_WRITE_l <= '0'; end if; fr_state <= idle; when others => fr_state <= idle; end case; end if; end process fr; end arch_fiber_rec; library ieee; use ieee.std_logic_1164.all; use work.numeric_std.all; entity fifo_data_pump is port (clk : in std_logic; reset : in std_logic; violation_count: in unsigned(7 downto 0); fiber_to_ibus_buf: buffer std_logic_vector(15 downto 0); fifo_OUT: in std_logic_vector(8 downto 0); fifo_READ_l: out std_logic; data_pump_word_ready: buffer std_logic; refill_ibus_output_buf: in std_logic; fifo_reset_l: in std_logic; fifo_EMPTY_l: in std_logic ); end fifo_data_pump; -- purpose: pump data out of the fifo architecture arch_fifo_data_pump of fifo_data_pump is type pump_states is (idle,fifo_strobe,fifo_read_data,fifo_wait_on_empty);-- handshake states signal pump_state : pump_states; -- handshake signal count : unsigned(1 downto 0); begin -- fifo_data_pump_arch -- purpose: pump : process (clk,reset) begin -- process pump -- activities triggered by asynchronous reset (active low) if reset = '1' then fifo_READ_l <= '1'; elsif clk'event and clk = '1' then --debug <= '0'; data_pump_word_ready <= '0'; -- data_pump_word_ready <= '1'; fifo_READ_l <= '1'; case pump_state is when idle => count <= "00"; -- fifo_READ_l <= '1'; -- data_pump_word_ready <= '1'; if (fifo_reset_l = '1' or refill_ibus_output_buf = '1') then data_pump_word_ready <= '0'; if (fifo_empty_l = '0') then -- This is an inverted signal so here there is -- no data in the fifo, must now wait for data -- to bcome available pump_state <= fifo_wait_on_empty; else pump_state <= fifo_strobe; end if; else pump_state <= idle; end if; when fifo_wait_on_empty => data_pump_word_ready <= '0'; --- may need to chsnge to 1 if (fifo_EMPTY_l = '0') then pump_state <= fifo_wait_on_empty; else pump_state <= fifo_strobe; end if; when fifo_strobe => data_pump_word_ready <= '0'; fifo_READ_l <= '0'; pump_state <= fifo_read_data; when fifo_read_data => if (fifo_out(8) = '1') then count <= "00"; fifo_READ_l <= '1'; pump_state <= fifo_strobe; else fiber_to_ibus_buf(15 downto 8) <= fifo_out(7 downto 0); fiber_to_ibus_buf(7 downto 0) <= fiber_to_ibus_buf(15 downto 8); if (count = "01") then data_pump_word_ready <= '1'; pump_state <= idle; else count <= count +1; fifo_READ_l <= '1'; if (fifo_empty_l = '0') then pump_state <= fifo_wait_on_empty; else pump_state <= fifo_strobe; end if; end if; end if; -- data_pump_word_ready <= '0'; -- fiber_to_ibus_buf(15 downto 8) <= fifo_out(7 downto 0); -- fiber_to_ibus_buf(7 downto 0) <= -- fiber_to_ibus_buf(15 downto 8); -- -- -- We use the control indicator to delimit word boundaries, -- -- end of transfer occurs when we see the control bits, -- -- no matter how many bytes are used. -- -- -- if (fifo_out(8) = '1') then -- pump_state <= idle; -- else -- if (fifo_empty_l = '0') then -- pump_state <= fifo_wait_on_empty; -- else -- pump_state <= fifo_strobe; -- end if; -- end if; when others => pump_state <= idle; end case; end if; end process pump; end arch_fifo_data_pump; library ieee; use ieee.std_logic_1164.all; use work.numeric_std.all; entity tout is port ( -- led1 : out std_logic; -- led2 : out std_logic; -- led3 : out std_logic; clk : in std_logic; fast : in std_logic; slow : in std_logic; DEBUG : buffer std_logic; -- -- on board data bus and associated control signals -- id: inout std_logic_vector(31 downto 0); -- -- global -- reset: in std_logic; AO_FROM_PC_STROBE: buffer std_logic; AO_FROM_PC_ACK: in std_logic; AO_TO_PC_STROBE: in std_logic; AO_TO_PC_ACK: buffer std_logic; in_strobe: in std_logic; -- fiber reciever -- fr_d: in std_logic_vector(11 downto 0); fr_ref_clk: out std_logic; fr_rf: buffer std_logic; fr_mode: out std_logic; fr_status: in std_logic; fr_RDY_l: in std_logic; fr_ckr: in std_logic; -- -- fiber output section -- fo_d: out std_logic_vector(9 downto 0); fo_ENN_l: out std_logic; fo_ENA_l: out std_logic; fo_CKW: buffer std_logic; fo_mode: out std_logic; fo_foto: out std_logic; fo_RP_l: in std_logic; -- -- fifo stuff -- fifo_reset_l: buffer std_logic; -- Declare as a buffer since we want fifo_WRITE_l: out std_logic; fifo_D: out std_logic_vector(8 downto 0); fifo_READ_l: out std_logic; fifo_FULL_l: in std_logic; fifo_HALF_l: in std_logic; fifo_EMPTY_l: in std_logic; fifo_OUT: in std_logic_vector(8 downto 0) ); end tout; -- purpose: Collect together preceeding modules architecture tout_arch of tout is signal write_oe : std_logic; signal read_oe : std_logic; signal fo_data_strobe : std_logic; signal violation_count : unsigned(7 downto 0); signal decriment_fifo_count : std_logic; signal increment_fifo_count : std_logic; signal data_pump_word_ready: std_logic; signal refill_ibus_output_buf: std_logic; signal fiber_to_ibus_buf : std_logic_vector(15 downto 0); signal reset_fifo : std_logic; signal rec_enabled : std_logic; type tristate_state_type is (idle,active); signal tristate_state : tristate_state_type; signal il_tristate : std_logic; signal il_ack: std_logic; signal i_am_remote : std_logic; -- set to 1 for remote board 0 for local signal my_data_address : std_logic_vector(3 downto 0); signal my_ctrl_address : std_logic_vector(3 downto 0); signal from_FI_ack : std_logic; signal from_FI_req : std_logic; signal data_from_pc : std_logic_vector(15 downto 0); signal address_from_pc : std_logic_vector(7 downto 0); signal power_up_reset: std_logic; signal soft_request_reset: std_logic; signal data_to_FO : std_logic_vector(15 downto 0); signal this_chip_selected: std_logic; signal FI_address : std_logic_vector(7 downto 0); signal FI_to_ibus_req : std_logic; signal FI_to_ibus_ack : std_logic; signal FI_data: std_logic_vector(15 downto 0); signal write_to_FO_req : std_logic; signal write_to_FO_ack : std_logic; -- alias reset_fifo : std_logic is request_reset; begin -- reset <= '1'; -- negative logic DEBUG <= AO_FROM_PC_STROBE; i_am_remote <= '1'; my_data_address <= "1111"; my_ctrl_address <= "0010"; -- -- Fiber output section -- outstrobe : process (clk,reset) begin -- process outstrobe -- activities triggered by asynchronous reset (active low) if clk'event and clk = '1' then fo_data_strobe <= not fo_data_strobe; end if; end process outstrobe; fo_CKW <= fo_data_strobe; fo_mode <= '0'; fo_foto <= '0'; fo_ENN_l <= '1'; -- purpose: Takes care of tristating the internal lower bus ack line which is -- multi-driven by several chips. This is a clocked process because we wish to -- make sure that the ack signal is set to zero before the output is tristated. -- In this way the output holding latch always holds the line low in the -- absence of any logic drive. -- type : sequential -- inputs : clk, reset, -- bus_strobe : process (clk, reset) -- begin -- process -- if reset = '1' then -- asynchronous reset (active low) -- fo_ENA_l <= '1'; -- elsif clk'event and clk = '1' then -- rising clock edge -- case (tristate_state) is -- when idle => -- il_tristate <= '1'; -- if (this_chip_selected = '1') then -- il_tristate <= '0'; -- tristate_state <= active; -- end if; -- when active => -- if (this_chip_selected = '0') then -- il_tristate <= '0'; -- Lower output before tristating -- tristate_state <= idle; -- end if; -- when others => -- tristate_state <= idle; -- end case; -- end if; -- end process bus_strobe; -- AO_FROM_PC_ACK <= il_ack when (il_tristate = '0') else 'Z'; -- -- deal with signal routing depending on setting of loopback bit -- --from_pc_ack <= to_pc_ack when (loopback_state = '1') else write_to_FO_ack; --to_pc_req <= from_pc_req when (loopback_state = '1') else FI_to_ibus_req; --data_to_pc <= data_from_FI when (loopback_state = '1') else FO_data; --write_to_FO_req <= from_pc_req when (loopback_state = '0') else '0'; --FI_to_ibus_ack <= to_pc_ack when (loopback_state = '0') else '0'; -- direction: BP data read to ibus_upper >FO ibus_reader : read_from_ibus port map ( clk => clk, reset => reset, iu_req => AO_TO_PC_STROBE, -- in iu_ack => AO_TO_PC_ACK, -- out iu_io => id(31 downto 16), data => data_to_FO, req => write_to_FO_req, -- out ack => write_to_FO_ack -- in ); -- direction: received FI=PC writes output to ibus_lower FI_reader : read_from_FI port map ( clk => clk, reset => reset, req => FI_to_ibus_req, -- in ack => FI_to_ibus_ack, -- out data => FI_data, il_io => id(15 downto 0), address => address_from_pc, il_req => AO_FROM_PC_STROBE, -- out il_ack => AO_FROM_PC_ACK, -- in i_am_remote => i_am_remote, my_ctrl_address => my_ctrl_address, my_data_address => my_data_address, request_reset => reset_fifo, FI_i_am_addressed => this_chip_selected, receive_enabled => rec_enabled ); -- ibus_FO: ibus_FO_action port map ( clk => clk, reset => reset, il_i_am_addressed => this_chip_selected, fo_req => write_to_FO_req, -- in fo_ack => write_to_FO_ack, -- out data => data_to_FO, fiber_clk => fo_CKW, fo_d => fo_d, fo_ENA_l => fo_ENA_l ); -- -- fiber receiver stuff -- fr_ref_clk <= fo_data_strobe; fr_mode <= '0'; fr_rf <= '1'; ibus_FI: ibus_FI_port port map ( clk => clk, reset => reset, data => FI_data, req => FI_to_ibus_req, -- out ack => FI_to_ibus_ack, -- in fiber_to_ibus_buf => fiber_to_ibus_buf, data_pump_word_ready => data_pump_word_ready, refill_ibus_output_buf => refill_ibus_output_buf ); fr_imp: fiber_rec port map ( clk => clk, fr_d => fr_d, fr_RDY_l => fr_RDY_l, fr_status => fr_status, receive_enabled => rec_enabled, increment_fifo_count => increment_fifo_count, violation_count => violation_count, fifo_reset_l => fifo_reset_l, fifo_D => fifo_D, fifo_WRITE_l => fifo_WRITE_l, reset_fifo_request => reset_fifo ); pump: fifo_data_pump port map ( clk => clk, reset => reset, violation_count => violation_count, fiber_to_ibus_buf => fiber_to_ibus_buf, fifo_OUT => fifo_OUT, fifo_READ_l => fifo_READ_l, data_pump_word_ready => data_pump_word_ready, refill_ibus_output_buf => refill_ibus_output_buf, fifo_reset_l => fifo_reset_l, fifo_EMPTY_l => fifo_EMPTY_l ); -- end tout_arch;