ENTITY tout IS
    PORT (
	clk : in std_logic  ; 
	fast : in std_logic  ; 
	slow : in std_logic  ; 
	debug : inout std_logic  ; 
	id : inout std_logic_vector (31 downto 0) ; 
	reset : in std_logic  ; 
	ao_from_pc_strobe : inout std_logic  ; 
	ao_from_pc_ack : in std_logic  ; 
	ao_to_pc_strobe : in std_logic  ; 
	ao_to_pc_ack : inout std_logic  ; 
	in_strobe : in std_logic  ; 
	fr_d : in std_logic_vector (11 downto 0) ; 
	fr_ref_clk : inout std_logic  ; 
	fr_rf : inout std_logic  ; 
	fr_mode : inout std_logic  ; 
	fr_status : in std_logic  ; 
	fr_rdy_l : in std_logic  ; 
	fr_ckr : in std_logic  ; 
	fo_d : inout std_logic_vector (9 downto 0) ; 
	fo_enn_l : inout std_logic  ; 
	fo_ena_l : inout std_logic  ; 
	fo_ckw : inout std_logic  ; 
	fo_mode : inout std_logic  ; 
	fo_foto : inout std_logic  ; 
	fo_rp_l : in std_logic  ; 
	fifo_reset_l : inout std_logic  ; 
	fifo_write_l : inout std_logic  ; 
	fifo_d : inout std_logic_vector (8 downto 0) ; 
	fifo_read_l : inout std_logic  ; 
	fifo_full_l : in std_logic  ; 
	fifo_half_l : in std_logic  ; 
	fifo_empty_l : in std_logic  ; 
	fifo_out : in std_logic_vector (8 downto 0)
    ) ;
END tout ;