| | | | | | | _________________ -| |- -| |- -| |- -| CYPRESS |- -| |- -| |- Warp VHDL Synthesis Compiler: Version 6.0.1 IR 18 -| |- Copyright (C) 1991-2000 Cypress Semiconductor |_______________| | | | | | | | ====================================================================== Compiling: pc_remote_sinphase.vhd Options: -m -yu -e10 -w100 -o2 -ygs -fO -fP -fL1 -v4 -dc37256 -pcy37256p160-125ac -u pc_remote_sinphase.hie -uch0000 pc_remote_sinphase.vhd ====================================================================== vhdlfe V6.0.1 IR 18: VHDL parser Fri Aug 31 17:50:24 2001 Library 'work' => directory 'lc37256' Linking 'f:\warp6\bin\std.vhd'. Linking 'f:\warp6\lib\common\cypress.vhd'. Linking 'f:\warp6\lib\common\work\cypress.vif'. Using control file 'pc_remote_sinphase.ctl'. Library 'ieee' => directory 'f:\warp6\lib\ieee\work' Linking 'f:\warp6\lib\ieee\work\stdlogic.vif'. Linking 'f:\warp6\lib\common\stdlogic\lpmpkg.vif'. Linking 'f:\warp6\lib\common\stdlogic\rtlpkg.vif'. Linking 'f:\warp6\lib\common\stdlogic\mod_cnst.vif'. Linking 'f:\warp6\lib\common\stdlogic\mod_mthu.vif'. Linking 'f:\warp6\lib\common\stdlogic\mod_mths.vif'. Linking 'f:\warp6\lib\common\stdlogic\mod_genu.vif'. Note: Using config. rule 'clk' to set attribute 'pin_numbers' on 'clk'. Note: Using config. rule 'reset' to set attribute 'pin_numbers' on 'reset'. Note: Using config. rule 'sinphase_zeros' to set attribute 'pin_numbers' on 'sinphase_zeros'. pc_remote_sinphase.vhd (line 93, col 29): Note: Substituting module 'cmp_vv_us' for '='. pc_remote_sinphase.vhd (line 97, col 32): Note: Substituting module 'add_vi_us' for '+'. pc_remote_sinphase.vhd (line 105, col 35): Note: Substituting module 'cmp_vv_us' for '='. pc_remote_sinphase.vhd (line 108, col 28): Note: Substituting module 'cmp_vv_us' for '='. pc_remote_sinphase.vhd (line 115, col 30): Note: Substituting module 'add_vi_us' for '+'. pc_remote_sinphase.vhd (line 116, col 45): Note: Substituting module 'add_vi_us' for '+'. pc_remote_sinphase.vhd (line 119, col 39): Note: Substituting module 'cmp_vv_us' for '='. pc_remote_sinphase.vhd (line 122, col 38): Note: Substituting module 'cmp_vv_us' for '='. pc_remote_sinphase.vhd (line 126, col 43): Note: Substituting module 'add_vi_us' for '+'. pc_remote_sinphase.vhd (line 127, col 43): Note: Substituting module 'add_vi_us' for '+'. Library 'ieee' => directory 'f:\warp6\lib\ieee\work' Note: Using config. rule 'clk' to set attribute 'pin_numbers' on 'clk'. Note: Using config. rule 'reset' to set attribute 'pin_numbers' on 'reset'. pc_remote_sinphase.vhd (line 250, col 31): Note: Substituting module 'cmp_vv_us' for '='. pc_remote_sinphase.vhd (line 259, col 31): Note: Substituting module 'cmp_vv_us' for '='. pc_remote_sinphase.vhd (line 264, col 34): Note: Substituting module 'add_vi_us' for '+'. pc_remote_sinphase.vhd (line 284, col 32): Note: Substituting module 'cmp_vv_us' for '='. pc_remote_sinphase.vhd (line 287, col 34): Note: Substituting module 'add_vi_us' for '+'. Library 'ieee' => directory 'f:\warp6\lib\ieee\work' Note: Using config. rule 'clk' to set attribute 'pin_numbers' on 'clk'. Note: Using config. rule 'reset' to set attribute 'pin_numbers' on 'reset'. Library 'ieee' => directory 'f:\warp6\lib\ieee\work' Note: Using config. rule 'clk' to set attribute 'pin_numbers' on 'clk'. Note: Using config. rule 'reset' to set attribute 'pin_numbers' on 'reset'. Note: Using config. rule 'sinphase_bus_request' to set attribute 'pin_numbers' on 'sinphase_bus_request'. Note: Using config. rule 'sinphase_bus_grant' to set attribute 'pin_numbers' on 'sinphase_bus_grant'. Note: Using config. rule 'sinphase_strobe' to set attribute 'pin_numbers' on 'sinphase_strobe'. Note: Using config. rule 'sinphase_zeros' to set attribute 'pin_numbers' on 'sinphase_zeros'. Note: Using config. rule 'sinphase_mids' to set attribute 'pin_numbers' on 'sinphase_mids'. Note: Using config. rule 'ao_from_pc_strobe' to set attribute 'pin_numbers' on 'ao_from_pc_strobe'. Note: Using config. rule 'ao_from_pc_ack' to set attribute 'pin_numbers' on 'ao_from_pc_ack'. Note: Using config. rule 'ao_to_pc_strobe' to set attribute 'pin_numbers' on 'ao_to_pc_strobe'. Note: Using config. rule 'ao_to_pc_ack' to set attribute 'pin_numbers' on 'ao_to_pc_ack'. Note: Using config. rule 'soft_reset' to set attribute 'pin_numbers' on 'soft_reset'. Note: Using config. rule 'da_not_clr' to set attribute 'pin_numbers' on 'da_not_clr'. Note: Using config. rule 'da_not_wr' to set attribute 'pin_numbers' on 'da_not_wr'. Note: Using config. rule 'da_not_cs' to set attribute 'pin_numbers' on 'da_not_cs'. Note: Using config. rule 'da_not_ldab' to set attribute 'pin_numbers' on 'da_not_ldab'. Note: Using config. rule 'da_not_ldcd' to set attribute 'pin_numbers' on 'da_not_ldcd'. Note: Using config. rule 'da_not_ldef' to set attribute 'pin_numbers' on 'da_not_ldef'. Note: Using config. rule 'da_not_ldgh' to set attribute 'pin_numbers' on 'da_not_ldgh'. Note: Using config. rule 'clk' to set attribute 'pin_numbers' on 'clk'. Note: Using config. rule 'reset' to set attribute 'pin_numbers' on 'reset'. Note: Using config. rule 'clk' to set attribute 'pin_numbers' on 'clk'. Note: Using config. rule 'reset' to set attribute 'pin_numbers' on 'reset'. Note: Using config. rule 'clk' to set attribute 'pin_numbers' on 'clk'. Note: Using config. rule 'reset' to set attribute 'pin_numbers' on 'reset'. Note: Using config. rule 'sinphase_zeros' to set attribute 'pin_numbers' on 'sinphase_zeros'. vhdlfe: No errors. tovif V6.0.1 IR 18: High-level synthesis Fri Aug 31 17:50:29 2001 Linking 'f:\warp6\bin\std.vhd'. Linking 'f:\warp6\lib\common\cypress.vhd'. Linking 'f:\warp6\lib\common\work\cypress.vif'. Linking '\\Dejima\ao\AO\arc_2001_1_17\vhdl\interface\interface\pc_remote\sinphase\pc_remote_sinphase.ctl'. Linking 'f:\warp6\lib\ieee\work\stdlogic.vif'. Linking 'f:\warp6\lib\common\stdlogic\lpmpkg.vif'. Linking 'f:\warp6\lib\common\stdlogic\rtlpkg.vif'. Linking 'f:\warp6\lib\common\stdlogic\mod_cnst.vif'. Linking 'f:\warp6\lib\common\stdlogic\mod_mthu.vif'. Linking 'f:\warp6\lib\common\stdlogic\mod_mths.vif'. Linking 'f:\warp6\lib\common\stdlogic\mod_genu.vif'. Linking 'f:\warp6\lib\common\stdlogic\mcompare.vif'. pc_remote_sinphase.vhd (line 345, col 6): Warning: (W460) 'digital_out(7)' unassigned in arch. 'read_from_ibus_arch' of read_from_ibus. pc_remote_sinphase.vhd (line 345, col 6): Warning: (W460) 'digital_out(6)' unassigned in arch. 'read_from_ibus_arch' of read_from_ibus. pc_remote_sinphase.vhd (line 345, col 6): Warning: (W460) 'digital_out(5)' unassigned in arch. 'read_from_ibus_arch' of read_from_ibus. pc_remote_sinphase.vhd (line 345, col 6): Warning: (W460) 'digital_out(4)' unassigned in arch. 'read_from_ibus_arch' of read_from_ibus. pc_remote_sinphase.vhd (line 345, col 6): Warning: (W460) 'digital_out(3)' unassigned in arch. 'read_from_ibus_arch' of read_from_ibus. pc_remote_sinphase.vhd (line 345, col 6): Warning: (W460) 'digital_out(2)' unassigned in arch. 'read_from_ibus_arch' of read_from_ibus. pc_remote_sinphase.vhd (line 345, col 6): Warning: (W460) 'digital_out(1)' unassigned in arch. 'read_from_ibus_arch' of read_from_ibus. pc_remote_sinphase.vhd (line 345, col 6): Warning: (W460) 'digital_out(0)' unassigned in arch. 'read_from_ibus_arch' of read_from_ibus. Note: Using config. rule 'id(15)' to set attribute 'pin_numbers' on 'id(15)'. Note: Using config. rule 'id(14)' to set attribute 'pin_numbers' on 'id(14)'. Note: Using config. rule 'id(13)' to set attribute 'pin_numbers' on 'id(13)'. Note: Using config. rule 'id(12)' to set attribute 'pin_numbers' on 'id(12)'. Note: Using config. rule 'id(11)' to set attribute 'pin_numbers' on 'id(11)'. Note: Using config. rule 'id(10)' to set attribute 'pin_numbers' on 'id(10)'. Note: Using config. rule 'id(9)' to set attribute 'pin_numbers' on 'id(9)'. Note: Using config. rule 'id(8)' to set attribute 'pin_numbers' on 'id(8)'. Note: Using config. rule 'id(7)' to set attribute 'pin_numbers' on 'id(7)'. Note: Using config. rule 'id(6)' to set attribute 'pin_numbers' on 'id(6)'. Note: Using config. rule 'id(5)' to set attribute 'pin_numbers' on 'id(5)'. Note: Using config. rule 'id(4)' to set attribute 'pin_numbers' on 'id(4)'. Note: Using config. rule 'id(3)' to set attribute 'pin_numbers' on 'id(3)'. Note: Using config. rule 'id(2)' to set attribute 'pin_numbers' on 'id(2)'. Note: Using config. rule 'id(1)' to set attribute 'pin_numbers' on 'id(1)'. Note: Using config. rule 'id(0)' to set attribute 'pin_numbers' on 'id(0)'. Note: Using config. rule 'shdn(2)' to set attribute 'pin_numbers' on 'shdn(2)'. Note: Using config. rule 'shdn(1)' to set attribute 'pin_numbers' on 'shdn(1)'. Note: Using config. rule 'shdn(0)' to set attribute 'pin_numbers' on 'shdn(0)'. Note: Using config. rule 'dad(12)' to set attribute 'pin_numbers' on 'dad(12)'. Note: Using config. rule 'dad(11)' to set attribute 'pin_numbers' on 'dad(11)'. Note: Using config. rule 'dad(10)' to set attribute 'pin_numbers' on 'dad(10)'. Note: Using config. rule 'dad(9)' to set attribute 'pin_numbers' on 'dad(9)'. Note: Using config. rule 'dad(8)' to set attribute 'pin_numbers' on 'dad(8)'. Note: Using config. rule 'dad(7)' to set attribute 'pin_numbers' on 'dad(7)'. Note: Using config. rule 'dad(6)' to set attribute 'pin_numbers' on 'dad(6)'. Note: Using config. rule 'dad(5)' to set attribute 'pin_numbers' on 'dad(5)'. Note: Using config. rule 'dad(4)' to set attribute 'pin_numbers' on 'dad(4)'. Note: Using config. rule 'dad(3)' to set attribute 'pin_numbers' on 'dad(3)'. Note: Using config. rule 'dad(2)' to set attribute 'pin_numbers' on 'dad(2)'. Note: Using config. rule 'dad(1)' to set attribute 'pin_numbers' on 'dad(1)'. Note: Using config. rule 'dad(0)' to set attribute 'pin_numbers' on 'dad(0)'. Note: Using config. rule 'daaddr(2)' to set attribute 'pin_numbers' on 'daaddr(2)'. Note: Using config. rule 'daaddr(1)' to set attribute 'pin_numbers' on 'daaddr(1)'. Note: Using config. rule 'daaddr(0)' to set attribute 'pin_numbers' on 'daaddr(0)'. Note: Using config. rule 'dio(7)' to set attribute 'pin_numbers' on 'dio(7)'. Note: Using config. rule 'dio(6)' to set attribute 'pin_numbers' on 'dio(6)'. Note: Using config. rule 'dio(5)' to set attribute 'pin_numbers' on 'dio(5)'. Note: Using config. rule 'dio(4)' to set attribute 'pin_numbers' on 'dio(4)'. Note: Using config. rule 'dio(3)' to set attribute 'pin_numbers' on 'dio(3)'. Note: Using config. rule 'dio(2)' to set attribute 'pin_numbers' on 'dio(2)'. Note: Using config. rule 'dio(1)' to set attribute 'pin_numbers' on 'dio(1)'. Note: Using config. rule 'dio(0)' to set attribute 'pin_numbers' on 'dio(0)'. pc_remote_sinphase.vhd (line 565, col 6): Warning: (W460) 'led1' unassigned in arch. 'tout_arch' of tout. pc_remote_sinphase.vhd (line 565, col 6): Warning: (W460) 'sinphase_bus_request' unassigned in arch. 'tout_arch' of tout. pc_remote_sinphase.vhd (line 565, col 6): Warning: (W460) 'dio_dir' unassigned in arch. 'tout_arch' of tout. tovif: No errors. 11 warnings. topld V6.0.1 IR 18: Synthesis and optimization Fri Aug 31 17:50:42 2001 Linking 'f:\warp6\bin\std.vhd'. Linking 'f:\warp6\lib\common\cypress.vhd'. Linking 'f:\warp6\lib\common\work\cypress.vif'. Linking '\\Dejima\ao\AO\arc_2001_1_17\vhdl\interface\interface\pc_remote\sinphase\pc_remote_sinphase.ctl'. Linking 'f:\warp6\lib\ieee\work\stdlogic.vif'. Linking 'f:\warp6\lib\common\stdlogic\lpmpkg.vif'. Linking 'f:\warp6\lib\common\stdlogic\rtlpkg.vif'. Linking 'f:\warp6\lib\common\stdlogic\mod_cnst.vif'. Linking 'f:\warp6\lib\common\stdlogic\mod_mthu.vif'. Linking 'f:\warp6\lib\common\stdlogic\mod_mths.vif'. Linking 'f:\warp6\lib\common\stdlogic\mod_genu.vif'. Linking 'f:\warp6\lib\common\stdlogic\mcompare.vif'. Note: Using config. rule 'clk' to set attribute 'pin_numbers' on 'clk'. Note: Using config. rule 'id(15)' to set attribute 'pin_numbers' on 'id(15)'. Note: Using config. rule 'id(14)' to set attribute 'pin_numbers' on 'id(14)'. Note: Using config. rule 'id(13)' to set attribute 'pin_numbers' on 'id(13)'. Note: Using config. rule 'id(12)' to set attribute 'pin_numbers' on 'id(12)'. Note: Using config. rule 'id(11)' to set attribute 'pin_numbers' on 'id(11)'. Note: Using config. rule 'id(10)' to set attribute 'pin_numbers' on 'id(10)'. Note: Using config. rule 'id(9)' to set attribute 'pin_numbers' on 'id(9)'. Note: Using config. rule 'id(8)' to set attribute 'pin_numbers' on 'id(8)'. Note: Using config. rule 'id(7)' to set attribute 'pin_numbers' on 'id(7)'. Note: Using config. rule 'id(6)' to set attribute 'pin_numbers' on 'id(6)'. Note: Using config. rule 'id(5)' to set attribute 'pin_numbers' on 'id(5)'. Note: Using config. rule 'id(4)' to set attribute 'pin_numbers' on 'id(4)'. Note: Using config. rule 'id(3)' to set attribute 'pin_numbers' on 'id(3)'. Note: Using config. rule 'id(2)' to set attribute 'pin_numbers' on 'id(2)'. Note: Using config. rule 'id(1)' to set attribute 'pin_numbers' on 'id(1)'. Note: Using config. rule 'id(0)' to set attribute 'pin_numbers' on 'id(0)'. Note: Using config. rule 'reset' to set attribute 'pin_numbers' on 'reset'. Note: Using config. rule 'sinphase_bus_request' to set attribute 'pin_numbers' on 'sinphase_bus_request'. Note: Using config. rule 'sinphase_bus_grant' to set attribute 'pin_numbers' on 'sinphase_bus_grant'. Note: Using config. rule 'sinphase_strobe' to set attribute 'pin_numbers' on 'sinphase_strobe'. Note: Using config. rule 'sinphase_zeros' to set attribute 'pin_numbers' on 'sinphase_zeros'. Note: Using config. rule 'sinphase_mids' to set attribute 'pin_numbers' on 'sinphase_mids'. Note: Using config. rule 'ao_from_pc_strobe' to set attribute 'pin_numbers' on 'ao_from_pc_strobe'. Note: Using config. rule 'ao_from_pc_ack' to set attribute 'pin_numbers' on 'ao_from_pc_ack'. Note: Using config. rule 'ao_to_pc_strobe' to set attribute 'pin_numbers' on 'ao_to_pc_strobe'. Note: Using config. rule 'ao_to_pc_ack' to set attribute 'pin_numbers' on 'ao_to_pc_ack'. Note: Using config. rule 'soft_reset' to set attribute 'pin_numbers' on 'soft_reset'. Note: Using config. rule 'shdn(2)' to set attribute 'pin_numbers' on 'shdn(2)'. Note: Using config. rule 'shdn(1)' to set attribute 'pin_numbers' on 'shdn(1)'. Note: Using config. rule 'shdn(0)' to set attribute 'pin_numbers' on 'shdn(0)'. Note: Using config. rule 'da_not_clr' to set attribute 'pin_numbers' on 'da_not_clr'. Note: Using config. rule 'da_not_wr' to set attribute 'pin_numbers' on 'da_not_wr'. Note: Using config. rule 'da_not_cs' to set attribute 'pin_numbers' on 'da_not_cs'. Note: Using config. rule 'da_not_ldab' to set attribute 'pin_numbers' on 'da_not_ldab'. Note: Using config. rule 'da_not_ldcd' to set attribute 'pin_numbers' on 'da_not_ldcd'. Note: Using config. rule 'da_not_ldef' to set attribute 'pin_numbers' on 'da_not_ldef'. Note: Using config. rule 'da_not_ldgh' to set attribute 'pin_numbers' on 'da_not_ldgh'. Note: Using config. rule 'dad(12)' to set attribute 'pin_numbers' on 'dad(12)'. Note: Using config. rule 'dad(11)' to set attribute 'pin_numbers' on 'dad(11)'. Note: Using config. rule 'dad(10)' to set attribute 'pin_numbers' on 'dad(10)'. Note: Using config. rule 'dad(9)' to set attribute 'pin_numbers' on 'dad(9)'. Note: Using config. rule 'dad(8)' to set attribute 'pin_numbers' on 'dad(8)'. Note: Using config. rule 'dad(7)' to set attribute 'pin_numbers' on 'dad(7)'. Note: Using config. rule 'dad(6)' to set attribute 'pin_numbers' on 'dad(6)'. Note: Using config. rule 'dad(5)' to set attribute 'pin_numbers' on 'dad(5)'. Note: Using config. rule 'dad(4)' to set attribute 'pin_numbers' on 'dad(4)'. Note: Using config. rule 'dad(3)' to set attribute 'pin_numbers' on 'dad(3)'. Note: Using config. rule 'dad(2)' to set attribute 'pin_numbers' on 'dad(2)'. Note: Using config. rule 'dad(1)' to set attribute 'pin_numbers' on 'dad(1)'. Note: Using config. rule 'dad(0)' to set attribute 'pin_numbers' on 'dad(0)'. Note: Using config. rule 'daaddr(2)' to set attribute 'pin_numbers' on 'daaddr(2)'. Note: Using config. rule 'daaddr(1)' to set attribute 'pin_numbers' on 'daaddr(1)'. Note: Using config. rule 'daaddr(0)' to set attribute 'pin_numbers' on 'daaddr(0)'. Note: Using config. rule 'dio(7)' to set attribute 'pin_numbers' on 'dio(7)'. Note: Using config. rule 'dio(6)' to set attribute 'pin_numbers' on 'dio(6)'. Note: Using config. rule 'dio(5)' to set attribute 'pin_numbers' on 'dio(5)'. Note: Using config. rule 'dio(4)' to set attribute 'pin_numbers' on 'dio(4)'. Note: Using config. rule 'dio(3)' to set attribute 'pin_numbers' on 'dio(3)'. Note: Using config. rule 'dio(2)' to set attribute 'pin_numbers' on 'dio(2)'. Note: Using config. rule 'dio(1)' to set attribute 'pin_numbers' on 'dio(1)'. Note: Using config. rule 'dio(0)' to set attribute 'pin_numbers' on 'dio(0)'. Linking 'f:\warp6\lib\lc370\stdlogic\c370.vif'. State variable 'dac_state' is represented by a Bit_vector (0 to 2). State encoding (sequential) for 'dac_state' is: idle := b"000"; pc_ack_st := b"001"; sp_ack_st := b"010"; sp_shift := b"011"; write_dac := b"100"; State variable 'il_read_state' is represented by a Bit_vector (0 to 2). State encoding (sequential) for 'il_read_state' is: idle := b"000"; am_i_addressed := b"001"; il_hs_for_address := b"010"; il_hs_for_data := b"011"; il_use_ctrl_data := b"100"; internal_ack1 := b"101"; State variable 'kdac' is represented by a Bit_vector (0 to 1). State encoding (sequential) for 'kdac' is: kd_idle := b"00"; kd_ack := b"01"; kd_guard := b"10"; Note: Using config. rule 'clk' to set attribute 'pin_numbers' on 'clk'. Note: Using config. rule 'clk' to set attribute 'pin_numbers' on 'clk'. ---------------------------------------------------------- Detecting unused logic. ---------------------------------------------------------- User names dac_data_from_pc_14 dac_data_from_pc_13 Deleted 2 User equations/components. Deleted 202 Synthesized equations/components. ------------------------------------------------------ Alias Detection ------------------------------------------------------ ------------------------------------------------------ Aliased 1 equations, 157 wires. ------------------------------------------------------ ---------------------------------------------------------- Circuit simplification ---------------------------------------------------------- Note: Virtual signal \spg:MODULE_3:g1:a0:gx:u0:eq_5\ with ( cost: 128 or cost_inv: -1) > 120 or with size: 64 > 124 has been made a (soft) node. Note: Virtual signal \spg:MODULE_7:g1:a0:gx:u0:eq_5\ with ( cost: 128 or cost_inv: -1) > 120 or with size: 64 > 124 has been made a (soft) node. Note: Virtual signal \spg:MODULE_8:g1:a0:gx:u0:eq_5\ with ( cost: 128 or cost_inv: -1) > 120 or with size: 64 > 124 has been made a (soft) node. Note: Virtual signal \spg:cmp_vv_us_MODGEN_4\ with ( cost: 768 or cost_inv: 3) > 120 or with size: 1 > 124 has been made a (soft) node. Note: Virtual signal \dacwr:cmp_vv_us_MODGEN_10\ with ( cost: 136 or cost_inv: 24) > 120 or with size: 8 > 124 has been made a (soft) node. Note: Virtual signal \spg:cmp_vv_us_MODGEN_1\ with ( cost: 192 or cost_inv: 64) > 120 or with size: 16 > 124 has been made a (soft) node. Note: Virtual signal \spg:cmp_vv_us_MODGEN_3\ with ( cost: 132 or cost_inv: 12) > 120 or with size: 4 > 124 has been made a (soft) node. Note: Virtual signal \spg:cmp_vv_us_MODGEN_8\ with ( cost: 1073741824 or cost_inv: 1073741824) > 120 or with size: 32 > 124 has been made a (soft) node. ---------------------------------------------------------- Circuit simplification results: Expanded 147 signals. Turned 8 signals into soft nodes. Maximum expansion cost was set at 4. ---------------------------------------------------------- ------------------------------------------------------ Alias Detection ------------------------------------------------------ ------------------------------------------------------ Aliased 0 equations, 0 wires. ------------------------------------------------------ Created 1036 PLD nodes. topld: No errors. ---------------------------------------------------------------------------- PLD Optimizer Software: DSGNOPT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 DESIGN HEADER INFORMATION (17:51:16) Input File(s): pc_remote_sinphase.pla Device : cy37256p160 Package : cy37256p160-125ac ReportFile : pc_remote_sinphase.rpt Program Controls: COMMAND LANGUAGE_VHDL COMMAND UserCode 0000000000000000 COMMAND PROPERTY BUS_HOLD ENABLE Signal Requests: GROUP DT-OPT ALL GROUP USEPOL ALL GROUP FACTOR ALL GROUP FAST_SLEW ALL GROUP SOFT \spg:MODULE_8:g1:a0:gx:u0:eq_5\ \spg:MODULE_7:g1:a0:gx:u0:eq_5\ \spg:MODULE_3:g1:a0:gx:u0:eq_5\ \spg:cmp_vv_us_MODGEN_8\ \spg:cmp_vv_us_MODGEN_4\ \spg:cmp_vv_us_MODGEN_3\ \spg:cmp_vv_us_MODGEN_1\ \dacwr:cmp_vv_us_MODGEN_10\ Completed Successfully ---------------------------------------------------------------------------- PLD Optimizer Software: DSGNOPT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 OPTIMIZATION OPTIONS (17:51:16) Messages: Information: Process virtual '\spg:MODULE_8:g1:a0:gx:u0:eq_5\' ... converted to NODE. ... converted to NODE. ... converted to NODE. ... converted to NODE. ... converted to NODE. ... converted to NODE. ... converted to NODE. ... converted to NODE. Information: Process virtual '\spg:MODULE_8:g1:a0:gx:u0:eqi_0\' ... expanded. Information: Process virtual '\spg:MODULE_7:g1:a0:gx:u0:eqi_0\' ... expanded. Information: Process virtual '\spg:MODULE_3:g1:a0:gx:u0:eqi_0\' ... expanded. Information: Process virtual '\spg:kdacSBV_0\\D\' ... expanded. Information: Process virtual '\spg:current_phase_0\\D\' ... expanded. Information: Process virtual '\spg:current_phase_1\\D\' ... expanded. Information: Process virtual '\spg:current_phase_2\\D\' ... expanded. Information: Process virtual '\spg:current_phase_3\\D\' ... expanded. Information: Process virtual '\spg:current_phase_4\\D\' ... expanded. Information: Process virtual '\spg:current_phase_5\\D\' ... expanded. Information: Process virtual '\spg:current_phase_6\\D\' ... expanded. Information: Process virtual '\spg:current_phase_7\\D\' ... expanded. Information: Process virtual '\spg:current_phase_8\\D\' ... expanded. Information: Process virtual '\spg:current_phase_9\\D\' ... expanded. Information: Process virtual '\spg:current_phase_10\\D\' ... expanded. Information: Process virtual '\spg:current_phase_11\\D\' ... expanded. Information: Process virtual '\spg:current_phase_12\\D\' ... expanded. Information: Process virtual '\spg:current_count_0\\D\' ... expanded. Information: Process virtual '\spg:current_count_1\\D\' ... expanded. Information: Process virtual '\spg:current_count_2\\D\' ... expanded. Information: Process virtual '\spg:current_count_3\\D\' ... expanded. Information: Process virtual '\spg:current_count_4\\D\' ... expanded. Information: Process virtual '\spg:current_count_5\\D\' ... expanded. Information: Process virtual '\spg:current_count_6\\D\' ... expanded. Information: Process virtual '\spg:current_count_7\\D\' ... expanded. Information: Process virtual '\spg:current_count_8\\D\' ... expanded. Information: Process virtual '\spg:current_count_9\\D\' ... expanded. Information: Process virtual '\spg:precount_0\\D\' ... expanded. Information: Process virtual '\spg:precount_1\\D\' ... expanded. Information: Process virtual '\spg:precount_2\\D\' ... expanded. Information: Process virtual '\spg:precount_3\\D\' ... expanded. Information: Process virtual '\spg:iclk\\D\' ... expanded. Information: Process virtual '\spg:sample_0\\D\' ... expanded. Information: Process virtual '\spg:sample_1\\D\' ... expanded. Information: Process virtual '\spg:sample_2\\D\' ... expanded. Information: Process virtual '\rio:this_is_a_ctrl_transaction\\D\' ... expanded. Information: Process virtual '\rio:il_read_stateSBV_2\\D\' ... expanded. Information: Process virtual '\rio:il_read_stateSBV_1\\D\' ... expanded. Information: Process virtual '\rio:il_read_stateSBV_0\\D\' ... expanded. Information: Process virtual 'predev_0D' ... expanded. Information: Process virtual 'predev_1D' ... expanded. Information: Process virtual 'predev_2D' ... expanded. Information: Process virtual 'predev_3D' ... expanded. Information: Process virtual 'val7_0D' ... expanded. Information: Process virtual 'val7_1D' ... expanded. Information: Process virtual 'val7_2D' ... expanded. Information: Process virtual 'val7_3D' ... expanded. Information: Process virtual 'val7_4D' ... expanded. Information: Process virtual 'val7_5D' ... expanded. Information: Process virtual 'val7_6D' ... expanded. Information: Process virtual 'val7_7D' ... expanded. Information: Process virtual 'val6_0D' ... expanded. Information: Process virtual 'val6_1D' ... expanded. Information: Process virtual 'val6_2D' ... expanded. Information: Process virtual 'val6_3D' ... expanded. Information: Process virtual 'val6_4D' ... expanded. Information: Process virtual 'val6_5D' ... expanded. Information: Process virtual 'val6_6D' ... expanded. Information: Process virtual 'val6_7D' ... expanded. Information: Process virtual 'val5_0D' ... expanded. Information: Process virtual 'val5_1D' ... expanded. Information: Process virtual 'val5_2D' ... expanded. Information: Process virtual 'val5_3D' ... expanded. Information: Process virtual 'val5_4D' ... expanded. Information: Process virtual 'val5_5D' ... expanded. Information: Process virtual 'val5_6D' ... expanded. Information: Process virtual 'val5_7D' ... expanded. Information: Process virtual 'val4_0D' ... expanded. Information: Process virtual 'val4_1D' ... expanded. Information: Process virtual 'val4_2D' ... expanded. Information: Process virtual 'val4_3D' ... expanded. Information: Process virtual 'val4_4D' ... expanded. Information: Process virtual 'val4_5D' ... expanded. Information: Process virtual 'val4_6D' ... expanded. Information: Process virtual 'val4_7D' ... expanded. Information: Process virtual 'val3_0D' ... expanded. Information: Process virtual 'val3_1D' ... expanded. Information: Process virtual 'val3_2D' ... expanded. Information: Process virtual 'val3_3D' ... expanded. Information: Process virtual 'val3_4D' ... expanded. Information: Process virtual 'val3_5D' ... expanded. Information: Process virtual 'val3_6D' ... expanded. Information: Process virtual 'val3_7D' ... expanded. Information: Process virtual 'val2_0D' ... expanded. Information: Process virtual 'val2_1D' ... expanded. Information: Process virtual 'val2_2D' ... expanded. Information: Process virtual 'val2_3D' ... expanded. Information: Process virtual 'val2_4D' ... expanded. Information: Process virtual 'val2_5D' ... expanded. Information: Process virtual 'val2_6D' ... expanded. Information: Process virtual 'val2_7D' ... expanded. Information: Process virtual 'val1_0D' ... expanded. Information: Process virtual 'val1_1D' ... expanded. Information: Process virtual 'val1_2D' ... expanded. Information: Process virtual 'val1_3D' ... expanded. Information: Process virtual 'val1_4D' ... expanded. Information: Process virtual 'val1_5D' ... expanded. Information: Process virtual 'val1_6D' ... expanded. Information: Process virtual 'val1_7D' ... expanded. Information: Process virtual 'val0_0D' ... expanded. Information: Process virtual 'val0_1D' ... expanded. Information: Process virtual 'val0_2D' ... expanded. Information: Process virtual 'val0_3D' ... expanded. Information: Process virtual 'val0_4D' ... expanded. Information: Process virtual 'val0_5D' ... expanded. Information: Process virtual 'val0_6D' ... expanded. Information: Process virtual 'val0_7D' ... expanded. Information: Process virtual 'steplen_0D' ... expanded. Information: Process virtual 'steplen_1D' ... expanded. Information: Process virtual 'steplen_2D' ... expanded. Information: Process virtual 'steplen_3D' ... expanded. Information: Process virtual 'steplen_4D' ... expanded. Information: Process virtual 'steplen_5D' ... expanded. Information: Process virtual 'steplen_6D' ... expanded. Information: Process virtual 'steplen_7D' ... expanded. Information: Process virtual 'steplen_8D' ... expanded. Information: Process virtual 'steplen_9D' ... expanded. Information: Process virtual 'phase2_0D' ... expanded. Information: Process virtual 'phase2_1D' ... expanded. Information: Process virtual 'phase2_2D' ... expanded. Information: Process virtual 'phase2_3D' ... expanded. Information: Process virtual 'phase2_4D' ... expanded. Information: Process virtual 'phase2_5D' ... expanded. Information: Process virtual 'phase2_6D' ... expanded. Information: Process virtual 'phase2_7D' ... expanded. Information: Process virtual 'phase2_8D' ... expanded. Information: Process virtual 'phase2_9D' ... expanded. Information: Process virtual 'phase2_10D' ... expanded. Information: Process virtual 'phase2_11D' ... expanded. Information: Process virtual 'phase2_12D' ... expanded. Information: Process virtual 'phase1_0D' ... expanded. Information: Process virtual 'phase1_1D' ... expanded. Information: Process virtual 'phase1_2D' ... expanded. Information: Process virtual 'phase1_3D' ... expanded. Information: Process virtual 'phase1_4D' ... expanded. Information: Process virtual 'phase1_5D' ... expanded. Information: Process virtual 'phase1_6D' ... expanded. Information: Process virtual 'phase1_7D' ... expanded. Information: Process virtual 'phase1_8D' ... expanded. Information: Process virtual 'phase1_9D' ... expanded. Information: Process virtual 'phase1_10D' ... expanded. Information: Process virtual 'phase1_11D' ... expanded. Information: Process virtual 'phase1_12D' ... expanded. Information: Process virtual 'dac_data_from_pc_15D' ... expanded. Information: Process virtual 'this_chip_selectedD' ... expanded. Information: Process virtual '\dacwr:dac_hold_0\\D\' ... expanded. Information: Process virtual '\dacwr:dac_hold_1\\D\' ... expanded. Information: Process virtual '\dacwr:dac_hold_2\\D\' ... expanded. Information: Process virtual '\dacwr:dac_hold_3\\D\' ... expanded. Information: Process virtual '\dacwr:dac_hold_4\\D\' ... expanded. Information: Process virtual '\dacwr:dac_hold_5\\D\' ... expanded. Information: Process virtual '\dacwr:dac_hold_6\\D\' ... expanded. Information: Process virtual '\dacwr:dac_hold_7\\D\' ... expanded. Information: Process virtual '\dacwr:dac_hold_8\\D\' ... expanded. Information: Process virtual '\dacwr:dac_hold_9\\D\' ... expanded. Information: Process virtual '\dacwr:dac_hold_10\\D\' ... expanded. Information: Process virtual '\dacwr:dac_hold_11\\D\' ... expanded. Information: Process virtual '\dacwr:dac_hold_12\\D\' ... expanded. Information: Process virtual '\dacwr:timeout_0\\D\' ... expanded. Information: Process virtual '\dacwr:timeout_1\\D\' ... expanded. Information: Process virtual '\dacwr:timeout_2\\D\' ... expanded. Information: Process virtual '\dacwr:dac_stateSBV_2\\D\' ... expanded. Information: Process virtual '\dacwr:dac_stateSBV_1\\D\' ... expanded. Information: Process virtual '\dacwr:dac_stateSBV_0\\D\' ... expanded. Information: Process virtual '\dacwr:dac_addr_copy_0\\D\' ... expanded. Information: Process virtual '\dacwr:dac_addr_copy_1\\D\' ... expanded. Information: Process virtual '\dacwr:dac_addr_copy_2\\D\' ... expanded. Information: Process virtual 'shift_0D' ... expanded. Information: Process virtual 'shift_1D' ... expanded. Information: Process virtual 'shift_2D' ... expanded. Information: Process virtual 'address_from_pc_0D' ... expanded. Information: Process virtual 'address_from_pc_1D' ... expanded. Information: Process virtual 'address_from_pc_2D' ... expanded. Information: Process virtual 'address_from_pc_3D' ... expanded. Information: Process virtual 'dac_data_from_pc_0D' ... expanded. Information: Process virtual 'dac_data_from_pc_1D' ... expanded. Information: Process virtual 'dac_data_from_pc_2D' ... expanded. Information: Process virtual 'dac_data_from_pc_3D' ... expanded. Information: Process virtual 'dac_data_from_pc_4D' ... expanded. Information: Process virtual 'dac_data_from_pc_5D' ... expanded. Information: Process virtual 'dac_data_from_pc_6D' ... expanded. Information: Process virtual 'dac_data_from_pc_7D' ... expanded. Information: Process virtual 'dac_data_from_pc_8D' ... expanded. Information: Process virtual 'dac_data_from_pc_9D' ... expanded. Information: Process virtual 'dac_data_from_pc_10D' ... expanded. Information: Process virtual 'dac_data_from_pc_11D' ... expanded. Information: Process virtual 'dac_data_from_pc_12D' ... expanded. Information: Process virtual 'to_dac_from_pc_ackD' ... expanded. Information: Process virtual 'to_dac_from_pc_reqD' ... expanded. Information: Process virtual 'sp_ackD' ... expanded. Information: Process virtual 'sp_reqD' ... expanded. Information: Process virtual '\dad(0)D\' ... expanded. Information: Process virtual '\dad(1)D\' ... expanded. Information: Process virtual '\dad(2)D\' ... expanded. Information: Process virtual '\dad(3)D\' ... expanded. Information: Process virtual '\dad(4)D\' ... expanded. Information: Process virtual '\dad(5)D\' ... expanded. Information: Process virtual '\dad(6)D\' ... expanded. Information: Process virtual '\dad(7)D\' ... expanded. Information: Process virtual '\dad(8)D\' ... expanded. Information: Process virtual '\dad(9)D\' ... expanded. Information: Process virtual '\dad(10)D\' ... expanded. Information: Process virtual '\dad(11)D\' ... expanded. Information: Process virtual '\dad(12)D\' ... expanded. Information: Process virtual 'sinphase_zerosD' ... expanded. Information: Process virtual '\spg:MODULE_8:g1:a0:gx:u0:eq_7\' ... expanded. Information: Process virtual '\spg:MODULE_7:g1:a0:gx:u0:eq_7\' ... expanded. Information: Process virtual '\spg:MODULE_3:g1:a0:gx:u0:eq_7\' ... expanded. Information: Process virtual '\spg:kdacSBV_0\' ... converted to NODE. Information: Process virtual '\spg:current_phase_0\' ... converted to NODE. Information: Process virtual '\spg:current_phase_1\' ... converted to NODE. Information: Process virtual '\spg:current_phase_2\' ... converted to NODE. Information: Process virtual '\spg:current_phase_3\' ... converted to NODE. Information: Process virtual '\spg:current_phase_4\' ... converted to NODE. Information: Process virtual '\spg:current_phase_5\' ... converted to NODE. Information: Process virtual '\spg:current_phase_6\' ... converted to NODE. Information: Process virtual '\spg:current_phase_7\' ... converted to NODE. Information: Process virtual '\spg:current_phase_8\' ... converted to NODE. Information: Process virtual '\spg:current_phase_9\' ... converted to NODE. Information: Process virtual '\spg:current_phase_10\' ... converted to NODE. Information: Process virtual '\spg:current_phase_11\' ... converted to NODE. Information: Process virtual '\spg:current_phase_12\' ... converted to NODE. Information: Process virtual '\spg:current_count_0\' ... converted to NODE. Information: Process virtual '\spg:current_count_1\' ... converted to NODE. Information: Process virtual '\spg:current_count_2\' ... converted to NODE. Information: Process virtual '\spg:current_count_3\' ... converted to NODE. Information: Process virtual '\spg:current_count_4\' ... converted to NODE. Information: Process virtual '\spg:current_count_5\' ... converted to NODE. Information: Process virtual '\spg:current_count_6\' ... converted to NODE. Information: Process virtual '\spg:current_count_7\' ... converted to NODE. Information: Process virtual '\spg:current_count_8\' ... converted to NODE. Information: Process virtual '\spg:current_count_9\' ... converted to NODE. Information: Process virtual '\spg:kick_dac\' ... converted to NODE. Information: Process virtual '\spg:precount_0\' ... converted to NODE. Information: Process virtual '\spg:precount_1\' ... converted to NODE. Information: Process virtual '\spg:precount_2\' ... converted to NODE. Information: Process virtual '\spg:precount_3\' ... converted to NODE. Information: Process virtual '\spg:iclk\' ... converted to NODE. Information: Process virtual '\spg:sample_0\' ... converted to NODE. Information: Process virtual '\spg:sample_1\' ... converted to NODE. Information: Process virtual '\spg:sample_2\' ... converted to NODE. Information: Process virtual '\rio:this_is_a_ctrl_transaction\' ... converted to NODE. Information: Process virtual '\rio:il_read_stateSBV_2\' ... converted to NODE. Information: Process virtual '\rio:il_read_stateSBV_1\' ... converted to NODE. Information: Process virtual '\rio:il_read_stateSBV_0\' ... converted to NODE. Information: Process virtual 'predev_0' ... converted to NODE. Information: Process virtual 'predev_1' ... converted to NODE. Information: Process virtual 'predev_2' ... converted to NODE. Information: Process virtual 'predev_3' ... converted to NODE. Information: Process virtual 'val7_0' ... converted to NODE. Information: Process virtual 'val7_1' ... converted to NODE. Information: Process virtual 'val7_2' ... converted to NODE. Information: Process virtual 'val7_3' ... converted to NODE. Information: Process virtual 'val7_4' ... converted to NODE. Information: Process virtual 'val7_5' ... converted to NODE. Information: Process virtual 'val7_6' ... converted to NODE. Information: Process virtual 'val7_7' ... converted to NODE. Information: Process virtual 'val6_0' ... converted to NODE. Information: Process virtual 'val6_1' ... converted to NODE. Information: Process virtual 'val6_2' ... converted to NODE. Information: Process virtual 'val6_3' ... converted to NODE. Information: Process virtual 'val6_4' ... converted to NODE. Information: Process virtual 'val6_5' ... converted to NODE. Information: Process virtual 'val6_6' ... converted to NODE. Information: Process virtual 'val6_7' ... converted to NODE. Information: Process virtual 'val5_0' ... converted to NODE. Information: Process virtual 'val5_1' ... converted to NODE. Information: Process virtual 'val5_2' ... converted to NODE. Information: Process virtual 'val5_3' ... converted to NODE. Information: Process virtual 'val5_4' ... converted to NODE. Information: Process virtual 'val5_5' ... converted to NODE. Information: Process virtual 'val5_6' ... converted to NODE. Information: Process virtual 'val5_7' ... converted to NODE. Information: Process virtual 'val4_0' ... converted to NODE. Information: Process virtual 'val4_1' ... converted to NODE. Information: Process virtual 'val4_2' ... converted to NODE. Information: Process virtual 'val4_3' ... converted to NODE. Information: Process virtual 'val4_4' ... converted to NODE. Information: Process virtual 'val4_5' ... converted to NODE. Information: Process virtual 'val4_6' ... converted to NODE. Information: Process virtual 'val4_7' ... converted to NODE. Information: Process virtual 'val3_0' ... converted to NODE. Information: Process virtual 'val3_1' ... converted to NODE. Information: Process virtual 'val3_2' ... converted to NODE. Information: Process virtual 'val3_3' ... converted to NODE. Information: Process virtual 'val3_4' ... converted to NODE. Information: Process virtual 'val3_5' ... converted to NODE. Information: Process virtual 'val3_6' ... converted to NODE. Information: Process virtual 'val3_7' ... converted to NODE. Information: Process virtual 'val2_0' ... converted to NODE. Information: Process virtual 'val2_1' ... converted to NODE. Information: Process virtual 'val2_2' ... converted to NODE. Information: Process virtual 'val2_3' ... converted to NODE. Information: Process virtual 'val2_4' ... converted to NODE. Information: Process virtual 'val2_5' ... converted to NODE. Information: Process virtual 'val2_6' ... converted to NODE. Information: Process virtual 'val2_7' ... converted to NODE. Information: Process virtual 'val1_0' ... converted to NODE. Information: Process virtual 'val1_1' ... converted to NODE. Information: Process virtual 'val1_2' ... converted to NODE. Information: Process virtual 'val1_3' ... converted to NODE. Information: Process virtual 'val1_4' ... converted to NODE. Information: Process virtual 'val1_5' ... converted to NODE. Information: Process virtual 'val1_6' ... converted to NODE. Information: Process virtual 'val1_7' ... converted to NODE. Information: Process virtual 'val0_0' ... converted to NODE. Information: Process virtual 'val0_1' ... converted to NODE. Information: Process virtual 'val0_2' ... converted to NODE. Information: Process virtual 'val0_3' ... converted to NODE. Information: Process virtual 'val0_4' ... converted to NODE. Information: Process virtual 'val0_5' ... converted to NODE. Information: Process virtual 'val0_6' ... converted to NODE. Information: Process virtual 'val0_7' ... converted to NODE. Information: Process virtual 'steplen_0' ... converted to NODE. Information: Process virtual 'steplen_1' ... converted to NODE. Information: Process virtual 'steplen_2' ... converted to NODE. Information: Process virtual 'steplen_3' ... converted to NODE. Information: Process virtual 'steplen_4' ... converted to NODE. Information: Process virtual 'steplen_5' ... converted to NODE. Information: Process virtual 'steplen_6' ... converted to NODE. Information: Process virtual 'steplen_7' ... converted to NODE. Information: Process virtual 'steplen_8' ... converted to NODE. Information: Process virtual 'steplen_9' ... converted to NODE. Information: Process virtual 'phase2_0' ... converted to NODE. Information: Process virtual 'phase2_1' ... converted to NODE. Information: Process virtual 'phase2_2' ... converted to NODE. Information: Process virtual 'phase2_3' ... converted to NODE. Information: Process virtual 'phase2_4' ... converted to NODE. Information: Process virtual 'phase2_5' ... converted to NODE. Information: Process virtual 'phase2_6' ... converted to NODE. Information: Process virtual 'phase2_7' ... converted to NODE. Information: Process virtual 'phase2_8' ... converted to NODE. Information: Process virtual 'phase2_9' ... converted to NODE. Information: Process virtual 'phase2_10' ... converted to NODE. Information: Process virtual 'phase2_11' ... converted to NODE. Information: Process virtual 'phase2_12' ... converted to NODE. Information: Process virtual 'phase1_0' ... converted to NODE. Information: Process virtual 'phase1_1' ... converted to NODE. Information: Process virtual 'phase1_2' ... converted to NODE. Information: Process virtual 'phase1_3' ... converted to NODE. Information: Process virtual 'phase1_4' ... converted to NODE. Information: Process virtual 'phase1_5' ... converted to NODE. Information: Process virtual 'phase1_6' ... converted to NODE. Information: Process virtual 'phase1_7' ... converted to NODE. Information: Process virtual 'phase1_8' ... converted to NODE. Information: Process virtual 'phase1_9' ... converted to NODE. Information: Process virtual 'phase1_10' ... converted to NODE. Information: Process virtual 'phase1_11' ... converted to NODE. Information: Process virtual 'phase1_12' ... converted to NODE. Information: Process virtual 'dac_data_from_pc_15' ... converted to NODE. Information: Process virtual 'this_chip_selected' ... converted to NODE. Information: Process virtual '\dacwr:dac_hold_0\' ... converted to NODE. Information: Process virtual '\dacwr:dac_hold_1\' ... converted to NODE. Information: Process virtual '\dacwr:dac_hold_2\' ... converted to NODE. Information: Process virtual '\dacwr:dac_hold_3\' ... converted to NODE. Information: Process virtual '\dacwr:dac_hold_4\' ... converted to NODE. Information: Process virtual '\dacwr:dac_hold_5\' ... converted to NODE. Information: Process virtual '\dacwr:dac_hold_6\' ... converted to NODE. Information: Process virtual '\dacwr:dac_hold_7\' ... converted to NODE. Information: Process virtual '\dacwr:dac_hold_8\' ... converted to NODE. Information: Process virtual '\dacwr:dac_hold_9\' ... converted to NODE. Information: Process virtual '\dacwr:dac_hold_10\' ... converted to NODE. Information: Process virtual '\dacwr:dac_hold_11\' ... converted to NODE. Information: Process virtual '\dacwr:dac_hold_12\' ... converted to NODE. Information: Process virtual '\dacwr:timeout_0\' ... converted to NODE. Information: Process virtual '\dacwr:timeout_1\' ... converted to NODE. Information: Process virtual '\dacwr:timeout_2\' ... converted to NODE. Information: Process virtual '\dacwr:dac_stateSBV_2\' ... converted to NODE. Information: Process virtual '\dacwr:dac_stateSBV_1\' ... converted to NODE. Information: Process virtual '\dacwr:dac_stateSBV_0\' ... converted to NODE. Information: Process virtual '\dacwr:dac_addr_copy_0\' ... expanded. Information: Process virtual '\dacwr:dac_addr_copy_1\' ... expanded. Information: Process virtual '\dacwr:dac_addr_copy_2\' ... expanded. Information: Process virtual 'shift_0' ... converted to NODE. Information: Process virtual 'shift_1' ... converted to NODE. Information: Process virtual 'shift_2' ... converted to NODE. Information: Process virtual 'address_from_pc_0' ... converted to NODE. Information: Process virtual 'address_from_pc_1' ... converted to NODE. Information: Process virtual 'address_from_pc_2' ... converted to NODE. Information: Process virtual 'address_from_pc_3' ... converted to NODE. Information: Process virtual 'dac_data_from_pc_0' ... converted to NODE. Information: Process virtual 'dac_data_from_pc_1' ... converted to NODE. Information: Process virtual 'dac_data_from_pc_2' ... converted to NODE. Information: Process virtual 'dac_data_from_pc_3' ... converted to NODE. Information: Process virtual 'dac_data_from_pc_4' ... converted to NODE. Information: Process virtual 'dac_data_from_pc_5' ... converted to NODE. Information: Process virtual 'dac_data_from_pc_6' ... converted to NODE. Information: Process virtual 'dac_data_from_pc_7' ... converted to NODE. Information: Process virtual 'dac_data_from_pc_8' ... converted to NODE. Information: Process virtual 'dac_data_from_pc_9' ... converted to NODE. Information: Process virtual 'dac_data_from_pc_10' ... converted to NODE. Information: Process virtual 'dac_data_from_pc_11' ... converted to NODE. Information: Process virtual 'dac_data_from_pc_12' ... converted to NODE. Information: Process virtual 'to_dac_from_pc_ack' ... converted to NODE. Information: Process virtual 'to_dac_from_pc_req' ... converted to NODE. Information: Process virtual 'sp_ack' ... converted to NODE. Information: Process virtual 'sp_req' ... converted to NODE. Information: Generating both D & T register equations for signal ao_from_pc_ack.D[54] Information: Expanding XOR equation found on signal ao_from_pc_ack.T[54] Information: Generating both D & T register equations for signal sinphase_zeros.D[79] Information: Expanding XOR equation found on signal sinphase_zeros.T[79] Information: Generating both D & T register equations for signal dad(0).D[82] Information: Expanding XOR equation found on signal dad(0).T[82] Information: Generating both D & T register equations for signal dad(1).D[83] Information: Expanding XOR equation found on signal dad(1).T[83] Information: Generating both D & T register equations for signal dad(2).D[84] Information: Expanding XOR equation found on signal dad(2).T[84] Information: Generating both D & T register equations for signal dad(3).D[85] Information: Expanding XOR equation found on signal dad(3).T[85] Information: Generating both D & T register equations for signal dad(4).D[86] Information: Expanding XOR equation found on signal dad(4).T[86] Information: Generating both D & T register equations for signal dad(5).D[87] Information: Expanding XOR equation found on signal dad(5).T[87] Information: Generating both D & T register equations for signal dad(6).D[88] Information: Expanding XOR equation found on signal dad(6).T[88] Information: Generating both D & T register equations for signal dad(7).D[89] Information: Expanding XOR equation found on signal dad(7).T[89] Information: Generating both D & T register equations for signal dad(8).D[91] Information: Expanding XOR equation found on signal dad(8).T[91] Information: Generating both D & T register equations for signal dad(9).D[92] Information: Expanding XOR equation found on signal dad(9).T[92] Information: Generating both D & T register equations for signal dad(10).D[93] Information: Expanding XOR equation found on signal dad(10).T[93] Information: Generating both D & T register equations for signal dad(11).D[94] Information: Expanding XOR equation found on signal dad(11).T[94] Information: Generating both D & T register equations for signal dad(12).D[95] Information: Expanding XOR equation found on signal dad(12).T[95] Information: Generating both D & T register equations for signal daaddr(0).D[96] Information: Expanding XOR equation found on signal daaddr(0).T[96] Information: Generating both D & T register equations for signal daaddr(1).D[97] Information: Expanding XOR equation found on signal daaddr(1).T[97] Information: Generating both D & T register equations for signal daaddr(2).D[98] Information: Expanding XOR equation found on signal daaddr(2).T[98] Information: Generating both D & T register equations for signal da_not_wr.D[103] Information: Expanding XOR equation found on signal da_not_wr.T[103] Information: Generating both D & T register equations for signal da_not_cs.D[104] Information: Generating both D & T register equations for signal da_not_clr.D[112] Information: Generating both D & T register equations for signal \spg:kdacSBV_0\.D Information: Expanding XOR equation found on signal \spg:kdacSBV_0\.T Information: Generating both D & T register equations for signal \spg:current_phase_0\.D Information: Expanding XOR equation found on signal \spg:current_phase_0\.T Information: Generating both D & T register equations for signal \spg:current_phase_1\.D Information: Expanding XOR equation found on signal \spg:current_phase_1\.T Information: Generating both D & T register equations for signal \spg:current_phase_2\.D Information: Expanding XOR equation found on signal \spg:current_phase_2\.T Information: Generating both D & T register equations for signal \spg:current_phase_3\.D Information: Expanding XOR equation found on signal \spg:current_phase_3\.T Information: Generating both D & T register equations for signal \spg:current_phase_4\.D Information: Expanding XOR equation found on signal \spg:current_phase_4\.T Information: Generating both D & T register equations for signal \spg:current_phase_5\.D Information: Expanding XOR equation found on signal \spg:current_phase_5\.T Information: Generating both D & T register equations for signal \spg:current_phase_6\.D Information: Expanding XOR equation found on signal \spg:current_phase_6\.T Information: Generating both D & T register equations for signal \spg:current_phase_7\.D Information: Expanding XOR equation found on signal \spg:current_phase_7\.T Information: Generating both D & T register equations for signal \spg:current_phase_8\.D Information: Expanding XOR equation found on signal \spg:current_phase_8\.T Information: Generating both D & T register equations for signal \spg:current_phase_9\.D Information: Expanding XOR equation found on signal \spg:current_phase_9\.T Information: Generating both D & T register equations for signal \spg:current_phase_10\.D Information: Expanding XOR equation found on signal \spg:current_phase_10\.T Information: Generating both D & T register equations for signal \spg:current_phase_11\.D Information: Expanding XOR equation found on signal \spg:current_phase_11\.T Information: Generating both D & T register equations for signal \spg:current_phase_12\.D Information: Expanding XOR equation found on signal \spg:current_phase_12\.T Information: Generating both D & T register equations for signal \spg:current_count_0\.D Information: Expanding XOR equation found on signal \spg:current_count_0\.T Information: Generating both D & T register equations for signal \spg:current_count_1\.D Information: Expanding XOR equation found on signal \spg:current_count_1\.T Information: Generating both D & T register equations for signal \spg:current_count_2\.D Information: Expanding XOR equation found on signal \spg:current_count_2\.T Information: Generating both D & T register equations for signal \spg:current_count_3\.D Information: Expanding XOR equation found on signal \spg:current_count_3\.T Information: Generating both D & T register equations for signal \spg:current_count_4\.D Information: Expanding XOR equation found on signal \spg:current_count_4\.T Information: Generating both D & T register equations for signal \spg:current_count_5\.D Information: Expanding XOR equation found on signal \spg:current_count_5\.T Information: Generating both D & T register equations for signal \spg:current_count_6\.D Information: Expanding XOR equation found on signal \spg:current_count_6\.T Information: Generating both D & T register equations for signal \spg:current_count_7\.D Information: Expanding XOR equation found on signal \spg:current_count_7\.T Information: Generating both D & T register equations for signal \spg:current_count_8\.D Information: Expanding XOR equation found on signal \spg:current_count_8\.T Information: Generating both D & T register equations for signal \spg:current_count_9\.D Information: Expanding XOR equation found on signal \spg:current_count_9\.T Information: Generating both D & T register equations for signal \spg:kick_dac\.D Information: Expanding XOR equation found on signal \spg:kick_dac\.T Information: Generating both D & T register equations for signal \spg:precount_0\.D Information: Expanding XOR equation found on signal \spg:precount_0\.T Information: Generating both D & T register equations for signal \spg:precount_1\.D Information: Expanding XOR equation found on signal \spg:precount_1\.T Information: Generating both D & T register equations for signal \spg:precount_2\.D Information: Expanding XOR equation found on signal \spg:precount_2\.T Information: Generating both D & T register equations for signal \spg:precount_3\.D Information: Expanding XOR equation found on signal \spg:precount_3\.T Information: Generating both D & T register equations for signal \spg:iclk\.D Information: Expanding XOR equation found on signal \spg:iclk\.T Information: Generating both D & T register equations for signal \spg:sample_0\.D Information: Expanding XOR equation found on signal \spg:sample_0\.T Information: Generating both D & T register equations for signal \spg:sample_1\.D Information: Expanding XOR equation found on signal \spg:sample_1\.T Information: Generating both D & T register equations for signal \spg:sample_2\.D Information: Expanding XOR equation found on signal \spg:sample_2\.T Information: Generating both D & T register equations for signal \rio:this_is_a_ctrl_transaction\.D Information: Expanding XOR equation found on signal \rio:this_is_a_ctrl_transaction\.T Information: Generating both D & T register equations for signal \rio:il_read_stateSBV_2\.D Information: Expanding XOR equation found on signal \rio:il_read_stateSBV_2\.T Information: Generating both D & T register equations for signal \rio:il_read_stateSBV_1\.D Information: Expanding XOR equation found on signal \rio:il_read_stateSBV_1\.T Information: Generating both D & T register equations for signal \rio:il_read_stateSBV_0\.D Information: Expanding XOR equation found on signal \rio:il_read_stateSBV_0\.T Information: Generating both D & T register equations for signal predev_0.D Information: Expanding XOR equation found on signal predev_0.T Information: Generating both D & T register equations for signal predev_1.D Information: Expanding XOR equation found on signal predev_1.T Information: Generating both D & T register equations for signal predev_2.D Information: Expanding XOR equation found on signal predev_2.T Information: Generating both D & T register equations for signal predev_3.D Information: Expanding XOR equation found on signal predev_3.T Information: Generating both D & T register equations for signal val7_0.D Information: Expanding XOR equation found on signal val7_0.T Information: Generating both D & T register equations for signal val7_1.D Information: Expanding XOR equation found on signal val7_1.T Information: Generating both D & T register equations for signal val7_2.D Information: Expanding XOR equation found on signal val7_2.T Information: Generating both D & T register equations for signal val7_3.D Information: Expanding XOR equation found on signal val7_3.T Information: Generating both D & T register equations for signal val7_4.D Information: Expanding XOR equation found on signal val7_4.T Information: Generating both D & T register equations for signal val7_5.D Information: Expanding XOR equation found on signal val7_5.T Information: Generating both D & T register equations for signal val7_6.D Information: Expanding XOR equation found on signal val7_6.T Information: Generating both D & T register equations for signal val7_7.D Information: Expanding XOR equation found on signal val7_7.T Information: Generating both D & T register equations for signal val6_0.D Information: Expanding XOR equation found on signal val6_0.T Information: Generating both D & T register equations for signal val6_1.D Information: Expanding XOR equation found on signal val6_1.T Information: Generating both D & T register equations for signal val6_2.D Information: Expanding XOR equation found on signal val6_2.T Information: Generating both D & T register equations for signal val6_3.D Information: Expanding XOR equation found on signal val6_3.T Information: Generating both D & T register equations for signal val6_4.D Information: Expanding XOR equation found on signal val6_4.T Information: Generating both D & T register equations for signal val6_5.D Information: Expanding XOR equation found on signal val6_5.T Information: Generating both D & T register equations for signal val6_6.D Information: Expanding XOR equation found on signal val6_6.T Information: Generating both D & T register equations for signal val6_7.D Information: Expanding XOR equation found on signal val6_7.T Information: Generating both D & T register equations for signal val5_0.D Information: Expanding XOR equation found on signal val5_0.T Information: Generating both D & T register equations for signal val5_1.D Information: Expanding XOR equation found on signal val5_1.T Information: Generating both D & T register equations for signal val5_2.D Information: Expanding XOR equation found on signal val5_2.T Information: Generating both D & T register equations for signal val5_3.D Information: Expanding XOR equation found on signal val5_3.T Information: Generating both D & T register equations for signal val5_4.D Information: Expanding XOR equation found on signal val5_4.T Information: Generating both D & T register equations for signal val5_5.D Information: Expanding XOR equation found on signal val5_5.T Information: Generating both D & T register equations for signal val5_6.D Information: Expanding XOR equation found on signal val5_6.T Information: Generating both D & T register equations for signal val5_7.D Information: Expanding XOR equation found on signal val5_7.T Information: Generating both D & T register equations for signal val4_0.D Information: Expanding XOR equation found on signal val4_0.T Information: Generating both D & T register equations for signal val4_1.D Information: Expanding XOR equation found on signal val4_1.T Information: Generating both D & T register equations for signal val4_2.D Information: Expanding XOR equation found on signal val4_2.T Information: Generating both D & T register equations for signal val4_3.D Information: Expanding XOR equation found on signal val4_3.T Information: Generating both D & T register equations for signal val4_4.D Information: Expanding XOR equation found on signal val4_4.T Information: Generating both D & T register equations for signal val4_5.D Information: Expanding XOR equation found on signal val4_5.T Information: Generating both D & T register equations for signal val4_6.D Information: Expanding XOR equation found on signal val4_6.T Information: Generating both D & T register equations for signal val4_7.D Information: Expanding XOR equation found on signal val4_7.T Information: Generating both D & T register equations for signal val3_0.D Information: Expanding XOR equation found on signal val3_0.T Information: Generating both D & T register equations for signal val3_1.D Information: Expanding XOR equation found on signal val3_1.T Information: Generating both D & T register equations for signal val3_2.D Information: Expanding XOR equation found on signal val3_2.T Information: Generating both D & T register equations for signal val3_3.D Information: Expanding XOR equation found on signal val3_3.T Information: Generating both D & T register equations for signal val3_4.D Information: Expanding XOR equation found on signal val3_4.T Information: Generating both D & T register equations for signal val3_5.D Information: Expanding XOR equation found on signal val3_5.T Information: Generating both D & T register equations for signal val3_6.D Information: Expanding XOR equation found on signal val3_6.T Information: Generating both D & T register equations for signal val3_7.D Information: Expanding XOR equation found on signal val3_7.T Information: Generating both D & T register equations for signal val2_0.D Information: Expanding XOR equation found on signal val2_0.T Information: Generating both D & T register equations for signal val2_1.D Information: Expanding XOR equation found on signal val2_1.T Information: Generating both D & T register equations for signal val2_2.D Information: Expanding XOR equation found on signal val2_2.T Information: Generating both D & T register equations for signal val2_3.D Information: Expanding XOR equation found on signal val2_3.T Information: Generating both D & T register equations for signal val2_4.D Information: Expanding XOR equation found on signal val2_4.T Information: Generating both D & T register equations for signal val2_5.D Information: Expanding XOR equation found on signal val2_5.T Information: Generating both D & T register equations for signal val2_6.D Information: Expanding XOR equation found on signal val2_6.T Information: Generating both D & T register equations for signal val2_7.D Information: Expanding XOR equation found on signal val2_7.T Information: Generating both D & T register equations for signal val1_0.D Information: Expanding XOR equation found on signal val1_0.T Information: Generating both D & T register equations for signal val1_1.D Information: Expanding XOR equation found on signal val1_1.T Information: Generating both D & T register equations for signal val1_2.D Information: Expanding XOR equation found on signal val1_2.T Information: Generating both D & T register equations for signal val1_3.D Information: Expanding XOR equation found on signal val1_3.T Information: Generating both D & T register equations for signal val1_4.D Information: Expanding XOR equation found on signal val1_4.T Information: Generating both D & T register equations for signal val1_5.D Information: Expanding XOR equation found on signal val1_5.T Information: Generating both D & T register equations for signal val1_6.D Information: Expanding XOR equation found on signal val1_6.T Information: Generating both D & T register equations for signal val1_7.D Information: Expanding XOR equation found on signal val1_7.T Information: Generating both D & T register equations for signal val0_0.D Information: Expanding XOR equation found on signal val0_0.T Information: Generating both D & T register equations for signal val0_1.D Information: Expanding XOR equation found on signal val0_1.T Information: Generating both D & T register equations for signal val0_2.D Information: Expanding XOR equation found on signal val0_2.T Information: Generating both D & T register equations for signal val0_3.D Information: Expanding XOR equation found on signal val0_3.T Information: Generating both D & T register equations for signal val0_4.D Information: Expanding XOR equation found on signal val0_4.T Information: Generating both D & T register equations for signal val0_5.D Information: Expanding XOR equation found on signal val0_5.T Information: Generating both D & T register equations for signal val0_6.D Information: Expanding XOR equation found on signal val0_6.T Information: Generating both D & T register equations for signal val0_7.D Information: Expanding XOR equation found on signal val0_7.T Information: Generating both D & T register equations for signal steplen_0.D Information: Expanding XOR equation found on signal steplen_0.T Information: Generating both D & T register equations for signal steplen_1.D Information: Expanding XOR equation found on signal steplen_1.T Information: Generating both D & T register equations for signal steplen_2.D Information: Expanding XOR equation found on signal steplen_2.T Information: Generating both D & T register equations for signal steplen_3.D Information: Expanding XOR equation found on signal steplen_3.T Information: Generating both D & T register equations for signal steplen_4.D Information: Expanding XOR equation found on signal steplen_4.T Information: Generating both D & T register equations for signal steplen_5.D Information: Expanding XOR equation found on signal steplen_5.T Information: Generating both D & T register equations for signal steplen_6.D Information: Expanding XOR equation found on signal steplen_6.T Information: Generating both D & T register equations for signal steplen_7.D Information: Expanding XOR equation found on signal steplen_7.T Information: Generating both D & T register equations for signal steplen_8.D Information: Expanding XOR equation found on signal steplen_8.T Information: Generating both D & T register equations for signal steplen_9.D Information: Expanding XOR equation found on signal steplen_9.T Information: Generating both D & T register equations for signal phase2_0.D Information: Expanding XOR equation found on signal phase2_0.T Information: Generating both D & T register equations for signal phase2_1.D Information: Expanding XOR equation found on signal phase2_1.T Information: Generating both D & T register equations for signal phase2_2.D Information: Expanding XOR equation found on signal phase2_2.T Information: Generating both D & T register equations for signal phase2_3.D Information: Expanding XOR equation found on signal phase2_3.T Information: Generating both D & T register equations for signal phase2_4.D Information: Expanding XOR equation found on signal phase2_4.T Information: Generating both D & T register equations for signal phase2_5.D Information: Expanding XOR equation found on signal phase2_5.T Information: Generating both D & T register equations for signal phase2_6.D Information: Expanding XOR equation found on signal phase2_6.T Information: Generating both D & T register equations for signal phase2_7.D Information: Expanding XOR equation found on signal phase2_7.T Information: Generating both D & T register equations for signal phase2_8.D Information: Expanding XOR equation found on signal phase2_8.T Information: Generating both D & T register equations for signal phase2_9.D Information: Expanding XOR equation found on signal phase2_9.T Information: Generating both D & T register equations for signal phase2_10.D Information: Expanding XOR equation found on signal phase2_10.T Information: Generating both D & T register equations for signal phase2_11.D Information: Expanding XOR equation found on signal phase2_11.T Information: Generating both D & T register equations for signal phase2_12.D Information: Expanding XOR equation found on signal phase2_12.T Information: Generating both D & T register equations for signal phase1_0.D Information: Expanding XOR equation found on signal phase1_0.T Information: Generating both D & T register equations for signal phase1_1.D Information: Expanding XOR equation found on signal phase1_1.T Information: Generating both D & T register equations for signal phase1_2.D Information: Expanding XOR equation found on signal phase1_2.T Information: Generating both D & T register equations for signal phase1_3.D Information: Expanding XOR equation found on signal phase1_3.T Information: Generating both D & T register equations for signal phase1_4.D Information: Expanding XOR equation found on signal phase1_4.T Information: Generating both D & T register equations for signal phase1_5.D Information: Expanding XOR equation found on signal phase1_5.T Information: Generating both D & T register equations for signal phase1_6.D Information: Expanding XOR equation found on signal phase1_6.T Information: Generating both D & T register equations for signal phase1_7.D Information: Expanding XOR equation found on signal phase1_7.T Information: Generating both D & T register equations for signal phase1_8.D Information: Expanding XOR equation found on signal phase1_8.T Information: Generating both D & T register equations for signal phase1_9.D Information: Expanding XOR equation found on signal phase1_9.T Information: Generating both D & T register equations for signal phase1_10.D Information: Expanding XOR equation found on signal phase1_10.T Information: Generating both D & T register equations for signal phase1_11.D Information: Expanding XOR equation found on signal phase1_11.T Information: Generating both D & T register equations for signal phase1_12.D Information: Expanding XOR equation found on signal phase1_12.T Information: Generating both D & T register equations for signal dac_data_from_pc_15.D Information: Expanding XOR equation found on signal dac_data_from_pc_15.T Information: Generating both D & T register equations for signal this_chip_selected.D Information: Expanding XOR equation found on signal this_chip_selected.T Information: Generating both D & T register equations for signal \dacwr:dac_hold_0\.D Information: Expanding XOR equation found on signal \dacwr:dac_hold_0\.T Information: Generating both D & T register equations for signal \dacwr:dac_hold_1\.D Information: Expanding XOR equation found on signal \dacwr:dac_hold_1\.T Information: Generating both D & T register equations for signal \dacwr:dac_hold_2\.D Information: Expanding XOR equation found on signal \dacwr:dac_hold_2\.T Information: Generating both D & T register equations for signal \dacwr:dac_hold_3\.D Information: Expanding XOR equation found on signal \dacwr:dac_hold_3\.T Information: Generating both D & T register equations for signal \dacwr:dac_hold_4\.D Information: Expanding XOR equation found on signal \dacwr:dac_hold_4\.T Information: Generating both D & T register equations for signal \dacwr:dac_hold_5\.D Information: Expanding XOR equation found on signal \dacwr:dac_hold_5\.T Information: Generating both D & T register equations for signal \dacwr:dac_hold_6\.D Information: Expanding XOR equation found on signal \dacwr:dac_hold_6\.T Information: Generating both D & T register equations for signal \dacwr:dac_hold_7\.D Information: Expanding XOR equation found on signal \dacwr:dac_hold_7\.T Information: Generating both D & T register equations for signal \dacwr:dac_hold_8\.D Information: Expanding XOR equation found on signal \dacwr:dac_hold_8\.T Information: Generating both D & T register equations for signal \dacwr:dac_hold_9\.D Information: Expanding XOR equation found on signal \dacwr:dac_hold_9\.T Information: Generating both D & T register equations for signal \dacwr:dac_hold_10\.D Information: Expanding XOR equation found on signal \dacwr:dac_hold_10\.T Information: Generating both D & T register equations for signal \dacwr:dac_hold_11\.D Information: Expanding XOR equation found on signal \dacwr:dac_hold_11\.T Information: Generating both D & T register equations for signal \dacwr:dac_hold_12\.D Information: Expanding XOR equation found on signal \dacwr:dac_hold_12\.T Information: Generating both D & T register equations for signal \dacwr:timeout_0\.D Information: Expanding XOR equation found on signal \dacwr:timeout_0\.T Information: Generating both D & T register equations for signal \dacwr:timeout_1\.D Information: Expanding XOR equation found on signal \dacwr:timeout_1\.T Information: Generating both D & T register equations for signal \dacwr:timeout_2\.D Information: Expanding XOR equation found on signal \dacwr:timeout_2\.T Information: Generating both D & T register equations for signal \dacwr:dac_stateSBV_2\.D Information: Expanding XOR equation found on signal \dacwr:dac_stateSBV_2\.T Information: Generating both D & T register equations for signal \dacwr:dac_stateSBV_1\.D Information: Expanding XOR equation found on signal \dacwr:dac_stateSBV_1\.T Information: Generating both D & T register equations for signal \dacwr:dac_stateSBV_0\.D Information: Expanding XOR equation found on signal \dacwr:dac_stateSBV_0\.T Information: Generating both D & T register equations for signal shift_0.D Information: Expanding XOR equation found on signal shift_0.T Information: Generating both D & T register equations for signal shift_1.D Information: Expanding XOR equation found on signal shift_1.T Information: Generating both D & T register equations for signal shift_2.D Information: Expanding XOR equation found on signal shift_2.T Information: Generating both D & T register equations for signal address_from_pc_0.D Information: Expanding XOR equation found on signal address_from_pc_0.T Information: Generating both D & T register equations for signal address_from_pc_1.D Information: Expanding XOR equation found on signal address_from_pc_1.T Information: Generating both D & T register equations for signal address_from_pc_2.D Information: Expanding XOR equation found on signal address_from_pc_2.T Information: Generating both D & T register equations for signal address_from_pc_3.D Information: Expanding XOR equation found on signal address_from_pc_3.T Information: Generating both D & T register equations for signal dac_data_from_pc_0.D Information: Expanding XOR equation found on signal dac_data_from_pc_0.T Information: Generating both D & T register equations for signal dac_data_from_pc_1.D Information: Expanding XOR equation found on signal dac_data_from_pc_1.T Information: Generating both D & T register equations for signal dac_data_from_pc_2.D Information: Expanding XOR equation found on signal dac_data_from_pc_2.T Information: Generating both D & T register equations for signal dac_data_from_pc_3.D Information: Expanding XOR equation found on signal dac_data_from_pc_3.T Information: Generating both D & T register equations for signal dac_data_from_pc_4.D Information: Expanding XOR equation found on signal dac_data_from_pc_4.T Information: Generating both D & T register equations for signal dac_data_from_pc_5.D Information: Expanding XOR equation found on signal dac_data_from_pc_5.T Information: Generating both D & T register equations for signal dac_data_from_pc_6.D Information: Expanding XOR equation found on signal dac_data_from_pc_6.T Information: Generating both D & T register equations for signal dac_data_from_pc_7.D Information: Expanding XOR equation found on signal dac_data_from_pc_7.T Information: Generating both D & T register equations for signal dac_data_from_pc_8.D Information: Expanding XOR equation found on signal dac_data_from_pc_8.T Information: Generating both D & T register equations for signal dac_data_from_pc_9.D Information: Expanding XOR equation found on signal dac_data_from_pc_9.T Information: Generating both D & T register equations for signal dac_data_from_pc_10.D Information: Expanding XOR equation found on signal dac_data_from_pc_10.T Information: Generating both D & T register equations for signal dac_data_from_pc_11.D Information: Expanding XOR equation found on signal dac_data_from_pc_11.T Information: Generating both D & T register equations for signal dac_data_from_pc_12.D Information: Expanding XOR equation found on signal dac_data_from_pc_12.T Information: Generating both D & T register equations for signal to_dac_from_pc_ack.D Information: Expanding XOR equation found on signal to_dac_from_pc_ack.T Information: Generating both D & T register equations for signal to_dac_from_pc_req.D Information: Expanding XOR equation found on signal to_dac_from_pc_req.T Information: Generating both D & T register equations for signal sp_ack.D Information: Expanding XOR equation found on signal sp_ack.T Information: Generating both D & T register equations for signal sp_req.D Information: Expanding XOR equation found on signal sp_req.T Information: Optimizing logic without changing polarity for signals: \dacwr:dac_hold_0\.T \dacwr:dac_hold_10\.T \dacwr:dac_hold_11\.T \dacwr:dac_hold_12\.T \dacwr:dac_hold_1\.T \dacwr:dac_hold_2\.T \dacwr:dac_hold_3\.T \dacwr:dac_hold_4\.T \dacwr:dac_hold_5\.T \dacwr:dac_hold_6\.T \dacwr:dac_hold_7\.T \dacwr:dac_hold_8\.T \dacwr:dac_hold_9\.T \dacwr:dac_stateSBV_0\.T \dacwr:dac_stateSBV_1\.T \dacwr:dac_stateSBV_2\.T \dacwr:timeout_0\.T \dacwr:timeout_1\.T \dacwr:timeout_2\.T \rio:il_read_stateSBV_0\.T \rio:il_read_stateSBV_1\.T \rio:il_read_stateSBV_2\.T \rio:this_is_a_ctrl_transaction\.T \spg:current_count_0\.T \spg:current_count_1\.T \spg:current_count_2\.T \spg:current_count_3\.T \spg:current_count_4\.T \spg:current_count_5\.T \spg:current_count_6\.T \spg:current_count_7\.T \spg:current_count_8\.T \spg:current_count_9\.T \spg:current_phase_0\.T \spg:current_phase_10\.T \spg:current_phase_11\.T \spg:current_phase_12\.T \spg:current_phase_1\.T \spg:current_phase_2\.T \spg:current_phase_3\.T \spg:current_phase_4\.T \spg:current_phase_5\.T \spg:current_phase_6\.T \spg:current_phase_7\.T \spg:current_phase_8\.T \spg:current_phase_9\.T \spg:iclk\.T \spg:kdacSBV_0\.T \spg:kick_dac\.T \spg:precount_0\.T \spg:precount_1\.T \spg:precount_2\.T \spg:precount_3\.T \spg:sample_0\.T \spg:sample_1\.T \spg:sample_2\.T address_from_pc_0.T address_from_pc_1.T address_from_pc_2.T address_from_pc_3.T ao_from_pc_ack.T da_not_wr.T daaddr(0).T daaddr(1).T daaddr(2).T dac_data_from_pc_0.T dac_data_from_pc_1.T dac_data_from_pc_10.T dac_data_from_pc_11.T dac_data_from_pc_12.T dac_data_from_pc_15.T dac_data_from_pc_2.T dac_data_from_pc_3.T dac_data_from_pc_4.T dac_data_from_pc_5.T dac_data_from_pc_6.T dac_data_from_pc_7.T dac_data_from_pc_8.T dac_data_from_pc_9.T dad(0).T dad(1).T dad(10).T dad(11).T dad(12).T dad(2).T dad(3).T dad(4).T dad(5).T dad(6).T dad(7).T dad(8).T dad(9).T phase1_0.T phase1_1.T phase1_10.T phase1_11.T phase1_12.T phase1_2.T phase1_3.T phase1_4.T phase1_5.T phase1_6.T phase1_7.T phase1_8.T phase1_9.T phase2_0.T phase2_1.T phase2_10.T phase2_11.T phase2_12.T phase2_2.T phase2_3.T phase2_4.T phase2_5.T phase2_6.T phase2_7.T phase2_8.T phase2_9.T predev_0.T predev_1.T predev_2.T predev_3.T shift_0.T shift_1.T shift_2.T sinphase_zeros.T sp_ack.T sp_req.T steplen_0.T steplen_1.T steplen_2.T steplen_3.T steplen_4.T steplen_5.T steplen_6.T steplen_7.T steplen_8.T steplen_9.T this_chip_selected.T to_dac_from_pc_ack.T to_dac_from_pc_req.T val0_0.T val0_1.T val0_2.T val0_3.T val0_4.T val0_5.T val0_6.T val0_7.T val1_0.T val1_1.T val1_2.T val1_3.T val1_4.T val1_5.T val1_6.T val1_7.T val2_0.T val2_1.T val2_2.T val2_3.T val2_4.T val2_5.T val2_6.T val2_7.T val3_0.T val3_1.T val3_2.T val3_3.T val3_4.T val3_5.T val3_6.T val3_7.T val4_0.T val4_1.T val4_2.T val4_3.T val4_4.T val4_5.T val4_6.T val4_7.T val5_0.T val5_1.T val5_2.T val5_3.T val5_4.T val5_5.T val5_6.T val5_7.T val6_0.T val6_1.T val6_2.T val6_3.T val6_4.T val6_5.T val6_6.T val6_7.T val7_0.T val7_1.T val7_2.T val7_3.T val7_4.T val7_5.T val7_6.T val7_7.T Information: Optimizing logic using best output polarity for signals: \dacwr:cmp_vv_us_MODGEN_10\ \dacwr:dac_hold_0\.D \dacwr:dac_hold_10\.D \dacwr:dac_hold_11\.D \dacwr:dac_hold_12\.D \dacwr:dac_hold_1\.D \dacwr:dac_hold_2\.D \dacwr:dac_hold_3\.D \dacwr:dac_hold_4\.D \dacwr:dac_hold_5\.D \dacwr:dac_hold_6\.D \dacwr:dac_hold_7\.D \dacwr:dac_hold_8\.D \dacwr:dac_hold_9\.D \dacwr:dac_stateSBV_0\.D \dacwr:dac_stateSBV_1\.D \dacwr:dac_stateSBV_2\.D \dacwr:timeout_0\.D \dacwr:timeout_1\.D \dacwr:timeout_2\.D \rio:il_read_stateSBV_0\.D \rio:il_read_stateSBV_1\.D \rio:il_read_stateSBV_2\.D \rio:this_is_a_ctrl_transaction\.D \spg:MODULE_3:g1:a0:gx:u0:eq_5\ \spg:MODULE_3:g1:a0:gx:u0:geq(0):c3:u1\ \spg:MODULE_7:g1:a0:gx:u0:eq_5\ \spg:MODULE_7:g1:a0:gx:u0:geq(0):c3:u1\ \spg:MODULE_8:g1:a0:gx:u0:eq_5\ \spg:MODULE_8:g1:a0:gx:u0:geq(0):c3:u1\ \spg:cmp_vv_us_MODGEN_1\ \spg:cmp_vv_us_MODGEN_3\ \spg:cmp_vv_us_MODGEN_8\ \spg:current_count_1\.D \spg:current_count_2\.D \spg:current_count_3\.D \spg:current_count_4\.D \spg:current_count_5\.D \spg:current_count_6\.D \spg:current_count_7\.D \spg:current_count_8\.D \spg:current_count_9\.D \spg:current_phase_0\.D \spg:current_phase_10\.D \spg:current_phase_11\.D \spg:current_phase_12\.D \spg:current_phase_1\.D \spg:current_phase_2\.D \spg:current_phase_3\.D \spg:current_phase_4\.D \spg:current_phase_5\.D \spg:current_phase_6\.D \spg:current_phase_7\.D \spg:current_phase_8\.D \spg:current_phase_9\.D \spg:iclk\.D \spg:kdacSBV_0\.D \spg:precount_1\.D \spg:precount_2\.D \spg:precount_3\.D \spg:sample_0\.D \spg:sample_1\.D \spg:sample_2\.D address_from_pc_0.D address_from_pc_1.D address_from_pc_2.D address_from_pc_3.D da_not_ldab da_not_ldcd da_not_ldef da_not_ldgh daaddr(0).D daaddr(1).D daaddr(2).D dac_data_from_pc_0.D dac_data_from_pc_1.D dac_data_from_pc_10.D dac_data_from_pc_11.D dac_data_from_pc_12.D dac_data_from_pc_15.D dac_data_from_pc_2.D dac_data_from_pc_3.D dac_data_from_pc_4.D dac_data_from_pc_5.D dac_data_from_pc_6.D dac_data_from_pc_7.D dac_data_from_pc_8.D dac_data_from_pc_9.D dad(0).D dad(1).D dad(10).D dad(11).D dad(12).D dad(2).D dad(3).D dad(4).D dad(5).D dad(6).D dad(7).D dad(8).D dad(9).D phase1_0.D phase1_1.D phase1_10.D phase1_11.D phase1_12.D phase1_2.D phase1_3.D phase1_4.D phase1_5.D phase1_6.D phase1_7.D phase1_8.D phase1_9.D phase2_0.D phase2_1.D phase2_10.D phase2_11.D phase2_12.D phase2_2.D phase2_3.D phase2_4.D phase2_5.D phase2_6.D phase2_7.D phase2_8.D phase2_9.D predev_0.D predev_1.D predev_2.D predev_3.D shift_0.D shift_1.D shift_2.D sinphase_zeros.D sp_ack.D sp_req.D steplen_0.D steplen_1.D steplen_2.D steplen_3.D steplen_4.D steplen_5.D steplen_6.D steplen_7.D steplen_8.D steplen_9.D this_chip_selected.D to_dac_from_pc_ack.D val0_0.D val0_1.D val0_2.D val0_3.D val0_4.D val0_5.D val0_6.D val0_7.D val1_0.D val1_1.D val1_2.D val1_3.D val1_4.D val1_5.D val1_6.D val1_7.D val2_0.D val2_1.D val2_2.D val2_3.D val2_4.D val2_5.D val2_6.D val2_7.D val3_0.D val3_1.D val3_2.D val3_3.D val3_4.D val3_5.D val3_6.D val3_7.D val4_0.D val4_1.D val4_2.D val4_3.D val4_4.D val4_5.D val4_6.D val4_7.D val5_0.D val5_1.D val5_2.D val5_3.D val5_4.D val5_5.D val5_6.D val5_7.D val6_0.D val6_1.D val6_2.D val6_3.D val6_4.D val6_5.D val6_6.D val6_7.D val7_0.D val7_1.D val7_2.D val7_3.D val7_4.D val7_5.D val7_6.D val7_7.D Information: Selected logic optimization OFF for signals: \dacwr:dac_hold_0\.C \dacwr:dac_hold_10\.C \dacwr:dac_hold_11\.C \dacwr:dac_hold_12\.C \dacwr:dac_hold_1\.C \dacwr:dac_hold_2\.C \dacwr:dac_hold_3\.C \dacwr:dac_hold_4\.C \dacwr:dac_hold_5\.C \dacwr:dac_hold_6\.C \dacwr:dac_hold_7\.C \dacwr:dac_hold_8\.C \dacwr:dac_hold_9\.C \dacwr:dac_stateSBV_0\.C \dacwr:dac_stateSBV_1\.C \dacwr:dac_stateSBV_2\.C \dacwr:timeout_0\.C \dacwr:timeout_1\.C \dacwr:timeout_2\.C \rio:il_read_stateSBV_0\.C \rio:il_read_stateSBV_1\.C \rio:il_read_stateSBV_2\.C \rio:this_is_a_ctrl_transaction\.AR \rio:this_is_a_ctrl_transaction\.C \spg:cmp_vv_us_MODGEN_4\ \spg:current_count_0\.D \spg:current_count_0\.C \spg:current_count_1\.C \spg:current_count_2\.C \spg:current_count_3\.C \spg:current_count_4\.C \spg:current_count_5\.C \spg:current_count_6\.C \spg:current_count_7\.C \spg:current_count_8\.C \spg:current_count_9\.C \spg:current_phase_0\.C \spg:current_phase_10\.C \spg:current_phase_11\.C \spg:current_phase_12\.C \spg:current_phase_1\.C \spg:current_phase_2\.C \spg:current_phase_3\.C \spg:current_phase_4\.C \spg:current_phase_5\.C \spg:current_phase_6\.C \spg:current_phase_7\.C \spg:current_phase_8\.C \spg:current_phase_9\.C \spg:iclk\.C \spg:kdacSBV_0\.C \spg:kick_dac\.D \spg:kick_dac\.C \spg:precount_0\.D \spg:precount_0\.C \spg:precount_1\.C \spg:precount_2\.C \spg:precount_3\.C \spg:sample_0\.C \spg:sample_1\.C \spg:sample_2\.C address_from_pc_0.C address_from_pc_1.C address_from_pc_2.C address_from_pc_3.C ao_from_pc_ack.D ao_from_pc_ack.C ao_from_pc_ack.OE da_not_clr.D da_not_clr.T da_not_clr.AR da_not_clr.C da_not_cs.D da_not_cs.T da_not_cs.AR da_not_cs.C da_not_wr.D da_not_wr.C daaddr(0).C daaddr(1).C daaddr(2).C dac_data_from_pc_0.C dac_data_from_pc_1.C dac_data_from_pc_10.C dac_data_from_pc_11.C dac_data_from_pc_12.C dac_data_from_pc_15.C dac_data_from_pc_2.C dac_data_from_pc_3.C dac_data_from_pc_4.C dac_data_from_pc_5.C dac_data_from_pc_6.C dac_data_from_pc_7.C dac_data_from_pc_8.C dac_data_from_pc_9.C dad(0).C dad(1).C dad(10).C dad(11).C dad(12).C dad(2).C dad(3).C dad(4).C dad(5).C dad(6).C dad(7).C dad(8).C dad(9).C dio_tristate phase1_0.C phase1_1.C phase1_10.C phase1_11.C phase1_12.C phase1_2.C phase1_3.C phase1_4.C phase1_5.C phase1_6.C phase1_7.C phase1_8.C phase1_9.C phase2_0.C phase2_1.C phase2_10.C phase2_11.C phase2_12.C phase2_2.C phase2_3.C phase2_4.C phase2_5.C phase2_6.C phase2_7.C phase2_8.C phase2_9.C predev_0.C predev_1.C predev_2.C predev_3.C shdn(0) shdn(1) shdn(2) shift_0.C shift_1.C shift_2.C sinphase_zeros.C sp_ack.C sp_req.C steplen_0.C steplen_1.C steplen_2.C steplen_3.C steplen_4.C steplen_5.C steplen_6.C steplen_7.C steplen_8.C steplen_9.C this_chip_selected.AR this_chip_selected.C to_dac_from_pc_ack.C to_dac_from_pc_req.D to_dac_from_pc_req.C val0_0.C val0_1.C val0_2.C val0_3.C val0_4.C val0_5.C val0_6.C val0_7.C val1_0.C val1_1.C val1_2.C val1_3.C val1_4.C val1_5.C val1_6.C val1_7.C val2_0.C val2_1.C val2_2.C val2_3.C val2_4.C val2_5.C val2_6.C val2_7.C val3_0.C val3_1.C val3_2.C val3_3.C val3_4.C val3_5.C val3_6.C val3_7.C val4_0.C val4_1.C val4_2.C val4_3.C val4_4.C val4_5.C val4_6.C val4_7.C val5_0.C val5_1.C val5_2.C val5_3.C val5_4.C val5_5.C val5_6.C val5_7.C val6_0.C val6_1.C val6_2.C val6_3.C val6_4.C val6_5.C val6_6.C val6_7.C val7_0.C val7_1.C val7_2.C val7_3.C val7_4.C val7_5.C val7_6.C val7_7.C Summary: Error Count = 0 Warning Count = 0 Completed Successfully ---------------------------------------------------------------------------- PLD Optimizer Software: MINOPT.EXE 01/NOV/1999 [v4.02 ] 6.0.1 IR 18 LOGIC MINIMIZATION () Messages: Summary: Error Count = 0 Warning Count = 0 Completed Successfully ---------------------------------------------------------------------------- PLD Optimizer Software: DSGNOPT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 OPTIMIZATION OPTIONS (17:51:33) Messages: Information: Optimizing Banked Preset/Reset requirements. Information: Selecting D register equation as minimal for signal \rio:this_is_a_ctrl_transaction\ Information: Selecting T register equation as minimal for signal this_chip_selected Information: Selecting D register equation as minimal for signal da_not_clr Information: Selecting D register equation as minimal for signal da_not_cs Information: Selecting D register equation as minimal for signal ao_from_pc_ack Information: Selecting D register equation as minimal for signal sinphase_zeros Information: Sum-Splitting output logic for signal sinphase_zeros[79]. Information: Selecting D register equation as minimal for signal dad(0) Information: Selecting D register equation as minimal for signal dad(1) Information: Selecting D register equation as minimal for signal dad(2) Information: Selecting D register equation as minimal for signal dad(3) Information: Selecting D register equation as minimal for signal dad(4) Information: Selecting D register equation as minimal for signal dad(5) Information: Selecting D register equation as minimal for signal dad(6) Information: Selecting D register equation as minimal for signal dad(7) Information: Selecting D register equation as minimal for signal dad(8) Information: Selecting D register equation as minimal for signal dad(9) Information: Selecting D register equation as minimal for signal dad(10) Information: Selecting D register equation as minimal for signal dad(11) Information: Selecting D register equation as minimal for signal dad(12) Information: Selecting T register equation as minimal for signal daaddr(0) Information: Selecting T register equation as minimal for signal daaddr(1) Information: Selecting T register equation as minimal for signal daaddr(2) Information: Selecting D register equation as minimal for signal da_not_wr Information: Selecting T register equation as minimal for signal val7_7 Information: Selecting T register equation as minimal for signal val7_6 Information: Selecting T register equation as minimal for signal val7_5 Information: Selecting T register equation as minimal for signal val7_4 Information: Selecting T register equation as minimal for signal val7_3 Information: Selecting T register equation as minimal for signal val7_2 Information: Selecting T register equation as minimal for signal val7_1 Information: Selecting T register equation as minimal for signal val7_0 Information: Selecting T register equation as minimal for signal val6_7 Information: Selecting T register equation as minimal for signal val6_6 Information: Selecting T register equation as minimal for signal val6_5 Information: Selecting T register equation as minimal for signal val6_4 Information: Selecting T register equation as minimal for signal val6_3 Information: Selecting T register equation as minimal for signal val6_2 Information: Selecting T register equation as minimal for signal val6_1 Information: Selecting T register equation as minimal for signal val6_0 Information: Selecting T register equation as minimal for signal val5_7 Information: Selecting T register equation as minimal for signal val5_6 Information: Selecting T register equation as minimal for signal val5_5 Information: Selecting T register equation as minimal for signal val5_4 Information: Selecting T register equation as minimal for signal val5_3 Information: Selecting T register equation as minimal for signal val5_2 Information: Selecting T register equation as minimal for signal val5_1 Information: Selecting T register equation as minimal for signal val5_0 Information: Selecting T register equation as minimal for signal val4_7 Information: Selecting T register equation as minimal for signal val4_6 Information: Selecting T register equation as minimal for signal val4_5 Information: Selecting T register equation as minimal for signal val4_4 Information: Selecting T register equation as minimal for signal val4_3 Information: Selecting T register equation as minimal for signal val4_2 Information: Selecting T register equation as minimal for signal val4_1 Information: Selecting T register equation as minimal for signal val4_0 Information: Selecting T register equation as minimal for signal val3_7 Information: Selecting T register equation as minimal for signal val3_6 Information: Selecting T register equation as minimal for signal val3_5 Information: Selecting T register equation as minimal for signal val3_4 Information: Selecting T register equation as minimal for signal val3_3 Information: Selecting T register equation as minimal for signal val3_2 Information: Selecting T register equation as minimal for signal val3_1 Information: Selecting T register equation as minimal for signal val3_0 Information: Selecting T register equation as minimal for signal val2_7 Information: Selecting T register equation as minimal for signal val2_6 Information: Selecting T register equation as minimal for signal val2_5 Information: Selecting T register equation as minimal for signal val2_4 Information: Selecting T register equation as minimal for signal val2_3 Information: Selecting T register equation as minimal for signal val2_2 Information: Selecting T register equation as minimal for signal val2_1 Information: Selecting T register equation as minimal for signal val2_0 Information: Selecting T register equation as minimal for signal val1_7 Information: Selecting T register equation as minimal for signal val1_6 Information: Selecting T register equation as minimal for signal val1_5 Information: Selecting T register equation as minimal for signal val1_4 Information: Selecting T register equation as minimal for signal val1_3 Information: Selecting T register equation as minimal for signal val1_2 Information: Selecting T register equation as minimal for signal val1_1 Information: Selecting T register equation as minimal for signal val1_0 Information: Selecting T register equation as minimal for signal val0_7 Information: Selecting T register equation as minimal for signal val0_6 Information: Selecting T register equation as minimal for signal val0_5 Information: Selecting T register equation as minimal for signal val0_4 Information: Selecting T register equation as minimal for signal val0_3 Information: Selecting T register equation as minimal for signal val0_2 Information: Selecting T register equation as minimal for signal val0_1 Information: Selecting T register equation as minimal for signal val0_0 Information: Selecting D register equation as minimal for signal to_dac_from_pc_req Information: Selecting D register equation as minimal for signal to_dac_from_pc_ack Information: Selecting T register equation as minimal for signal steplen_9 Information: Selecting T register equation as minimal for signal steplen_8 Information: Selecting T register equation as minimal for signal steplen_7 Information: Selecting T register equation as minimal for signal steplen_6 Information: Selecting T register equation as minimal for signal steplen_5 Information: Selecting T register equation as minimal for signal steplen_4 Information: Selecting T register equation as minimal for signal steplen_3 Information: Selecting T register equation as minimal for signal steplen_2 Information: Selecting T register equation as minimal for signal steplen_1 Information: Selecting T register equation as minimal for signal steplen_0 Information: Selecting D register equation as minimal for signal sp_req Information: Selecting D register equation as minimal for signal sp_ack Information: Selecting T register equation as minimal for signal shift_2 Information: Selecting T register equation as minimal for signal shift_1 Information: Selecting T register equation as minimal for signal shift_0 Information: Selecting T register equation as minimal for signal predev_3 Information: Selecting T register equation as minimal for signal predev_2 Information: Selecting T register equation as minimal for signal predev_1 Information: Selecting T register equation as minimal for signal predev_0 Information: Selecting T register equation as minimal for signal phase2_9 Information: Selecting T register equation as minimal for signal phase2_8 Information: Selecting T register equation as minimal for signal phase2_7 Information: Selecting T register equation as minimal for signal phase2_6 Information: Selecting T register equation as minimal for signal phase2_5 Information: Selecting T register equation as minimal for signal phase2_4 Information: Selecting T register equation as minimal for signal phase2_3 Information: Selecting T register equation as minimal for signal phase2_2 Information: Selecting T register equation as minimal for signal phase2_12 Information: Selecting T register equation as minimal for signal phase2_11 Information: Selecting T register equation as minimal for signal phase2_10 Information: Selecting T register equation as minimal for signal phase2_1 Information: Selecting T register equation as minimal for signal phase2_0 Information: Selecting T register equation as minimal for signal phase1_9 Information: Selecting T register equation as minimal for signal phase1_8 Information: Selecting T register equation as minimal for signal phase1_7 Information: Selecting T register equation as minimal for signal phase1_6 Information: Selecting T register equation as minimal for signal phase1_5 Information: Selecting T register equation as minimal for signal phase1_4 Information: Selecting T register equation as minimal for signal phase1_3 Information: Selecting T register equation as minimal for signal phase1_2 Information: Selecting T register equation as minimal for signal phase1_12 Information: Selecting T register equation as minimal for signal phase1_11 Information: Selecting T register equation as minimal for signal phase1_10 Information: Selecting T register equation as minimal for signal phase1_1 Information: Selecting T register equation as minimal for signal phase1_0 Information: Selecting T register equation as minimal for signal dac_data_from_pc_9 Information: Selecting T register equation as minimal for signal dac_data_from_pc_8 Information: Selecting T register equation as minimal for signal dac_data_from_pc_7 Information: Selecting T register equation as minimal for signal dac_data_from_pc_6 Information: Selecting T register equation as minimal for signal dac_data_from_pc_5 Information: Selecting T register equation as minimal for signal dac_data_from_pc_4 Information: Selecting T register equation as minimal for signal dac_data_from_pc_3 Information: Selecting T register equation as minimal for signal dac_data_from_pc_2 Information: Selecting T register equation as minimal for signal dac_data_from_pc_15 Information: Selecting T register equation as minimal for signal dac_data_from_pc_12 Information: Selecting T register equation as minimal for signal dac_data_from_pc_11 Information: Selecting T register equation as minimal for signal dac_data_from_pc_10 Information: Selecting T register equation as minimal for signal dac_data_from_pc_1 Information: Selecting T register equation as minimal for signal dac_data_from_pc_0 Information: Selecting T register equation as minimal for signal address_from_pc_3 Information: Selecting T register equation as minimal for signal address_from_pc_2 Information: Selecting T register equation as minimal for signal address_from_pc_1 Information: Selecting T register equation as minimal for signal address_from_pc_0 Information: Selecting T register equation as minimal for signal \spg:sample_2\ Information: Selecting T register equation as minimal for signal \spg:sample_1\ Information: Selecting D register equation as minimal for signal \spg:sample_0\ Information: Selecting T register equation as minimal for signal \spg:precount_3\ Information: Selecting T register equation as minimal for signal \spg:precount_2\ Information: Selecting D register equation as minimal for signal \spg:precount_1\ Information: Selecting D register equation as minimal for signal \spg:precount_0\ Information: Selecting D register equation as minimal for signal \spg:kick_dac\ Information: Selecting D register equation as minimal for signal \spg:kdacSBV_0\ Information: Selecting T register equation as minimal for signal \spg:iclk\ Information: Selecting T register equation as minimal for signal \spg:current_phase_9\ Information: Selecting T register equation as minimal for signal \spg:current_phase_8\ Information: Selecting T register equation as minimal for signal \spg:current_phase_7\ Information: Selecting T register equation as minimal for signal \spg:current_phase_6\ Information: Selecting T register equation as minimal for signal \spg:current_phase_5\ Information: Selecting T register equation as minimal for signal \spg:current_phase_4\ Information: Selecting T register equation as minimal for signal \spg:current_phase_3\ Information: Selecting T register equation as minimal for signal \spg:current_phase_2\ Information: Selecting D register equation as minimal for signal \spg:current_phase_1\ Information: Selecting T register equation as minimal for signal \spg:current_phase_12\ Information: Selecting T register equation as minimal for signal \spg:current_phase_11\ Information: Selecting T register equation as minimal for signal \spg:current_phase_10\ Information: Selecting D register equation as minimal for signal \spg:current_phase_0\ Information: Selecting T register equation as minimal for signal \spg:current_count_9\ Information: Selecting T register equation as minimal for signal \spg:current_count_8\ Information: Selecting T register equation as minimal for signal \spg:current_count_7\ Information: Selecting T register equation as minimal for signal \spg:current_count_6\ Information: Selecting T register equation as minimal for signal \spg:current_count_5\ Information: Selecting T register equation as minimal for signal \spg:current_count_4\ Information: Selecting T register equation as minimal for signal \spg:current_count_3\ Information: Selecting T register equation as minimal for signal \spg:current_count_2\ Information: Selecting D register equation as minimal for signal \spg:current_count_1\ Information: Selecting D register equation as minimal for signal \spg:current_count_0\ Information: Selecting D register equation as minimal for signal \rio:il_read_stateSBV_2\ Information: Selecting D register equation as minimal for signal \rio:il_read_stateSBV_1\ Information: Selecting D register equation as minimal for signal \rio:il_read_stateSBV_0\ Information: Selecting T register equation as minimal for signal \dacwr:timeout_2\ Information: Selecting D register equation as minimal for signal \dacwr:timeout_1\ Information: Selecting D register equation as minimal for signal \dacwr:timeout_0\ Information: Selecting D register equation as minimal for signal \dacwr:dac_stateSBV_2\ Information: Selecting T register equation as minimal for signal \dacwr:dac_stateSBV_1\ Information: Selecting D register equation as minimal for signal \dacwr:dac_stateSBV_0\ Information: Selecting T register equation as minimal for signal \dacwr:dac_hold_9\ Information: Selecting T register equation as minimal for signal \dacwr:dac_hold_8\ Information: Selecting D register equation as minimal for signal \dacwr:dac_hold_7\ Information: Selecting D register equation as minimal for signal \dacwr:dac_hold_6\ Information: Selecting D register equation as minimal for signal \dacwr:dac_hold_5\ Information: Selecting D register equation as minimal for signal \dacwr:dac_hold_4\ Information: Selecting D register equation as minimal for signal \dacwr:dac_hold_3\ Information: Selecting D register equation as minimal for signal \dacwr:dac_hold_2\ Information: Selecting D register equation as minimal for signal \dacwr:dac_hold_1\ Information: Selecting T register equation as minimal for signal \dacwr:dac_hold_12\ Information: Selecting T register equation as minimal for signal \dacwr:dac_hold_11\ Information: Selecting T register equation as minimal for signal \dacwr:dac_hold_10\ Information: Selecting D register equation as minimal for signal \dacwr:dac_hold_0\ Information: Optimizing Banked Preset/Reset requirements. Information: Selecting D register equation as minimal for signal \dacwr:dac_hold_0\ Information: Selecting T register equation as minimal for signal \dacwr:dac_hold_10\ Information: Selecting T register equation as minimal for signal \dacwr:dac_hold_11\ Information: Selecting T register equation as minimal for signal \dacwr:dac_hold_12\ Information: Selecting D register equation as minimal for signal \dacwr:dac_hold_1\ Information: Selecting D register equation as minimal for signal \dacwr:dac_hold_2\ Information: Selecting D register equation as minimal for signal \dacwr:dac_hold_3\ Information: Selecting D register equation as minimal for signal \dacwr:dac_hold_4\ Information: Selecting D register equation as minimal for signal \dacwr:dac_hold_5\ Information: Selecting D register equation as minimal for signal \dacwr:dac_hold_6\ Information: Selecting D register equation as minimal for signal \dacwr:dac_hold_7\ Information: Selecting T register equation as minimal for signal \dacwr:dac_hold_8\ Information: Selecting T register equation as minimal for signal \dacwr:dac_hold_9\ Information: Selecting D register equation as minimal for signal \dacwr:dac_stateSBV_0\ Information: Selecting T register equation as minimal for signal \dacwr:dac_stateSBV_1\ Information: Selecting D register equation as minimal for signal \dacwr:dac_stateSBV_2\ Information: Selecting D register equation as minimal for signal \dacwr:timeout_0\ Information: Selecting D register equation as minimal for signal \dacwr:timeout_1\ Information: Selecting T register equation as minimal for signal \dacwr:timeout_2\ Information: Selecting D register equation as minimal for signal \rio:il_read_stateSBV_0\ Information: Selecting D register equation as minimal for signal \rio:il_read_stateSBV_1\ Information: Selecting D register equation as minimal for signal \rio:il_read_stateSBV_2\ Information: Selecting D register equation as minimal for signal \spg:current_count_0\ Information: Selecting D register equation as minimal for signal \spg:current_count_1\ Information: Selecting T register equation as minimal for signal \spg:current_count_2\ Information: Selecting T register equation as minimal for signal \spg:current_count_3\ Information: Selecting T register equation as minimal for signal \spg:current_count_4\ Information: Selecting T register equation as minimal for signal \spg:current_count_5\ Information: Selecting T register equation as minimal for signal \spg:current_count_6\ Information: Selecting T register equation as minimal for signal \spg:current_count_7\ Information: Selecting T register equation as minimal for signal \spg:current_count_8\ Information: Selecting T register equation as minimal for signal \spg:current_count_9\ Information: Selecting D register equation as minimal for signal \spg:current_phase_0\ Information: Selecting T register equation as minimal for signal \spg:current_phase_10\ Information: Selecting T register equation as minimal for signal \spg:current_phase_11\ Information: Selecting T register equation as minimal for signal \spg:current_phase_12\ Information: Selecting D register equation as minimal for signal \spg:current_phase_1\ Information: Selecting T register equation as minimal for signal \spg:current_phase_2\ Information: Selecting T register equation as minimal for signal \spg:current_phase_3\ Information: Selecting T register equation as minimal for signal \spg:current_phase_4\ Information: Selecting T register equation as minimal for signal \spg:current_phase_5\ Information: Selecting T register equation as minimal for signal \spg:current_phase_6\ Information: Selecting T register equation as minimal for signal \spg:current_phase_7\ Information: Selecting T register equation as minimal for signal \spg:current_phase_8\ Information: Selecting T register equation as minimal for signal \spg:current_phase_9\ Information: Selecting T register equation as minimal for signal \spg:iclk\ Information: Selecting D register equation as minimal for signal \spg:kdacSBV_0\ Information: Selecting D register equation as minimal for signal \spg:kick_dac\ Information: Selecting D register equation as minimal for signal \spg:precount_0\ Information: Selecting D register equation as minimal for signal \spg:precount_1\ Information: Selecting T register equation as minimal for signal \spg:precount_2\ Information: Selecting T register equation as minimal for signal \spg:precount_3\ Information: Selecting D register equation as minimal for signal \spg:sample_0\ Information: Selecting T register equation as minimal for signal \spg:sample_1\ Information: Selecting T register equation as minimal for signal \spg:sample_2\ Information: Selecting T register equation as minimal for signal address_from_pc_0 Information: Selecting T register equation as minimal for signal address_from_pc_1 Information: Selecting T register equation as minimal for signal address_from_pc_2 Information: Selecting T register equation as minimal for signal address_from_pc_3 Information: Selecting T register equation as minimal for signal dac_data_from_pc_0 Information: Selecting T register equation as minimal for signal dac_data_from_pc_1 Information: Selecting T register equation as minimal for signal dac_data_from_pc_10 Information: Selecting T register equation as minimal for signal dac_data_from_pc_11 Information: Selecting T register equation as minimal for signal dac_data_from_pc_12 Information: Selecting T register equation as minimal for signal dac_data_from_pc_15 Information: Selecting T register equation as minimal for signal dac_data_from_pc_2 Information: Selecting T register equation as minimal for signal dac_data_from_pc_3 Information: Selecting T register equation as minimal for signal dac_data_from_pc_4 Information: Selecting T register equation as minimal for signal dac_data_from_pc_5 Information: Selecting T register equation as minimal for signal dac_data_from_pc_6 Information: Selecting T register equation as minimal for signal dac_data_from_pc_7 Information: Selecting T register equation as minimal for signal dac_data_from_pc_8 Information: Selecting T register equation as minimal for signal dac_data_from_pc_9 Information: Selecting T register equation as minimal for signal phase1_0 Information: Selecting T register equation as minimal for signal phase1_1 Information: Selecting T register equation as minimal for signal phase1_10 Information: Selecting T register equation as minimal for signal phase1_11 Information: Selecting T register equation as minimal for signal phase1_12 Information: Selecting T register equation as minimal for signal phase1_2 Information: Selecting T register equation as minimal for signal phase1_3 Information: Selecting T register equation as minimal for signal phase1_4 Information: Selecting T register equation as minimal for signal phase1_5 Information: Selecting T register equation as minimal for signal phase1_6 Information: Selecting T register equation as minimal for signal phase1_7 Information: Selecting T register equation as minimal for signal phase1_8 Information: Selecting T register equation as minimal for signal phase1_9 Information: Selecting T register equation as minimal for signal phase2_0 Information: Selecting T register equation as minimal for signal phase2_1 Information: Selecting T register equation as minimal for signal phase2_10 Information: Selecting T register equation as minimal for signal phase2_11 Information: Selecting T register equation as minimal for signal phase2_12 Information: Selecting T register equation as minimal for signal phase2_2 Information: Selecting T register equation as minimal for signal phase2_3 Information: Selecting T register equation as minimal for signal phase2_4 Information: Selecting T register equation as minimal for signal phase2_5 Information: Selecting T register equation as minimal for signal phase2_6 Information: Selecting T register equation as minimal for signal phase2_7 Information: Selecting T register equation as minimal for signal phase2_8 Information: Selecting T register equation as minimal for signal phase2_9 Information: Selecting T register equation as minimal for signal predev_0 Information: Selecting T register equation as minimal for signal predev_1 Information: Selecting T register equation as minimal for signal predev_2 Information: Selecting T register equation as minimal for signal predev_3 Information: Selecting T register equation as minimal for signal shift_0 Information: Selecting T register equation as minimal for signal shift_1 Information: Selecting T register equation as minimal for signal shift_2 Information: Selecting D register equation as minimal for signal sp_ack Information: Selecting D register equation as minimal for signal sp_req Information: Selecting T register equation as minimal for signal steplen_0 Information: Selecting T register equation as minimal for signal steplen_1 Information: Selecting T register equation as minimal for signal steplen_2 Information: Selecting T register equation as minimal for signal steplen_3 Information: Selecting T register equation as minimal for signal steplen_4 Information: Selecting T register equation as minimal for signal steplen_5 Information: Selecting T register equation as minimal for signal steplen_6 Information: Selecting T register equation as minimal for signal steplen_7 Information: Selecting T register equation as minimal for signal steplen_8 Information: Selecting T register equation as minimal for signal steplen_9 Information: Selecting D register equation as minimal for signal to_dac_from_pc_ack Information: Selecting D register equation as minimal for signal to_dac_from_pc_req Information: Selecting T register equation as minimal for signal val0_0 Information: Selecting T register equation as minimal for signal val0_1 Information: Selecting T register equation as minimal for signal val0_2 Information: Selecting T register equation as minimal for signal val0_3 Information: Selecting T register equation as minimal for signal val0_4 Information: Selecting T register equation as minimal for signal val0_5 Information: Selecting T register equation as minimal for signal val0_6 Information: Selecting T register equation as minimal for signal val0_7 Information: Selecting T register equation as minimal for signal val1_0 Information: Selecting T register equation as minimal for signal val1_1 Information: Selecting T register equation as minimal for signal val1_2 Information: Selecting T register equation as minimal for signal val1_3 Information: Selecting T register equation as minimal for signal val1_4 Information: Selecting T register equation as minimal for signal val1_5 Information: Selecting T register equation as minimal for signal val1_6 Information: Selecting T register equation as minimal for signal val1_7 Information: Selecting T register equation as minimal for signal val2_0 Information: Selecting T register equation as minimal for signal val2_1 Information: Selecting T register equation as minimal for signal val2_2 Information: Selecting T register equation as minimal for signal val2_3 Information: Selecting T register equation as minimal for signal val2_4 Information: Selecting T register equation as minimal for signal val2_5 Information: Selecting T register equation as minimal for signal val2_6 Information: Selecting T register equation as minimal for signal val2_7 Information: Selecting T register equation as minimal for signal val3_0 Information: Selecting T register equation as minimal for signal val3_1 Information: Selecting T register equation as minimal for signal val3_2 Information: Selecting T register equation as minimal for signal val3_3 Information: Selecting T register equation as minimal for signal val3_4 Information: Selecting T register equation as minimal for signal val3_5 Information: Selecting T register equation as minimal for signal val3_6 Information: Selecting T register equation as minimal for signal val3_7 Information: Selecting T register equation as minimal for signal val4_0 Information: Selecting T register equation as minimal for signal val4_1 Information: Selecting T register equation as minimal for signal val4_2 Information: Selecting T register equation as minimal for signal val4_3 Information: Selecting T register equation as minimal for signal val4_4 Information: Selecting T register equation as minimal for signal val4_5 Information: Selecting T register equation as minimal for signal val4_6 Information: Selecting T register equation as minimal for signal val4_7 Information: Selecting T register equation as minimal for signal val5_0 Information: Selecting T register equation as minimal for signal val5_1 Information: Selecting T register equation as minimal for signal val5_2 Information: Selecting T register equation as minimal for signal val5_3 Information: Selecting T register equation as minimal for signal val5_4 Information: Selecting T register equation as minimal for signal val5_5 Information: Selecting T register equation as minimal for signal val5_6 Information: Selecting T register equation as minimal for signal val5_7 Information: Selecting T register equation as minimal for signal val6_0 Information: Selecting T register equation as minimal for signal val6_1 Information: Selecting T register equation as minimal for signal val6_2 Information: Selecting T register equation as minimal for signal val6_3 Information: Selecting T register equation as minimal for signal val6_4 Information: Selecting T register equation as minimal for signal val6_5 Information: Selecting T register equation as minimal for signal val6_6 Information: Selecting T register equation as minimal for signal val6_7 Information: Selecting T register equation as minimal for signal val7_0 Information: Selecting T register equation as minimal for signal val7_1 Information: Selecting T register equation as minimal for signal val7_2 Information: Selecting T register equation as minimal for signal val7_3 Information: Selecting T register equation as minimal for signal val7_4 Information: Selecting T register equation as minimal for signal val7_5 Information: Selecting T register equation as minimal for signal val7_6 Information: Selecting T register equation as minimal for signal val7_7 Information: Selecting D register equation as minimal for signal da_not_wr Information: Selecting T register equation as minimal for signal daaddr(2) Information: Selecting T register equation as minimal for signal daaddr(1) Information: Selecting T register equation as minimal for signal daaddr(0) Information: Selecting D register equation as minimal for signal dad(12) Information: Selecting D register equation as minimal for signal dad(11) Information: Selecting D register equation as minimal for signal dad(10) Information: Selecting D register equation as minimal for signal dad(9) Information: Selecting D register equation as minimal for signal dad(8) Information: Selecting D register equation as minimal for signal dad(7) Information: Selecting D register equation as minimal for signal dad(6) Information: Selecting D register equation as minimal for signal dad(5) Information: Selecting D register equation as minimal for signal dad(4) Information: Selecting D register equation as minimal for signal dad(3) Information: Selecting D register equation as minimal for signal dad(2) Information: Selecting D register equation as minimal for signal dad(1) Information: Selecting D register equation as minimal for signal dad(0) Information: Selecting D register equation as minimal for signal sinphase_zeros Information: Selecting D register equation as minimal for signal ao_from_pc_ack Information: Selecting D register equation as minimal for signal \rio:this_is_a_ctrl_transaction\ Information: Selecting T register equation as minimal for signal this_chip_selected Information: Selecting D register equation as minimal for signal da_not_clr Information: Selecting D register equation as minimal for signal da_not_cs Information: Optimizing logic without changing polarity for signals: \dacwr:cmp_vv_us_MODGEN_10\ \dacwr:dac_hold_0\.D \dacwr:dac_hold_10\.T \dacwr:dac_hold_11\.T \dacwr:dac_hold_12\.T \dacwr:dac_hold_1\.D \dacwr:dac_hold_2\.D \dacwr:dac_hold_3\.D \dacwr:dac_hold_4\.D \dacwr:dac_hold_5\.D \dacwr:dac_hold_6\.D \dacwr:dac_hold_7\.D \dacwr:dac_hold_8\.T \dacwr:dac_hold_9\.T \dacwr:dac_stateSBV_0\.D \dacwr:dac_stateSBV_1\.T \dacwr:dac_stateSBV_2\.D \dacwr:timeout_0\.D \dacwr:timeout_1\.D \dacwr:timeout_2\.T \rio:il_read_stateSBV_0\.D \rio:il_read_stateSBV_1\.D \rio:il_read_stateSBV_2\.D \rio:this_is_a_ctrl_transaction\.D \spg:MODULE_3:g1:a0:gx:u0:eq_5\ \spg:MODULE_3:g1:a0:gx:u0:geq(0):c3:u1\ \spg:MODULE_7:g1:a0:gx:u0:eq_5\ \spg:MODULE_7:g1:a0:gx:u0:geq(0):c3:u1\ \spg:MODULE_8:g1:a0:gx:u0:eq_5\ \spg:MODULE_8:g1:a0:gx:u0:geq(0):c3:u1\ \spg:cmp_vv_us_MODGEN_1\ \spg:cmp_vv_us_MODGEN_3\ \spg:cmp_vv_us_MODGEN_8\ \spg:current_count_0\.D \spg:current_count_1\.D \spg:current_count_2\.T \spg:current_count_3\.T \spg:current_count_4\.T \spg:current_count_5\.T \spg:current_count_6\.T \spg:current_count_7\.T \spg:current_count_8\.T \spg:current_count_9\.T \spg:current_phase_0\.D \spg:current_phase_10\.T \spg:current_phase_11\.T \spg:current_phase_12\.T \spg:current_phase_1\.D \spg:current_phase_2\.T \spg:current_phase_3\.T \spg:current_phase_4\.T \spg:current_phase_5\.T \spg:current_phase_6\.T \spg:current_phase_7\.T \spg:current_phase_8\.T \spg:current_phase_9\.T \spg:iclk\.T \spg:kdacSBV_0\.D \spg:kick_dac\.D \spg:precount_0\.D \spg:precount_1\.D \spg:precount_2\.T \spg:precount_3\.T \spg:sample_0\.D \spg:sample_1\.T \spg:sample_2\.T address_from_pc_0.T address_from_pc_1.T address_from_pc_2.T address_from_pc_3.T ao_from_pc_ack.D da_not_clr.D da_not_cs.D da_not_wr.D daaddr(0).T daaddr(1).T daaddr(2).T dac_data_from_pc_0.T dac_data_from_pc_1.T dac_data_from_pc_10.T dac_data_from_pc_11.T dac_data_from_pc_12.T dac_data_from_pc_15.T dac_data_from_pc_2.T dac_data_from_pc_3.T dac_data_from_pc_4.T dac_data_from_pc_5.T dac_data_from_pc_6.T dac_data_from_pc_7.T dac_data_from_pc_8.T dac_data_from_pc_9.T dad(0).D dad(1).D dad(10).D dad(11).D dad(12).D dad(2).D dad(3).D dad(4).D dad(5).D dad(6).D dad(7).D dad(8).D dad(9).D phase1_0.T phase1_1.T phase1_10.T phase1_11.T phase1_12.T phase1_2.T phase1_3.T phase1_4.T phase1_5.T phase1_6.T phase1_7.T phase1_8.T phase1_9.T phase2_0.T phase2_1.T phase2_10.T phase2_11.T phase2_12.T phase2_2.T phase2_3.T phase2_4.T phase2_5.T phase2_6.T phase2_7.T phase2_8.T phase2_9.T predev_0.T predev_1.T predev_2.T predev_3.T shift_0.T shift_1.T shift_2.T sinphase_zeros.D sp_ack.D sp_req.D steplen_0.T steplen_1.T steplen_2.T steplen_3.T steplen_4.T steplen_5.T steplen_6.T steplen_7.T steplen_8.T steplen_9.T this_chip_selected.T to_dac_from_pc_ack.D to_dac_from_pc_req.D val0_0.T val0_1.T val0_2.T val0_3.T val0_4.T val0_5.T val0_6.T val0_7.T val1_0.T val1_1.T val1_2.T val1_3.T val1_4.T val1_5.T val1_6.T val1_7.T val2_0.T val2_1.T val2_2.T val2_3.T val2_4.T val2_5.T val2_6.T val2_7.T val3_0.T val3_1.T val3_2.T val3_3.T val3_4.T val3_5.T val3_6.T val3_7.T val4_0.T val4_1.T val4_2.T val4_3.T val4_4.T val4_5.T val4_6.T val4_7.T val5_0.T val5_1.T val5_2.T val5_3.T val5_4.T val5_5.T val5_6.T val5_7.T val6_0.T val6_1.T val6_2.T val6_3.T val6_4.T val6_5.T val6_6.T val6_7.T val7_0.T val7_1.T val7_2.T val7_3.T val7_4.T val7_5.T val7_6.T val7_7.T Information: Optimizing logic using best output polarity for signals: S_1 S_2 Information: Selected logic optimization OFF for signals: \dacwr:dac_hold_0\.C \dacwr:dac_hold_10\.C \dacwr:dac_hold_11\.C \dacwr:dac_hold_12\.C \dacwr:dac_hold_1\.C \dacwr:dac_hold_2\.C \dacwr:dac_hold_3\.C \dacwr:dac_hold_4\.C \dacwr:dac_hold_5\.C \dacwr:dac_hold_6\.C \dacwr:dac_hold_7\.C \dacwr:dac_hold_8\.C \dacwr:dac_hold_9\.C \dacwr:dac_stateSBV_0\.C \dacwr:dac_stateSBV_1\.C \dacwr:dac_stateSBV_2\.C \dacwr:timeout_0\.C \dacwr:timeout_1\.C \dacwr:timeout_2\.C \rio:il_read_stateSBV_0\.C \rio:il_read_stateSBV_1\.C \rio:il_read_stateSBV_2\.C \rio:this_is_a_ctrl_transaction\.AP \rio:this_is_a_ctrl_transaction\.AR \rio:this_is_a_ctrl_transaction\.C \spg:cmp_vv_us_MODGEN_4\ \spg:current_count_0\.C \spg:current_count_1\.C \spg:current_count_2\.C \spg:current_count_3\.C \spg:current_count_4\.C \spg:current_count_5\.C \spg:current_count_6\.C \spg:current_count_7\.C \spg:current_count_8\.C \spg:current_count_9\.C \spg:current_phase_0\.C \spg:current_phase_10\.C \spg:current_phase_11\.C \spg:current_phase_12\.C \spg:current_phase_1\.C \spg:current_phase_2\.C \spg:current_phase_3\.C \spg:current_phase_4\.C \spg:current_phase_5\.C \spg:current_phase_6\.C \spg:current_phase_7\.C \spg:current_phase_8\.C \spg:current_phase_9\.C \spg:iclk\.C \spg:kdacSBV_0\.C \spg:kick_dac\.C \spg:precount_0\.C \spg:precount_1\.C \spg:precount_2\.C \spg:precount_3\.C \spg:sample_0\.C \spg:sample_1\.C \spg:sample_2\.C address_from_pc_0.C address_from_pc_1.C address_from_pc_2.C address_from_pc_3.C ao_from_pc_ack.C ao_from_pc_ack.OE da_not_clr.AP da_not_clr.AR da_not_clr.C da_not_cs.AP da_not_cs.AR da_not_cs.C da_not_ldab da_not_ldcd da_not_ldef da_not_ldgh da_not_wr.C daaddr(0).C daaddr(1).C daaddr(2).C dac_data_from_pc_0.C dac_data_from_pc_1.C dac_data_from_pc_10.C dac_data_from_pc_11.C dac_data_from_pc_12.C dac_data_from_pc_15.C dac_data_from_pc_2.C dac_data_from_pc_3.C dac_data_from_pc_4.C dac_data_from_pc_5.C dac_data_from_pc_6.C dac_data_from_pc_7.C dac_data_from_pc_8.C dac_data_from_pc_9.C dad(0).C dad(1).C dad(10).C dad(11).C dad(12).C dad(2).C dad(3).C dad(4).C dad(5).C dad(6).C dad(7).C dad(8).C dad(9).C dio_tristate phase1_0.C phase1_1.C phase1_10.C phase1_11.C phase1_12.C phase1_2.C phase1_3.C phase1_4.C phase1_5.C phase1_6.C phase1_7.C phase1_8.C phase1_9.C phase2_0.C phase2_1.C phase2_10.C phase2_11.C phase2_12.C phase2_2.C phase2_3.C phase2_4.C phase2_5.C phase2_6.C phase2_7.C phase2_8.C phase2_9.C predev_0.C predev_1.C predev_2.C predev_3.C shdn(0) shdn(1) shdn(2) shift_0.C shift_1.C shift_2.C sinphase_zeros.C sp_ack.C sp_req.C steplen_0.C steplen_1.C steplen_2.C steplen_3.C steplen_4.C steplen_5.C steplen_6.C steplen_7.C steplen_8.C steplen_9.C this_chip_selected.AP this_chip_selected.AR this_chip_selected.C to_dac_from_pc_ack.C to_dac_from_pc_req.C val0_0.C val0_1.C val0_2.C val0_3.C val0_4.C val0_5.C val0_6.C val0_7.C val1_0.C val1_1.C val1_2.C val1_3.C val1_4.C val1_5.C val1_6.C val1_7.C val2_0.C val2_1.C val2_2.C val2_3.C val2_4.C val2_5.C val2_6.C val2_7.C val3_0.C val3_1.C val3_2.C val3_3.C val3_4.C val3_5.C val3_6.C val3_7.C val4_0.C val4_1.C val4_2.C val4_3.C val4_4.C val4_5.C val4_6.C val4_7.C val5_0.C val5_1.C val5_2.C val5_3.C val5_4.C val5_5.C val5_6.C val5_7.C val6_0.C val6_1.C val6_2.C val6_3.C val6_4.C val6_5.C val6_6.C val6_7.C val7_0.C val7_1.C val7_2.C val7_3.C val7_4.C val7_5.C val7_6.C val7_7.C Summary: Error Count = 0 Warning Count = 0 Completed Successfully ---------------------------------------------------------------------------- PLD Optimizer Software: MINOPT.EXE 01/NOV/1999 [v4.02 ] 6.0.1 IR 18 LOGIC MINIMIZATION () Messages: Summary: Error Count = 0 Warning Count = 0 Completed Successfully ---------------------------------------------------------------------------- PLD Optimizer Software: DSGNOPT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 OPTIMIZATION OPTIONS (17:51:39) Messages: Summary: Error Count = 0 Warning Count = 0 Completed Successfully ---------------------------------------------------------------------------- PLD Compiler Software: C37KFIT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 DESIGN EQUATIONS (17:51:42) S_1 = /\spg:cmp_vv_us_MODGEN_3\.CMB * \spg:cmp_vv_us_MODGEN_8\.CMB * /\spg:current_phase_8\.Q * phase1_8.Q + /\spg:cmp_vv_us_MODGEN_3\.CMB * \spg:cmp_vv_us_MODGEN_8\.CMB * \spg:current_phase_8\.Q * /phase1_8.Q + /\spg:current_phase_8\.Q * phase1_8.Q * /sinphase_zeros.Q + \spg:current_phase_12\.Q * /phase1_12.Q * /sinphase_zeros.Q + \spg:current_phase_8\.Q * /phase1_8.Q * /sinphase_zeros.Q + \spg:cmp_vv_us_MODGEN_3\.CMB * /sinphase_zeros.Q + /\spg:MODULE_7:g1:a0:gx:u0:geq(0):c3:u1\.CMB * /sinphase_zeros.Q S_2 = /\spg:cmp_vv_us_MODGEN_3\.CMB * \spg:cmp_vv_us_MODGEN_8\.CMB * /\spg:current_phase_10\.Q * phase1_10.Q + /\spg:cmp_vv_us_MODGEN_3\.CMB * \spg:cmp_vv_us_MODGEN_8\.CMB * /\spg:current_phase_11\.Q * phase1_11.Q + /\spg:cmp_vv_us_MODGEN_3\.CMB * \spg:cmp_vv_us_MODGEN_8\.CMB * /\spg:current_phase_12\.Q * phase1_12.Q + /\spg:cmp_vv_us_MODGEN_3\.CMB * \spg:cmp_vv_us_MODGEN_8\.CMB * /\spg:current_phase_9\.Q * phase1_9.Q + /\spg:cmp_vv_us_MODGEN_3\.CMB * \spg:cmp_vv_us_MODGEN_8\.CMB * \spg:current_phase_10\.Q * /phase1_10.Q + /\spg:cmp_vv_us_MODGEN_3\.CMB * \spg:cmp_vv_us_MODGEN_8\.CMB * \spg:current_phase_11\.Q * /phase1_11.Q + /\spg:cmp_vv_us_MODGEN_3\.CMB * \spg:cmp_vv_us_MODGEN_8\.CMB * \spg:current_phase_12\.Q * /phase1_12.Q + /\spg:cmp_vv_us_MODGEN_3\.CMB * \spg:cmp_vv_us_MODGEN_8\.CMB * \spg:current_phase_9\.Q * /phase1_9.Q + /\spg:MODULE_7:g1:a0:gx:u0:geq(0):c3:u1\.CMB * /\spg:cmp_vv_us_MODGEN_3\.CMB * \spg:cmp_vv_us_MODGEN_8\.CMB + /\spg:current_phase_10\.Q * phase1_10.Q * /sinphase_zeros.Q + /\spg:current_phase_11\.Q * phase1_11.Q * /sinphase_zeros.Q + /\spg:current_phase_12\.Q * phase1_12.Q * /sinphase_zeros.Q + /\spg:current_phase_9\.Q * phase1_9.Q * /sinphase_zeros.Q + \spg:current_phase_10\.Q * /phase1_10.Q * /sinphase_zeros.Q + \spg:current_phase_11\.Q * /phase1_11.Q * /sinphase_zeros.Q + \spg:current_phase_9\.Q * /phase1_9.Q * /sinphase_zeros.Q /\dacwr:cmp_vv_us_MODGEN_10\ = /\dacwr:timeout_0\.Q * shift_0.Q + /\dacwr:timeout_1\.Q * shift_1.Q + /\dacwr:timeout_2\.Q * shift_2.Q + \dacwr:timeout_0\.Q * /shift_0.Q + \dacwr:timeout_1\.Q * /shift_1.Q + \dacwr:timeout_2\.Q * /shift_2.Q \dacwr:dac_hold_0\.D = /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * \spg:sample_0\.Q * \spg:sample_1\.Q * \spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val7_0.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * /\spg:sample_0\.Q * \spg:sample_1\.Q * \spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val6_0.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * \spg:sample_0\.Q * /\spg:sample_1\.Q * \spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val5_0.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * /\spg:sample_0\.Q * /\spg:sample_1\.Q * \spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val4_0.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * \spg:sample_0\.Q * \spg:sample_1\.Q * /\spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val3_0.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * /\spg:sample_0\.Q * \spg:sample_1\.Q * /\spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val2_0.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * \spg:sample_0\.Q * /\spg:sample_1\.Q * /\spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val1_0.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * /\spg:sample_0\.Q * /\spg:sample_1\.Q * /\spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val0_0.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * dac_data_from_pc_0.Q * to_dac_from_pc_req.Q + \dacwr:dac_hold_0\.Q * /\dacwr:dac_stateSBV_2\.Q * /sp_req.Q * /to_dac_from_pc_req.Q + \dacwr:cmp_vv_us_MODGEN_10\.CMB * \dacwr:dac_hold_0\.Q * \dacwr:dac_stateSBV_2\.Q + \dacwr:dac_hold_0\.Q * /\dacwr:dac_stateSBV_1\.Q * \dacwr:dac_stateSBV_2\.Q + \dacwr:dac_hold_0\.Q * \dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q + \dacwr:dac_hold_0\.Q * \dacwr:dac_stateSBV_0\.Q \dacwr:dac_hold_0\.C = clk \dacwr:dac_hold_10\.T = /\dacwr:cmp_vv_us_MODGEN_10\.CMB * \dacwr:dac_hold_10\.Q * /\dacwr:dac_hold_9\.Q * /\dacwr:dac_stateSBV_0\.Q * \dacwr:dac_stateSBV_1\.Q * \dacwr:dac_stateSBV_2\.Q + /\dacwr:dac_hold_10\.Q * /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * dac_data_from_pc_10.Q * to_dac_from_pc_req.Q + \dacwr:dac_hold_10\.Q * /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * /dac_data_from_pc_10.Q * to_dac_from_pc_req.Q + \dacwr:dac_hold_10\.Q * /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q + /\dacwr:cmp_vv_us_MODGEN_10\.CMB * /\dacwr:dac_hold_10\.Q * \dacwr:dac_hold_9\.Q * \dacwr:dac_stateSBV_1\.Q * \dacwr:dac_stateSBV_2\.Q \dacwr:dac_hold_10\.C = clk \dacwr:dac_hold_11\.T = /\dacwr:cmp_vv_us_MODGEN_10\.CMB * /\dacwr:dac_hold_10\.Q * \dacwr:dac_hold_11\.Q * /\dacwr:dac_stateSBV_0\.Q * \dacwr:dac_stateSBV_1\.Q * \dacwr:dac_stateSBV_2\.Q + /\dacwr:dac_hold_11\.Q * /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * dac_data_from_pc_11.Q * to_dac_from_pc_req.Q + \dacwr:dac_hold_11\.Q * /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * /dac_data_from_pc_11.Q * to_dac_from_pc_req.Q + \dacwr:dac_hold_11\.Q * /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q + /\dacwr:cmp_vv_us_MODGEN_10\.CMB * \dacwr:dac_hold_10\.Q * /\dacwr:dac_hold_11\.Q * \dacwr:dac_stateSBV_1\.Q * \dacwr:dac_stateSBV_2\.Q \dacwr:dac_hold_11\.C = clk \dacwr:dac_hold_12\.T = /\dacwr:cmp_vv_us_MODGEN_10\.CMB * /\dacwr:dac_hold_11\.Q * \dacwr:dac_hold_12\.Q * /\dacwr:dac_stateSBV_0\.Q * \dacwr:dac_stateSBV_1\.Q * \dacwr:dac_stateSBV_2\.Q + /\dacwr:dac_hold_12\.Q * /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * dac_data_from_pc_12.Q * to_dac_from_pc_req.Q + \dacwr:dac_hold_12\.Q * /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * /dac_data_from_pc_12.Q * to_dac_from_pc_req.Q + \dacwr:dac_hold_12\.Q * /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q + \dacwr:cmp_vv_us_MODGEN_10\.CMB * /\dacwr:dac_hold_12\.Q * \dacwr:dac_stateSBV_1\.Q * \dacwr:dac_stateSBV_2\.Q * shift_1.Q + /\dacwr:cmp_vv_us_MODGEN_10\.CMB * \dacwr:dac_hold_11\.Q * /\dacwr:dac_hold_12\.Q * \dacwr:dac_stateSBV_1\.Q * \dacwr:dac_stateSBV_2\.Q + \dacwr:cmp_vv_us_MODGEN_10\.CMB * /\dacwr:dac_hold_12\.Q * \dacwr:dac_stateSBV_1\.Q * \dacwr:dac_stateSBV_2\.Q * /shift_0.Q + \dacwr:cmp_vv_us_MODGEN_10\.CMB * /\dacwr:dac_hold_12\.Q * \dacwr:dac_stateSBV_1\.Q * \dacwr:dac_stateSBV_2\.Q * /shift_2.Q \dacwr:dac_hold_12\.C = clk \dacwr:dac_hold_1\.D = /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * \spg:sample_0\.Q * \spg:sample_1\.Q * \spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val7_1.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * /\spg:sample_0\.Q * \spg:sample_1\.Q * \spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val6_1.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * \spg:sample_0\.Q * /\spg:sample_1\.Q * \spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val5_1.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * /\spg:sample_0\.Q * /\spg:sample_1\.Q * \spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val4_1.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * \spg:sample_0\.Q * \spg:sample_1\.Q * /\spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val3_1.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * /\spg:sample_0\.Q * \spg:sample_1\.Q * /\spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val2_1.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * \spg:sample_0\.Q * /\spg:sample_1\.Q * /\spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val1_1.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * /\spg:sample_0\.Q * /\spg:sample_1\.Q * /\spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val0_1.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * dac_data_from_pc_1.Q * to_dac_from_pc_req.Q + /\dacwr:cmp_vv_us_MODGEN_10\.CMB * \dacwr:dac_hold_0\.Q * \dacwr:dac_stateSBV_1\.Q * \dacwr:dac_stateSBV_2\.Q + \dacwr:dac_hold_1\.Q * /\dacwr:dac_stateSBV_2\.Q * /sp_req.Q * /to_dac_from_pc_req.Q + \dacwr:cmp_vv_us_MODGEN_10\.CMB * \dacwr:dac_hold_1\.Q * \dacwr:dac_stateSBV_2\.Q + \dacwr:dac_hold_1\.Q * /\dacwr:dac_stateSBV_1\.Q * \dacwr:dac_stateSBV_2\.Q + \dacwr:dac_hold_1\.Q * \dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q + \dacwr:dac_hold_1\.Q * \dacwr:dac_stateSBV_0\.Q \dacwr:dac_hold_1\.C = clk \dacwr:dac_hold_2\.D = /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * \spg:sample_0\.Q * \spg:sample_1\.Q * \spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val7_2.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * /\spg:sample_0\.Q * \spg:sample_1\.Q * \spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val6_2.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * \spg:sample_0\.Q * /\spg:sample_1\.Q * \spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val5_2.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * /\spg:sample_0\.Q * /\spg:sample_1\.Q * \spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val4_2.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * \spg:sample_0\.Q * \spg:sample_1\.Q * /\spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val3_2.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * /\spg:sample_0\.Q * \spg:sample_1\.Q * /\spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val2_2.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * \spg:sample_0\.Q * /\spg:sample_1\.Q * /\spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val1_2.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * /\spg:sample_0\.Q * /\spg:sample_1\.Q * /\spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val0_2.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * dac_data_from_pc_2.Q * to_dac_from_pc_req.Q + /\dacwr:cmp_vv_us_MODGEN_10\.CMB * \dacwr:dac_hold_1\.Q * \dacwr:dac_stateSBV_1\.Q * \dacwr:dac_stateSBV_2\.Q + \dacwr:dac_hold_2\.Q * /\dacwr:dac_stateSBV_2\.Q * /sp_req.Q * /to_dac_from_pc_req.Q + \dacwr:cmp_vv_us_MODGEN_10\.CMB * \dacwr:dac_hold_2\.Q * \dacwr:dac_stateSBV_2\.Q + \dacwr:dac_hold_2\.Q * /\dacwr:dac_stateSBV_1\.Q * \dacwr:dac_stateSBV_2\.Q + \dacwr:dac_hold_2\.Q * \dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q + \dacwr:dac_hold_2\.Q * \dacwr:dac_stateSBV_0\.Q \dacwr:dac_hold_2\.C = clk \dacwr:dac_hold_3\.D = /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * \spg:sample_0\.Q * \spg:sample_1\.Q * \spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val7_3.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * /\spg:sample_0\.Q * \spg:sample_1\.Q * \spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val6_3.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * \spg:sample_0\.Q * /\spg:sample_1\.Q * \spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val5_3.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * /\spg:sample_0\.Q * /\spg:sample_1\.Q * \spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val4_3.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * \spg:sample_0\.Q * \spg:sample_1\.Q * /\spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val3_3.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * /\spg:sample_0\.Q * \spg:sample_1\.Q * /\spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val2_3.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * \spg:sample_0\.Q * /\spg:sample_1\.Q * /\spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val1_3.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * /\spg:sample_0\.Q * /\spg:sample_1\.Q * /\spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val0_3.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * dac_data_from_pc_3.Q * to_dac_from_pc_req.Q + /\dacwr:cmp_vv_us_MODGEN_10\.CMB * \dacwr:dac_hold_2\.Q * \dacwr:dac_stateSBV_1\.Q * \dacwr:dac_stateSBV_2\.Q + \dacwr:dac_hold_3\.Q * /\dacwr:dac_stateSBV_2\.Q * /sp_req.Q * /to_dac_from_pc_req.Q + \dacwr:cmp_vv_us_MODGEN_10\.CMB * \dacwr:dac_hold_3\.Q * \dacwr:dac_stateSBV_2\.Q + \dacwr:dac_hold_3\.Q * /\dacwr:dac_stateSBV_1\.Q * \dacwr:dac_stateSBV_2\.Q + \dacwr:dac_hold_3\.Q * \dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q + \dacwr:dac_hold_3\.Q * \dacwr:dac_stateSBV_0\.Q \dacwr:dac_hold_3\.C = clk \dacwr:dac_hold_4\.D = /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * \spg:sample_0\.Q * \spg:sample_1\.Q * \spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val7_4.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * /\spg:sample_0\.Q * \spg:sample_1\.Q * \spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val6_4.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * \spg:sample_0\.Q * /\spg:sample_1\.Q * \spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val5_4.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * /\spg:sample_0\.Q * /\spg:sample_1\.Q * \spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val4_4.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * \spg:sample_0\.Q * \spg:sample_1\.Q * /\spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val3_4.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * /\spg:sample_0\.Q * \spg:sample_1\.Q * /\spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val2_4.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * \spg:sample_0\.Q * /\spg:sample_1\.Q * /\spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val1_4.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * /\spg:sample_0\.Q * /\spg:sample_1\.Q * /\spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val0_4.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * dac_data_from_pc_4.Q * to_dac_from_pc_req.Q + /\dacwr:cmp_vv_us_MODGEN_10\.CMB * \dacwr:dac_hold_3\.Q * \dacwr:dac_stateSBV_1\.Q * \dacwr:dac_stateSBV_2\.Q + \dacwr:dac_hold_4\.Q * /\dacwr:dac_stateSBV_2\.Q * /sp_req.Q * /to_dac_from_pc_req.Q + \dacwr:cmp_vv_us_MODGEN_10\.CMB * \dacwr:dac_hold_4\.Q * \dacwr:dac_stateSBV_2\.Q + \dacwr:dac_hold_4\.Q * /\dacwr:dac_stateSBV_1\.Q * \dacwr:dac_stateSBV_2\.Q + \dacwr:dac_hold_4\.Q * \dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q + \dacwr:dac_hold_4\.Q * \dacwr:dac_stateSBV_0\.Q \dacwr:dac_hold_4\.C = clk \dacwr:dac_hold_5\.D = /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * \spg:sample_0\.Q * \spg:sample_1\.Q * \spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val7_5.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * /\spg:sample_0\.Q * \spg:sample_1\.Q * \spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val6_5.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * \spg:sample_0\.Q * /\spg:sample_1\.Q * \spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val5_5.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * /\spg:sample_0\.Q * /\spg:sample_1\.Q * \spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val4_5.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * \spg:sample_0\.Q * \spg:sample_1\.Q * /\spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val3_5.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * /\spg:sample_0\.Q * \spg:sample_1\.Q * /\spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val2_5.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * \spg:sample_0\.Q * /\spg:sample_1\.Q * /\spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val1_5.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * /\spg:sample_0\.Q * /\spg:sample_1\.Q * /\spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val0_5.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * dac_data_from_pc_5.Q * to_dac_from_pc_req.Q + /\dacwr:cmp_vv_us_MODGEN_10\.CMB * \dacwr:dac_hold_4\.Q * \dacwr:dac_stateSBV_1\.Q * \dacwr:dac_stateSBV_2\.Q + \dacwr:dac_hold_5\.Q * /\dacwr:dac_stateSBV_2\.Q * /sp_req.Q * /to_dac_from_pc_req.Q + \dacwr:cmp_vv_us_MODGEN_10\.CMB * \dacwr:dac_hold_5\.Q * \dacwr:dac_stateSBV_2\.Q + \dacwr:dac_hold_5\.Q * /\dacwr:dac_stateSBV_1\.Q * \dacwr:dac_stateSBV_2\.Q + \dacwr:dac_hold_5\.Q * \dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q + \dacwr:dac_hold_5\.Q * \dacwr:dac_stateSBV_0\.Q \dacwr:dac_hold_5\.C = clk \dacwr:dac_hold_6\.D = /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * \spg:sample_0\.Q * \spg:sample_1\.Q * \spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val7_6.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * /\spg:sample_0\.Q * \spg:sample_1\.Q * \spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val6_6.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * \spg:sample_0\.Q * /\spg:sample_1\.Q * \spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val5_6.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * /\spg:sample_0\.Q * /\spg:sample_1\.Q * \spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val4_6.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * \spg:sample_0\.Q * \spg:sample_1\.Q * /\spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val3_6.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * /\spg:sample_0\.Q * \spg:sample_1\.Q * /\spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val2_6.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * \spg:sample_0\.Q * /\spg:sample_1\.Q * /\spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val1_6.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * /\spg:sample_0\.Q * /\spg:sample_1\.Q * /\spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val0_6.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * dac_data_from_pc_6.Q * to_dac_from_pc_req.Q + /\dacwr:cmp_vv_us_MODGEN_10\.CMB * \dacwr:dac_hold_5\.Q * \dacwr:dac_stateSBV_1\.Q * \dacwr:dac_stateSBV_2\.Q + \dacwr:dac_hold_6\.Q * /\dacwr:dac_stateSBV_2\.Q * /sp_req.Q * /to_dac_from_pc_req.Q + \dacwr:cmp_vv_us_MODGEN_10\.CMB * \dacwr:dac_hold_6\.Q * \dacwr:dac_stateSBV_2\.Q + \dacwr:dac_hold_6\.Q * /\dacwr:dac_stateSBV_1\.Q * \dacwr:dac_stateSBV_2\.Q + \dacwr:dac_hold_6\.Q * \dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q + \dacwr:dac_hold_6\.Q * \dacwr:dac_stateSBV_0\.Q \dacwr:dac_hold_6\.C = clk \dacwr:dac_hold_7\.D = /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * \spg:sample_0\.Q * \spg:sample_1\.Q * \spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val7_7.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * /\spg:sample_0\.Q * \spg:sample_1\.Q * \spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val6_7.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * \spg:sample_0\.Q * /\spg:sample_1\.Q * \spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val5_7.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * /\spg:sample_0\.Q * /\spg:sample_1\.Q * \spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val4_7.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * \spg:sample_0\.Q * \spg:sample_1\.Q * /\spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val3_7.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * /\spg:sample_0\.Q * \spg:sample_1\.Q * /\spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val2_7.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * \spg:sample_0\.Q * /\spg:sample_1\.Q * /\spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val1_7.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * /\spg:sample_0\.Q * /\spg:sample_1\.Q * /\spg:sample_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q * val0_7.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * dac_data_from_pc_7.Q * to_dac_from_pc_req.Q + /\dacwr:cmp_vv_us_MODGEN_10\.CMB * \dacwr:dac_hold_6\.Q * \dacwr:dac_stateSBV_1\.Q * \dacwr:dac_stateSBV_2\.Q + \dacwr:dac_hold_7\.Q * /\dacwr:dac_stateSBV_2\.Q * /sp_req.Q * /to_dac_from_pc_req.Q + \dacwr:cmp_vv_us_MODGEN_10\.CMB * \dacwr:dac_hold_7\.Q * \dacwr:dac_stateSBV_2\.Q + \dacwr:dac_hold_7\.Q * /\dacwr:dac_stateSBV_1\.Q * \dacwr:dac_stateSBV_2\.Q + \dacwr:dac_hold_7\.Q * \dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q + \dacwr:dac_hold_7\.Q * \dacwr:dac_stateSBV_0\.Q \dacwr:dac_hold_7\.C = clk \dacwr:dac_hold_8\.T = /\dacwr:cmp_vv_us_MODGEN_10\.CMB * /\dacwr:dac_hold_7\.Q * \dacwr:dac_hold_8\.Q * /\dacwr:dac_stateSBV_0\.Q * \dacwr:dac_stateSBV_1\.Q * \dacwr:dac_stateSBV_2\.Q + /\dacwr:dac_hold_8\.Q * /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * dac_data_from_pc_8.Q * to_dac_from_pc_req.Q + \dacwr:dac_hold_8\.Q * /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * /dac_data_from_pc_8.Q * to_dac_from_pc_req.Q + \dacwr:dac_hold_8\.Q * /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q + /\dacwr:cmp_vv_us_MODGEN_10\.CMB * \dacwr:dac_hold_7\.Q * /\dacwr:dac_hold_8\.Q * \dacwr:dac_stateSBV_1\.Q * \dacwr:dac_stateSBV_2\.Q \dacwr:dac_hold_8\.C = clk \dacwr:dac_hold_9\.T = /\dacwr:cmp_vv_us_MODGEN_10\.CMB * /\dacwr:dac_hold_8\.Q * \dacwr:dac_hold_9\.Q * /\dacwr:dac_stateSBV_0\.Q * \dacwr:dac_stateSBV_1\.Q * \dacwr:dac_stateSBV_2\.Q + /\dacwr:dac_hold_9\.Q * /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * dac_data_from_pc_9.Q * to_dac_from_pc_req.Q + \dacwr:dac_hold_9\.Q * /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * /dac_data_from_pc_9.Q * to_dac_from_pc_req.Q + \dacwr:dac_hold_9\.Q * /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q + /\dacwr:cmp_vv_us_MODGEN_10\.CMB * \dacwr:dac_hold_8\.Q * /\dacwr:dac_hold_9\.Q * \dacwr:dac_stateSBV_1\.Q * \dacwr:dac_stateSBV_2\.Q \dacwr:dac_hold_9\.C = clk \dacwr:dac_stateSBV_0\.D = \dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * /sp_req.Q + /\dacwr:dac_stateSBV_1\.Q * \dacwr:dac_stateSBV_2\.Q * /to_dac_from_pc_req.Q + \dacwr:dac_stateSBV_0\.Q * \dacwr:timeout_1\.Q + \dacwr:dac_stateSBV_0\.Q * \dacwr:timeout_0\.Q + \dacwr:dac_stateSBV_0\.Q * /\dacwr:timeout_2\.Q \dacwr:dac_stateSBV_0\.C = clk \dacwr:dac_stateSBV_1\.T = /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q + \dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * /sp_req.Q \dacwr:dac_stateSBV_1\.C = clk \dacwr:dac_stateSBV_2\.D = /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * sp_req.Q + /\dacwr:cmp_vv_us_MODGEN_10\.CMB * \dacwr:dac_stateSBV_1\.Q * \dacwr:dac_stateSBV_2\.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * to_dac_from_pc_req.Q \dacwr:dac_stateSBV_2\.C = clk \dacwr:timeout_0\.D = /\dacwr:cmp_vv_us_MODGEN_10\.CMB * \dacwr:dac_stateSBV_1\.Q * \dacwr:dac_stateSBV_2\.Q * /\dacwr:timeout_0\.Q + /\dacwr:dac_stateSBV_1\.Q * \dacwr:dac_stateSBV_2\.Q * \dacwr:timeout_0\.Q + \dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * \dacwr:timeout_0\.Q + \dacwr:dac_stateSBV_0\.Q * /\dacwr:timeout_0\.Q * \dacwr:timeout_1\.Q + \dacwr:dac_stateSBV_0\.Q * /\dacwr:timeout_0\.Q * /\dacwr:timeout_2\.Q \dacwr:timeout_0\.C = clk \dacwr:timeout_1\.D = /\dacwr:cmp_vv_us_MODGEN_10\.CMB * \dacwr:dac_stateSBV_1\.Q * \dacwr:dac_stateSBV_2\.Q * \dacwr:timeout_0\.Q * /\dacwr:timeout_1\.Q + /\dacwr:cmp_vv_us_MODGEN_10\.CMB * \dacwr:dac_stateSBV_2\.Q * /\dacwr:timeout_0\.Q * \dacwr:timeout_1\.Q + \dacwr:dac_stateSBV_0\.Q * /\dacwr:timeout_0\.Q * \dacwr:timeout_1\.Q + /\dacwr:dac_stateSBV_1\.Q * \dacwr:dac_stateSBV_2\.Q * \dacwr:timeout_1\.Q + \dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * \dacwr:timeout_1\.Q + \dacwr:dac_stateSBV_0\.Q * \dacwr:timeout_0\.Q * /\dacwr:timeout_1\.Q \dacwr:timeout_1\.C = clk \dacwr:timeout_2\.T = \dacwr:dac_stateSBV_1\.Q * \dacwr:dac_stateSBV_2\.Q * \dacwr:timeout_0\.Q * \dacwr:timeout_1\.Q * \dacwr:timeout_2\.Q + /\dacwr:cmp_vv_us_MODGEN_10\.CMB * \dacwr:dac_stateSBV_1\.Q * \dacwr:dac_stateSBV_2\.Q * \dacwr:timeout_0\.Q * \dacwr:timeout_1\.Q + \dacwr:cmp_vv_us_MODGEN_10\.CMB * /\dacwr:dac_stateSBV_0\.Q * \dacwr:dac_stateSBV_1\.Q * \dacwr:dac_stateSBV_2\.Q * \dacwr:timeout_2\.Q + /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * \dacwr:timeout_0\.Q * \dacwr:timeout_1\.Q * \dacwr:timeout_2\.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * \dacwr:timeout_2\.Q + \dacwr:dac_stateSBV_0\.Q * \dacwr:timeout_0\.Q * \dacwr:timeout_1\.Q * /\dacwr:timeout_2\.Q \dacwr:timeout_2\.C = clk \rio:il_read_stateSBV_0\.D = \rio:il_read_stateSBV_1\.Q * \rio:il_read_stateSBV_2\.Q * /ao_from_pc_strobe + \rio:il_read_stateSBV_0\.Q * \rio:il_read_stateSBV_2\.Q * /to_dac_from_pc_ack.Q \rio:il_read_stateSBV_0\.C = clk \rio:il_read_stateSBV_1\.D = /\rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_1\.Q * \rio:il_read_stateSBV_2\.Q * dac_data_from_pc_10.Q * /dac_data_from_pc_11.Q * dac_data_from_pc_15.Q * /dac_data_from_pc_9.Q + /\rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_1\.Q * \rio:il_read_stateSBV_2\.Q * /dac_data_from_pc_15.Q * this_chip_selected.Q + \rio:il_read_stateSBV_1\.Q * ao_from_pc_strobe \rio:il_read_stateSBV_1\.C = clk \rio:il_read_stateSBV_2\.D = /\rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_1\.Q * \rio:il_read_stateSBV_2\.Q * /dac_data_from_pc_15.Q * this_chip_selected.Q + /\rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_1\.Q * /\rio:il_read_stateSBV_2\.Q * ao_from_pc_strobe + \rio:il_read_stateSBV_1\.Q * \rio:il_read_stateSBV_2\.Q * ao_from_pc_strobe + \rio:il_read_stateSBV_1\.Q * \rio:il_read_stateSBV_2\.Q * /\rio:this_is_a_ctrl_transaction\.Q + \rio:il_read_stateSBV_0\.Q * \rio:il_read_stateSBV_2\.Q * /to_dac_from_pc_ack.Q \rio:il_read_stateSBV_2\.C = clk \rio:this_is_a_ctrl_transaction\.D = /\rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_1\.Q * \rio:il_read_stateSBV_2\.Q * dac_data_from_pc_10.Q * /dac_data_from_pc_11.Q * dac_data_from_pc_15.Q * dac_data_from_pc_8.Q * /dac_data_from_pc_9.Q + \rio:il_read_stateSBV_1\.Q * \rio:this_is_a_ctrl_transaction\.Q + \rio:il_read_stateSBV_0\.Q * \rio:this_is_a_ctrl_transaction\.Q + /\rio:il_read_stateSBV_2\.Q * \rio:this_is_a_ctrl_transaction\.Q + \rio:this_is_a_ctrl_transaction\.Q * /dac_data_from_pc_15.Q \rio:this_is_a_ctrl_transaction\.AP = GND \rio:this_is_a_ctrl_transaction\.AR = reset \rio:this_is_a_ctrl_transaction\.C = clk /\spg:MODULE_3:g1:a0:gx:u0:eq_5\ = /\spg:current_count_0\.Q * steplen_0.Q + /\spg:current_count_1\.Q * steplen_1.Q + /\spg:current_count_2\.Q * steplen_2.Q + /\spg:current_count_3\.Q * steplen_3.Q + /\spg:current_count_4\.Q * steplen_4.Q + /\spg:current_count_5\.Q * steplen_5.Q + \spg:current_count_0\.Q * /steplen_0.Q + \spg:current_count_1\.Q * /steplen_1.Q + \spg:current_count_2\.Q * /steplen_2.Q + \spg:current_count_3\.Q * /steplen_3.Q + \spg:current_count_4\.Q * /steplen_4.Q + \spg:current_count_5\.Q * /steplen_5.Q \spg:MODULE_3:g1:a0:gx:u0:geq(0):c3:u1\ = \spg:MODULE_3:g1:a0:gx:u0:eq_5\.CMB * \spg:current_count_6\.Q * \spg:current_count_7\.Q * steplen_6.Q * steplen_7.Q + \spg:MODULE_3:g1:a0:gx:u0:eq_5\.CMB * /\spg:current_count_6\.Q * \spg:current_count_7\.Q * /steplen_6.Q * steplen_7.Q + \spg:MODULE_3:g1:a0:gx:u0:eq_5\.CMB * \spg:current_count_6\.Q * /\spg:current_count_7\.Q * steplen_6.Q * /steplen_7.Q + \spg:MODULE_3:g1:a0:gx:u0:eq_5\.CMB * /\spg:current_count_6\.Q * /\spg:current_count_7\.Q * /steplen_6.Q * /steplen_7.Q /\spg:MODULE_7:g1:a0:gx:u0:eq_5\ = /\spg:current_phase_0\.Q * phase1_0.Q + /\spg:current_phase_1\.Q * phase1_1.Q + /\spg:current_phase_2\.Q * phase1_2.Q + /\spg:current_phase_3\.Q * phase1_3.Q + /\spg:current_phase_4\.Q * phase1_4.Q + /\spg:current_phase_5\.Q * phase1_5.Q + \spg:current_phase_0\.Q * /phase1_0.Q + \spg:current_phase_1\.Q * /phase1_1.Q + \spg:current_phase_2\.Q * /phase1_2.Q + \spg:current_phase_3\.Q * /phase1_3.Q + \spg:current_phase_4\.Q * /phase1_4.Q + \spg:current_phase_5\.Q * /phase1_5.Q \spg:MODULE_7:g1:a0:gx:u0:geq(0):c3:u1\ = \spg:MODULE_7:g1:a0:gx:u0:eq_5\.CMB * \spg:current_phase_6\.Q * \spg:current_phase_7\.Q * phase1_6.Q * phase1_7.Q + \spg:MODULE_7:g1:a0:gx:u0:eq_5\.CMB * /\spg:current_phase_6\.Q * \spg:current_phase_7\.Q * /phase1_6.Q * phase1_7.Q + \spg:MODULE_7:g1:a0:gx:u0:eq_5\.CMB * \spg:current_phase_6\.Q * /\spg:current_phase_7\.Q * phase1_6.Q * /phase1_7.Q + \spg:MODULE_7:g1:a0:gx:u0:eq_5\.CMB * /\spg:current_phase_6\.Q * /\spg:current_phase_7\.Q * /phase1_6.Q * /phase1_7.Q /\spg:MODULE_8:g1:a0:gx:u0:eq_5\ = /\spg:current_phase_0\.Q * phase2_0.Q + /\spg:current_phase_1\.Q * phase2_1.Q + /\spg:current_phase_2\.Q * phase2_2.Q + /\spg:current_phase_3\.Q * phase2_3.Q + /\spg:current_phase_4\.Q * phase2_4.Q + /\spg:current_phase_5\.Q * phase2_5.Q + \spg:current_phase_0\.Q * /phase2_0.Q + \spg:current_phase_1\.Q * /phase2_1.Q + \spg:current_phase_2\.Q * /phase2_2.Q + \spg:current_phase_3\.Q * /phase2_3.Q + \spg:current_phase_4\.Q * /phase2_4.Q + \spg:current_phase_5\.Q * /phase2_5.Q \spg:MODULE_8:g1:a0:gx:u0:geq(0):c3:u1\ = \spg:MODULE_8:g1:a0:gx:u0:eq_5\.CMB * \spg:current_phase_6\.Q * \spg:current_phase_7\.Q * phase2_6.Q * phase2_7.Q + \spg:MODULE_8:g1:a0:gx:u0:eq_5\.CMB * /\spg:current_phase_6\.Q * \spg:current_phase_7\.Q * /phase2_6.Q * phase2_7.Q + \spg:MODULE_8:g1:a0:gx:u0:eq_5\.CMB * \spg:current_phase_6\.Q * /\spg:current_phase_7\.Q * phase2_6.Q * /phase2_7.Q + \spg:MODULE_8:g1:a0:gx:u0:eq_5\.CMB * /\spg:current_phase_6\.Q * /\spg:current_phase_7\.Q * /phase2_6.Q * /phase2_7.Q /\spg:cmp_vv_us_MODGEN_1\ = /\spg:precount_0\.Q * predev_0.Q + /\spg:precount_1\.Q * predev_1.Q + /\spg:precount_2\.Q * predev_2.Q + /\spg:precount_3\.Q * predev_3.Q + \spg:precount_0\.Q * /predev_0.Q + \spg:precount_1\.Q * /predev_1.Q + \spg:precount_2\.Q * /predev_2.Q + \spg:precount_3\.Q * /predev_3.Q \spg:cmp_vv_us_MODGEN_3\ = \spg:MODULE_3:g1:a0:gx:u0:geq(0):c3:u1\.CMB * \spg:current_count_8\.Q * \spg:current_count_9\.Q * steplen_8.Q * steplen_9.Q + \spg:MODULE_3:g1:a0:gx:u0:geq(0):c3:u1\.CMB * /\spg:current_count_8\.Q * \spg:current_count_9\.Q * /steplen_8.Q * steplen_9.Q + \spg:MODULE_3:g1:a0:gx:u0:geq(0):c3:u1\.CMB * \spg:current_count_8\.Q * /\spg:current_count_9\.Q * steplen_8.Q * /steplen_9.Q + \spg:MODULE_3:g1:a0:gx:u0:geq(0):c3:u1\.CMB * /\spg:current_count_8\.Q * /\spg:current_count_9\.Q * /steplen_8.Q * /steplen_9.Q \spg:cmp_vv_us_MODGEN_4\ = \spg:sample_0\.Q * \spg:sample_1\.Q * \spg:sample_2\.Q /\spg:cmp_vv_us_MODGEN_8\ = /\spg:current_phase_10\.Q * phase2_10.Q + /\spg:current_phase_11\.Q * phase2_11.Q + /\spg:current_phase_12\.Q * phase2_12.Q + /\spg:current_phase_8\.Q * phase2_8.Q + /\spg:current_phase_9\.Q * phase2_9.Q + \spg:current_phase_10\.Q * /phase2_10.Q + \spg:current_phase_11\.Q * /phase2_11.Q + \spg:current_phase_12\.Q * /phase2_12.Q + \spg:current_phase_8\.Q * /phase2_8.Q + \spg:current_phase_9\.Q * /phase2_9.Q + /\spg:MODULE_8:g1:a0:gx:u0:geq(0):c3:u1\.CMB \spg:current_count_0\.D = /\spg:cmp_vv_us_MODGEN_3\.CMB * /\spg:current_count_0\.Q \spg:current_count_0\.C = \spg:iclk\.Q \spg:current_count_1\.D = /\spg:cmp_vv_us_MODGEN_3\.CMB * /\spg:current_count_0\.Q * \spg:current_count_1\.Q + /\spg:cmp_vv_us_MODGEN_3\.CMB * \spg:current_count_0\.Q * /\spg:current_count_1\.Q \spg:current_count_1\.C = \spg:iclk\.Q \spg:current_count_2\.T = /\spg:cmp_vv_us_MODGEN_3\.CMB * \spg:current_count_0\.Q * \spg:current_count_1\.Q + \spg:cmp_vv_us_MODGEN_3\.CMB * \spg:current_count_2\.Q \spg:current_count_2\.C = \spg:iclk\.Q \spg:current_count_3\.T = /\spg:cmp_vv_us_MODGEN_3\.CMB * \spg:current_count_0\.Q * \spg:current_count_1\.Q * \spg:current_count_2\.Q + \spg:cmp_vv_us_MODGEN_3\.CMB * \spg:current_count_3\.Q \spg:current_count_3\.C = \spg:iclk\.Q \spg:current_count_4\.T = /\spg:cmp_vv_us_MODGEN_3\.CMB * \spg:current_count_0\.Q * \spg:current_count_1\.Q * \spg:current_count_2\.Q * \spg:current_count_3\.Q + \spg:cmp_vv_us_MODGEN_3\.CMB * \spg:current_count_4\.Q \spg:current_count_4\.C = \spg:iclk\.Q \spg:current_count_5\.T = /\spg:cmp_vv_us_MODGEN_3\.CMB * \spg:current_count_0\.Q * \spg:current_count_1\.Q * \spg:current_count_2\.Q * \spg:current_count_3\.Q * \spg:current_count_4\.Q + \spg:cmp_vv_us_MODGEN_3\.CMB * \spg:current_count_5\.Q \spg:current_count_5\.C = \spg:iclk\.Q \spg:current_count_6\.T = /\spg:cmp_vv_us_MODGEN_3\.CMB * \spg:current_count_0\.Q * \spg:current_count_1\.Q * \spg:current_count_2\.Q * \spg:current_count_3\.Q * \spg:current_count_4\.Q * \spg:current_count_5\.Q + \spg:cmp_vv_us_MODGEN_3\.CMB * \spg:current_count_6\.Q \spg:current_count_6\.C = \spg:iclk\.Q \spg:current_count_7\.T = /\spg:cmp_vv_us_MODGEN_3\.CMB * \spg:current_count_0\.Q * \spg:current_count_1\.Q * \spg:current_count_2\.Q * \spg:current_count_3\.Q * \spg:current_count_4\.Q * \spg:current_count_5\.Q * \spg:current_count_6\.Q + \spg:cmp_vv_us_MODGEN_3\.CMB * \spg:current_count_7\.Q \spg:current_count_7\.C = \spg:iclk\.Q \spg:current_count_8\.T = /\spg:cmp_vv_us_MODGEN_3\.CMB * \spg:current_count_0\.Q * \spg:current_count_1\.Q * \spg:current_count_2\.Q * \spg:current_count_3\.Q * \spg:current_count_4\.Q * \spg:current_count_5\.Q * \spg:current_count_6\.Q * \spg:current_count_7\.Q + \spg:cmp_vv_us_MODGEN_3\.CMB * \spg:current_count_8\.Q \spg:current_count_8\.C = \spg:iclk\.Q \spg:current_count_9\.T = /\spg:cmp_vv_us_MODGEN_3\.CMB * \spg:current_count_0\.Q * \spg:current_count_1\.Q * \spg:current_count_2\.Q * \spg:current_count_3\.Q * \spg:current_count_4\.Q * \spg:current_count_5\.Q * \spg:current_count_6\.Q * \spg:current_count_7\.Q * \spg:current_count_8\.Q + \spg:cmp_vv_us_MODGEN_3\.CMB * \spg:current_count_9\.Q \spg:current_count_9\.C = \spg:iclk\.Q \spg:current_phase_0\.D = /\spg:cmp_vv_us_MODGEN_3\.CMB * /\spg:current_phase_0\.Q + /\spg:cmp_vv_us_MODGEN_4\.CMB * /\spg:current_phase_0\.Q \spg:current_phase_0\.C = \spg:iclk\.Q \spg:current_phase_10\.T = /\spg:cmp_vv_us_MODGEN_3\.CMB * \spg:current_phase_0\.Q * \spg:current_phase_1\.Q * \spg:current_phase_2\.Q * \spg:current_phase_3\.Q * \spg:current_phase_4\.Q * \spg:current_phase_5\.Q * \spg:current_phase_6\.Q * \spg:current_phase_7\.Q * \spg:current_phase_8\.Q * \spg:current_phase_9\.Q + /\spg:cmp_vv_us_MODGEN_4\.CMB * \spg:current_phase_0\.Q * \spg:current_phase_1\.Q * \spg:current_phase_2\.Q * \spg:current_phase_3\.Q * \spg:current_phase_4\.Q * \spg:current_phase_5\.Q * \spg:current_phase_6\.Q * \spg:current_phase_7\.Q * \spg:current_phase_8\.Q * \spg:current_phase_9\.Q + \spg:cmp_vv_us_MODGEN_3\.CMB * \spg:cmp_vv_us_MODGEN_4\.CMB * \spg:current_phase_10\.Q \spg:current_phase_10\.C = \spg:iclk\.Q \spg:current_phase_11\.T = /\spg:cmp_vv_us_MODGEN_3\.CMB * \spg:current_phase_0\.Q * \spg:current_phase_10\.Q * \spg:current_phase_1\.Q * \spg:current_phase_2\.Q * \spg:current_phase_3\.Q * \spg:current_phase_4\.Q * \spg:current_phase_5\.Q * \spg:current_phase_6\.Q * \spg:current_phase_7\.Q * \spg:current_phase_8\.Q * \spg:current_phase_9\.Q + /\spg:cmp_vv_us_MODGEN_4\.CMB * \spg:current_phase_0\.Q * \spg:current_phase_10\.Q * \spg:current_phase_1\.Q * \spg:current_phase_2\.Q * \spg:current_phase_3\.Q * \spg:current_phase_4\.Q * \spg:current_phase_5\.Q * \spg:current_phase_6\.Q * \spg:current_phase_7\.Q * \spg:current_phase_8\.Q * \spg:current_phase_9\.Q + \spg:cmp_vv_us_MODGEN_3\.CMB * \spg:cmp_vv_us_MODGEN_4\.CMB * \spg:current_phase_11\.Q \spg:current_phase_11\.C = \spg:iclk\.Q \spg:current_phase_12\.T = /\spg:cmp_vv_us_MODGEN_3\.CMB * \spg:current_phase_0\.Q * \spg:current_phase_10\.Q * \spg:current_phase_11\.Q * \spg:current_phase_1\.Q * \spg:current_phase_2\.Q * \spg:current_phase_3\.Q * \spg:current_phase_4\.Q * \spg:current_phase_5\.Q * \spg:current_phase_6\.Q * \spg:current_phase_7\.Q * \spg:current_phase_8\.Q * \spg:current_phase_9\.Q + /\spg:cmp_vv_us_MODGEN_4\.CMB * \spg:current_phase_0\.Q * \spg:current_phase_10\.Q * \spg:current_phase_11\.Q * \spg:current_phase_1\.Q * \spg:current_phase_2\.Q * \spg:current_phase_3\.Q * \spg:current_phase_4\.Q * \spg:current_phase_5\.Q * \spg:current_phase_6\.Q * \spg:current_phase_7\.Q * \spg:current_phase_8\.Q * \spg:current_phase_9\.Q + \spg:cmp_vv_us_MODGEN_3\.CMB * \spg:cmp_vv_us_MODGEN_4\.CMB * \spg:current_phase_12\.Q \spg:current_phase_12\.C = \spg:iclk\.Q /\spg:current_phase_1\.D = \spg:current_phase_0\.Q * \spg:current_phase_1\.Q + \spg:cmp_vv_us_MODGEN_3\.CMB * \spg:cmp_vv_us_MODGEN_4\.CMB + /\spg:current_phase_0\.Q * /\spg:current_phase_1\.Q \spg:current_phase_1\.C = \spg:iclk\.Q \spg:current_phase_2\.T = \spg:cmp_vv_us_MODGEN_3\.CMB * \spg:cmp_vv_us_MODGEN_4\.CMB * \spg:current_phase_2\.Q + /\spg:cmp_vv_us_MODGEN_3\.CMB * \spg:current_phase_0\.Q * \spg:current_phase_1\.Q + /\spg:cmp_vv_us_MODGEN_4\.CMB * \spg:current_phase_0\.Q * \spg:current_phase_1\.Q \spg:current_phase_2\.C = \spg:iclk\.Q \spg:current_phase_3\.T = /\spg:cmp_vv_us_MODGEN_3\.CMB * \spg:current_phase_0\.Q * \spg:current_phase_1\.Q * \spg:current_phase_2\.Q + /\spg:cmp_vv_us_MODGEN_4\.CMB * \spg:current_phase_0\.Q * \spg:current_phase_1\.Q * \spg:current_phase_2\.Q + \spg:cmp_vv_us_MODGEN_3\.CMB * \spg:cmp_vv_us_MODGEN_4\.CMB * \spg:current_phase_3\.Q \spg:current_phase_3\.C = \spg:iclk\.Q \spg:current_phase_4\.T = /\spg:cmp_vv_us_MODGEN_3\.CMB * \spg:current_phase_0\.Q * \spg:current_phase_1\.Q * \spg:current_phase_2\.Q * \spg:current_phase_3\.Q + /\spg:cmp_vv_us_MODGEN_4\.CMB * \spg:current_phase_0\.Q * \spg:current_phase_1\.Q * \spg:current_phase_2\.Q * \spg:current_phase_3\.Q + \spg:cmp_vv_us_MODGEN_3\.CMB * \spg:cmp_vv_us_MODGEN_4\.CMB * \spg:current_phase_4\.Q \spg:current_phase_4\.C = \spg:iclk\.Q \spg:current_phase_5\.T = /\spg:cmp_vv_us_MODGEN_3\.CMB * \spg:current_phase_0\.Q * \spg:current_phase_1\.Q * \spg:current_phase_2\.Q * \spg:current_phase_3\.Q * \spg:current_phase_4\.Q + /\spg:cmp_vv_us_MODGEN_4\.CMB * \spg:current_phase_0\.Q * \spg:current_phase_1\.Q * \spg:current_phase_2\.Q * \spg:current_phase_3\.Q * \spg:current_phase_4\.Q + \spg:cmp_vv_us_MODGEN_3\.CMB * \spg:cmp_vv_us_MODGEN_4\.CMB * \spg:current_phase_5\.Q \spg:current_phase_5\.C = \spg:iclk\.Q \spg:current_phase_6\.T = /\spg:cmp_vv_us_MODGEN_3\.CMB * \spg:current_phase_0\.Q * \spg:current_phase_1\.Q * \spg:current_phase_2\.Q * \spg:current_phase_3\.Q * \spg:current_phase_4\.Q * \spg:current_phase_5\.Q + /\spg:cmp_vv_us_MODGEN_4\.CMB * \spg:current_phase_0\.Q * \spg:current_phase_1\.Q * \spg:current_phase_2\.Q * \spg:current_phase_3\.Q * \spg:current_phase_4\.Q * \spg:current_phase_5\.Q + \spg:cmp_vv_us_MODGEN_3\.CMB * \spg:cmp_vv_us_MODGEN_4\.CMB * \spg:current_phase_6\.Q \spg:current_phase_6\.C = \spg:iclk\.Q \spg:current_phase_7\.T = /\spg:cmp_vv_us_MODGEN_3\.CMB * \spg:current_phase_0\.Q * \spg:current_phase_1\.Q * \spg:current_phase_2\.Q * \spg:current_phase_3\.Q * \spg:current_phase_4\.Q * \spg:current_phase_5\.Q * \spg:current_phase_6\.Q + /\spg:cmp_vv_us_MODGEN_4\.CMB * \spg:current_phase_0\.Q * \spg:current_phase_1\.Q * \spg:current_phase_2\.Q * \spg:current_phase_3\.Q * \spg:current_phase_4\.Q * \spg:current_phase_5\.Q * \spg:current_phase_6\.Q + \spg:cmp_vv_us_MODGEN_3\.CMB * \spg:cmp_vv_us_MODGEN_4\.CMB * \spg:current_phase_7\.Q \spg:current_phase_7\.C = \spg:iclk\.Q \spg:current_phase_8\.T = /\spg:cmp_vv_us_MODGEN_3\.CMB * \spg:current_phase_0\.Q * \spg:current_phase_1\.Q * \spg:current_phase_2\.Q * \spg:current_phase_3\.Q * \spg:current_phase_4\.Q * \spg:current_phase_5\.Q * \spg:current_phase_6\.Q * \spg:current_phase_7\.Q + /\spg:cmp_vv_us_MODGEN_4\.CMB * \spg:current_phase_0\.Q * \spg:current_phase_1\.Q * \spg:current_phase_2\.Q * \spg:current_phase_3\.Q * \spg:current_phase_4\.Q * \spg:current_phase_5\.Q * \spg:current_phase_6\.Q * \spg:current_phase_7\.Q + \spg:cmp_vv_us_MODGEN_3\.CMB * \spg:cmp_vv_us_MODGEN_4\.CMB * \spg:current_phase_8\.Q \spg:current_phase_8\.C = \spg:iclk\.Q \spg:current_phase_9\.T = /\spg:cmp_vv_us_MODGEN_3\.CMB * \spg:current_phase_0\.Q * \spg:current_phase_1\.Q * \spg:current_phase_2\.Q * \spg:current_phase_3\.Q * \spg:current_phase_4\.Q * \spg:current_phase_5\.Q * \spg:current_phase_6\.Q * \spg:current_phase_7\.Q * \spg:current_phase_8\.Q + /\spg:cmp_vv_us_MODGEN_4\.CMB * \spg:current_phase_0\.Q * \spg:current_phase_1\.Q * \spg:current_phase_2\.Q * \spg:current_phase_3\.Q * \spg:current_phase_4\.Q * \spg:current_phase_5\.Q * \spg:current_phase_6\.Q * \spg:current_phase_7\.Q * \spg:current_phase_8\.Q + \spg:cmp_vv_us_MODGEN_3\.CMB * \spg:cmp_vv_us_MODGEN_4\.CMB * \spg:current_phase_9\.Q \spg:current_phase_9\.C = \spg:iclk\.Q \spg:iclk\.T = \spg:cmp_vv_us_MODGEN_1\.CMB \spg:iclk\.C = clk \spg:kdacSBV_0\.D = sp_ack.Q * sp_req.Q + \spg:kdacSBV_0\.Q * \spg:kick_dac\.Q \spg:kdacSBV_0\.C = clk \spg:kick_dac\.D = \spg:cmp_vv_us_MODGEN_3\.CMB \spg:kick_dac\.C = \spg:iclk\.Q \spg:precount_0\.D = /\spg:cmp_vv_us_MODGEN_1\.CMB * /\spg:precount_0\.Q \spg:precount_0\.C = clk \spg:precount_1\.D = /\spg:cmp_vv_us_MODGEN_1\.CMB * /\spg:precount_0\.Q * \spg:precount_1\.Q + /\spg:cmp_vv_us_MODGEN_1\.CMB * \spg:precount_0\.Q * /\spg:precount_1\.Q \spg:precount_1\.C = clk \spg:precount_2\.T = /\spg:cmp_vv_us_MODGEN_1\.CMB * \spg:precount_0\.Q * \spg:precount_1\.Q + \spg:cmp_vv_us_MODGEN_1\.CMB * \spg:precount_2\.Q \spg:precount_2\.C = clk \spg:precount_3\.T = /\spg:cmp_vv_us_MODGEN_1\.CMB * \spg:precount_0\.Q * \spg:precount_1\.Q * \spg:precount_2\.Q + \spg:cmp_vv_us_MODGEN_1\.CMB * \spg:precount_3\.Q \spg:precount_3\.C = clk \spg:sample_0\.D = \spg:cmp_vv_us_MODGEN_3\.CMB * /\spg:cmp_vv_us_MODGEN_4\.CMB * /\spg:sample_0\.Q + /\spg:cmp_vv_us_MODGEN_3\.CMB * \spg:sample_0\.Q \spg:sample_0\.C = \spg:iclk\.Q \spg:sample_1\.T = \spg:cmp_vv_us_MODGEN_3\.CMB * \spg:cmp_vv_us_MODGEN_4\.CMB * \spg:sample_1\.Q + \spg:cmp_vv_us_MODGEN_3\.CMB * /\spg:cmp_vv_us_MODGEN_4\.CMB * \spg:sample_0\.Q \spg:sample_1\.C = \spg:iclk\.Q \spg:sample_2\.T = \spg:cmp_vv_us_MODGEN_3\.CMB * /\spg:cmp_vv_us_MODGEN_4\.CMB * \spg:sample_0\.Q * \spg:sample_1\.Q + \spg:cmp_vv_us_MODGEN_3\.CMB * \spg:cmp_vv_us_MODGEN_4\.CMB * \spg:sample_2\.Q \spg:sample_2\.C = \spg:iclk\.Q address_from_pc_0.T = /\rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_1\.Q * \rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * dac_data_from_pc_0.Q * dac_data_from_pc_10.Q * /dac_data_from_pc_11.Q * dac_data_from_pc_15.Q * /dac_data_from_pc_9.Q + /\rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_1\.Q * \rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /dac_data_from_pc_0.Q * dac_data_from_pc_10.Q * /dac_data_from_pc_11.Q * dac_data_from_pc_15.Q * /dac_data_from_pc_9.Q address_from_pc_0.C = clk address_from_pc_1.T = /\rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_1\.Q * \rio:il_read_stateSBV_2\.Q * /address_from_pc_1.Q * dac_data_from_pc_1.Q * dac_data_from_pc_10.Q * /dac_data_from_pc_11.Q * dac_data_from_pc_15.Q * /dac_data_from_pc_9.Q + /\rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_1\.Q * \rio:il_read_stateSBV_2\.Q * address_from_pc_1.Q * /dac_data_from_pc_1.Q * dac_data_from_pc_10.Q * /dac_data_from_pc_11.Q * dac_data_from_pc_15.Q * /dac_data_from_pc_9.Q address_from_pc_1.C = clk address_from_pc_2.T = /\rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_1\.Q * \rio:il_read_stateSBV_2\.Q * /address_from_pc_2.Q * dac_data_from_pc_10.Q * /dac_data_from_pc_11.Q * dac_data_from_pc_15.Q * dac_data_from_pc_2.Q * /dac_data_from_pc_9.Q + /\rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_1\.Q * \rio:il_read_stateSBV_2\.Q * address_from_pc_2.Q * dac_data_from_pc_10.Q * /dac_data_from_pc_11.Q * dac_data_from_pc_15.Q * /dac_data_from_pc_2.Q * /dac_data_from_pc_9.Q address_from_pc_2.C = clk address_from_pc_3.T = /\rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_1\.Q * \rio:il_read_stateSBV_2\.Q * /address_from_pc_3.Q * dac_data_from_pc_10.Q * /dac_data_from_pc_11.Q * dac_data_from_pc_15.Q * dac_data_from_pc_3.Q * /dac_data_from_pc_9.Q + /\rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_1\.Q * \rio:il_read_stateSBV_2\.Q * address_from_pc_3.Q * dac_data_from_pc_10.Q * /dac_data_from_pc_11.Q * dac_data_from_pc_15.Q * /dac_data_from_pc_3.Q * /dac_data_from_pc_9.Q address_from_pc_3.C = clk ao_from_pc_ack.D = \rio:il_read_stateSBV_1\.Q ao_from_pc_ack.C = clk ao_from_pc_ack.OE = this_chip_selected.Q da_not_clr.D = VCC da_not_clr.AP = GND da_not_clr.AR = reset da_not_clr.C = clk da_not_cs.D = GND da_not_cs.AP = GND da_not_cs.AR = reset da_not_cs.C = clk /da_not_ldab = /daaddr(1).Q * /daaddr(2).Q /da_not_ldcd = daaddr(1).Q * /daaddr(2).Q /da_not_ldef = /daaddr(1).Q * daaddr(2).Q /da_not_ldgh = daaddr(1).Q * daaddr(2).Q da_not_wr.D = /\dacwr:dac_stateSBV_0\.Q da_not_wr.C = clk daaddr(0).T = /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * /address_from_pc_0.Q * daaddr(0).Q * to_dac_from_pc_req.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * address_from_pc_0.Q * /daaddr(0).Q * to_dac_from_pc_req.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * daaddr(0).Q * sp_req.Q * /to_dac_from_pc_req.Q daaddr(0).C = clk daaddr(1).T = /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * /address_from_pc_1.Q * daaddr(1).Q * to_dac_from_pc_req.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * address_from_pc_1.Q * /daaddr(1).Q * to_dac_from_pc_req.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * daaddr(1).Q * sp_req.Q * /to_dac_from_pc_req.Q daaddr(1).C = clk daaddr(2).T = /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * /address_from_pc_2.Q * daaddr(2).Q * to_dac_from_pc_req.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * address_from_pc_2.Q * /daaddr(2).Q * to_dac_from_pc_req.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q * daaddr(2).Q * sp_req.Q * /to_dac_from_pc_req.Q daaddr(2).C = clk dac_data_from_pc_0.T = /\rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_1\.Q * /\rio:il_read_stateSBV_2\.Q * ao_from_pc_strobe * /dac_data_from_pc_0.Q * id(0) + /\rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_1\.Q * /\rio:il_read_stateSBV_2\.Q * ao_from_pc_strobe * dac_data_from_pc_0.Q * /id(0) dac_data_from_pc_0.C = clk dac_data_from_pc_1.T = /\rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_1\.Q * /\rio:il_read_stateSBV_2\.Q * ao_from_pc_strobe * /dac_data_from_pc_1.Q * id(1) + /\rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_1\.Q * /\rio:il_read_stateSBV_2\.Q * ao_from_pc_strobe * dac_data_from_pc_1.Q * /id(1) dac_data_from_pc_1.C = clk dac_data_from_pc_10.T = /\rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_1\.Q * /\rio:il_read_stateSBV_2\.Q * ao_from_pc_strobe * /dac_data_from_pc_10.Q * id(10) + /\rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_1\.Q * /\rio:il_read_stateSBV_2\.Q * ao_from_pc_strobe * dac_data_from_pc_10.Q * /id(10) dac_data_from_pc_10.C = clk dac_data_from_pc_11.T = /\rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_1\.Q * /\rio:il_read_stateSBV_2\.Q * ao_from_pc_strobe * /dac_data_from_pc_11.Q * id(11) + /\rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_1\.Q * /\rio:il_read_stateSBV_2\.Q * ao_from_pc_strobe * dac_data_from_pc_11.Q * /id(11) dac_data_from_pc_11.C = clk dac_data_from_pc_12.T = /\rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_1\.Q * /\rio:il_read_stateSBV_2\.Q * ao_from_pc_strobe * /dac_data_from_pc_12.Q * id(12) + /\rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_1\.Q * /\rio:il_read_stateSBV_2\.Q * ao_from_pc_strobe * dac_data_from_pc_12.Q * /id(12) dac_data_from_pc_12.C = clk dac_data_from_pc_15.T = /\rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_1\.Q * /\rio:il_read_stateSBV_2\.Q * ao_from_pc_strobe * /dac_data_from_pc_15.Q * id(15) + /\rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_1\.Q * /\rio:il_read_stateSBV_2\.Q * ao_from_pc_strobe * dac_data_from_pc_15.Q * /id(15) dac_data_from_pc_15.C = clk dac_data_from_pc_2.T = /\rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_1\.Q * /\rio:il_read_stateSBV_2\.Q * ao_from_pc_strobe * /dac_data_from_pc_2.Q * id(2) + /\rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_1\.Q * /\rio:il_read_stateSBV_2\.Q * ao_from_pc_strobe * dac_data_from_pc_2.Q * /id(2) dac_data_from_pc_2.C = clk dac_data_from_pc_3.T = /\rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_1\.Q * /\rio:il_read_stateSBV_2\.Q * ao_from_pc_strobe * /dac_data_from_pc_3.Q * id(3) + /\rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_1\.Q * /\rio:il_read_stateSBV_2\.Q * ao_from_pc_strobe * dac_data_from_pc_3.Q * /id(3) dac_data_from_pc_3.C = clk dac_data_from_pc_4.T = /\rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_1\.Q * /\rio:il_read_stateSBV_2\.Q * ao_from_pc_strobe * /dac_data_from_pc_4.Q * id(4) + /\rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_1\.Q * /\rio:il_read_stateSBV_2\.Q * ao_from_pc_strobe * dac_data_from_pc_4.Q * /id(4) dac_data_from_pc_4.C = clk dac_data_from_pc_5.T = /\rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_1\.Q * /\rio:il_read_stateSBV_2\.Q * ao_from_pc_strobe * /dac_data_from_pc_5.Q * id(5) + /\rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_1\.Q * /\rio:il_read_stateSBV_2\.Q * ao_from_pc_strobe * dac_data_from_pc_5.Q * /id(5) dac_data_from_pc_5.C = clk dac_data_from_pc_6.T = /\rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_1\.Q * /\rio:il_read_stateSBV_2\.Q * ao_from_pc_strobe * /dac_data_from_pc_6.Q * id(6) + /\rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_1\.Q * /\rio:il_read_stateSBV_2\.Q * ao_from_pc_strobe * dac_data_from_pc_6.Q * /id(6) dac_data_from_pc_6.C = clk dac_data_from_pc_7.T = /\rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_1\.Q * /\rio:il_read_stateSBV_2\.Q * ao_from_pc_strobe * /dac_data_from_pc_7.Q * id(7) + /\rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_1\.Q * /\rio:il_read_stateSBV_2\.Q * ao_from_pc_strobe * dac_data_from_pc_7.Q * /id(7) dac_data_from_pc_7.C = clk dac_data_from_pc_8.T = /\rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_1\.Q * /\rio:il_read_stateSBV_2\.Q * ao_from_pc_strobe * /dac_data_from_pc_8.Q * id(8) + /\rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_1\.Q * /\rio:il_read_stateSBV_2\.Q * ao_from_pc_strobe * dac_data_from_pc_8.Q * /id(8) dac_data_from_pc_8.C = clk dac_data_from_pc_9.T = /\rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_1\.Q * /\rio:il_read_stateSBV_2\.Q * ao_from_pc_strobe * /dac_data_from_pc_9.Q * id(9) + /\rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_1\.Q * /\rio:il_read_stateSBV_2\.Q * ao_from_pc_strobe * dac_data_from_pc_9.Q * /id(9) dac_data_from_pc_9.C = clk dad(0).D = \dacwr:dac_hold_0\.Q * /\dacwr:dac_stateSBV_1\.Q * \dacwr:dac_stateSBV_2\.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_2\.Q * dad(0).Q + \dacwr:dac_stateSBV_1\.Q * dad(0).Q + \dacwr:dac_hold_0\.Q * \dacwr:dac_stateSBV_0\.Q dad(0).C = clk dad(1).D = \dacwr:dac_hold_1\.Q * /\dacwr:dac_stateSBV_1\.Q * \dacwr:dac_stateSBV_2\.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_2\.Q * dad(1).Q + \dacwr:dac_stateSBV_1\.Q * dad(1).Q + \dacwr:dac_hold_1\.Q * \dacwr:dac_stateSBV_0\.Q dad(1).C = clk dad(10).D = \dacwr:dac_hold_10\.Q * /\dacwr:dac_stateSBV_1\.Q * \dacwr:dac_stateSBV_2\.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_2\.Q * dad(10).Q + \dacwr:dac_stateSBV_1\.Q * dad(10).Q + \dacwr:dac_hold_10\.Q * \dacwr:dac_stateSBV_0\.Q dad(10).C = clk dad(11).D = \dacwr:dac_hold_11\.Q * /\dacwr:dac_stateSBV_1\.Q * \dacwr:dac_stateSBV_2\.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_2\.Q * dad(11).Q + \dacwr:dac_stateSBV_1\.Q * dad(11).Q + \dacwr:dac_hold_11\.Q * \dacwr:dac_stateSBV_0\.Q dad(11).C = clk dad(12).D = \dacwr:dac_hold_12\.Q * /\dacwr:dac_stateSBV_1\.Q * \dacwr:dac_stateSBV_2\.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_2\.Q * dad(12).Q + \dacwr:dac_stateSBV_1\.Q * dad(12).Q + \dacwr:dac_hold_12\.Q * \dacwr:dac_stateSBV_0\.Q dad(12).C = clk dad(2).D = \dacwr:dac_hold_2\.Q * /\dacwr:dac_stateSBV_1\.Q * \dacwr:dac_stateSBV_2\.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_2\.Q * dad(2).Q + \dacwr:dac_stateSBV_1\.Q * dad(2).Q + \dacwr:dac_hold_2\.Q * \dacwr:dac_stateSBV_0\.Q dad(2).C = clk dad(3).D = \dacwr:dac_hold_3\.Q * /\dacwr:dac_stateSBV_1\.Q * \dacwr:dac_stateSBV_2\.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_2\.Q * dad(3).Q + \dacwr:dac_stateSBV_1\.Q * dad(3).Q + \dacwr:dac_hold_3\.Q * \dacwr:dac_stateSBV_0\.Q dad(3).C = clk dad(4).D = \dacwr:dac_hold_4\.Q * /\dacwr:dac_stateSBV_1\.Q * \dacwr:dac_stateSBV_2\.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_2\.Q * dad(4).Q + \dacwr:dac_stateSBV_1\.Q * dad(4).Q + \dacwr:dac_hold_4\.Q * \dacwr:dac_stateSBV_0\.Q dad(4).C = clk dad(5).D = \dacwr:dac_hold_5\.Q * /\dacwr:dac_stateSBV_1\.Q * \dacwr:dac_stateSBV_2\.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_2\.Q * dad(5).Q + \dacwr:dac_stateSBV_1\.Q * dad(5).Q + \dacwr:dac_hold_5\.Q * \dacwr:dac_stateSBV_0\.Q dad(5).C = clk dad(6).D = \dacwr:dac_hold_6\.Q * /\dacwr:dac_stateSBV_1\.Q * \dacwr:dac_stateSBV_2\.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_2\.Q * dad(6).Q + \dacwr:dac_stateSBV_1\.Q * dad(6).Q + \dacwr:dac_hold_6\.Q * \dacwr:dac_stateSBV_0\.Q dad(6).C = clk dad(7).D = \dacwr:dac_hold_7\.Q * /\dacwr:dac_stateSBV_1\.Q * \dacwr:dac_stateSBV_2\.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_2\.Q * dad(7).Q + \dacwr:dac_stateSBV_1\.Q * dad(7).Q + \dacwr:dac_hold_7\.Q * \dacwr:dac_stateSBV_0\.Q dad(7).C = clk dad(8).D = \dacwr:dac_hold_8\.Q * /\dacwr:dac_stateSBV_1\.Q * \dacwr:dac_stateSBV_2\.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_2\.Q * dad(8).Q + \dacwr:dac_stateSBV_1\.Q * dad(8).Q + \dacwr:dac_hold_8\.Q * \dacwr:dac_stateSBV_0\.Q dad(8).C = clk dad(9).D = \dacwr:dac_hold_9\.Q * /\dacwr:dac_stateSBV_1\.Q * \dacwr:dac_stateSBV_2\.Q + /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_2\.Q * dad(9).Q + \dacwr:dac_stateSBV_1\.Q * dad(9).Q + \dacwr:dac_hold_9\.Q * \dacwr:dac_stateSBV_0\.Q dad(9).C = clk dio_tristate = VCC phase1_0.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_0.Q * phase1_0.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_0.Q * /phase1_0.Q phase1_0.C = clk phase1_1.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_1.Q * phase1_1.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_1.Q * /phase1_1.Q phase1_1.C = clk phase1_10.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_10.Q * phase1_10.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_10.Q * /phase1_10.Q phase1_10.C = clk phase1_11.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_11.Q * phase1_11.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_11.Q * /phase1_11.Q phase1_11.C = clk phase1_12.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_12.Q * phase1_12.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_12.Q * /phase1_12.Q phase1_12.C = clk phase1_2.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_2.Q * phase1_2.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_2.Q * /phase1_2.Q phase1_2.C = clk phase1_3.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_3.Q * phase1_3.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_3.Q * /phase1_3.Q phase1_3.C = clk phase1_4.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_4.Q * phase1_4.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_4.Q * /phase1_4.Q phase1_4.C = clk phase1_5.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_5.Q * phase1_5.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_5.Q * /phase1_5.Q phase1_5.C = clk phase1_6.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_6.Q * phase1_6.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_6.Q * /phase1_6.Q phase1_6.C = clk phase1_7.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_7.Q * phase1_7.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_7.Q * /phase1_7.Q phase1_7.C = clk phase1_8.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_8.Q * phase1_8.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_8.Q * /phase1_8.Q phase1_8.C = clk phase1_9.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_9.Q * phase1_9.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_9.Q * /phase1_9.Q phase1_9.C = clk phase2_0.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_0.Q * phase2_0.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_0.Q * /phase2_0.Q phase2_0.C = clk phase2_1.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_1.Q * phase2_1.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_1.Q * /phase2_1.Q phase2_1.C = clk phase2_10.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_10.Q * phase2_10.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_10.Q * /phase2_10.Q phase2_10.C = clk phase2_11.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_11.Q * phase2_11.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_11.Q * /phase2_11.Q phase2_11.C = clk phase2_12.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_12.Q * phase2_12.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_12.Q * /phase2_12.Q phase2_12.C = clk phase2_2.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_2.Q * phase2_2.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_2.Q * /phase2_2.Q phase2_2.C = clk phase2_3.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_3.Q * phase2_3.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_3.Q * /phase2_3.Q phase2_3.C = clk phase2_4.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_4.Q * phase2_4.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_4.Q * /phase2_4.Q phase2_4.C = clk phase2_5.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_5.Q * phase2_5.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_5.Q * /phase2_5.Q phase2_5.C = clk phase2_6.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_6.Q * phase2_6.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_6.Q * /phase2_6.Q phase2_6.C = clk phase2_7.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_7.Q * phase2_7.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_7.Q * /phase2_7.Q phase2_7.C = clk phase2_8.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_8.Q * phase2_8.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_8.Q * /phase2_8.Q phase2_8.C = clk phase2_9.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_9.Q * phase2_9.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_9.Q * /phase2_9.Q phase2_9.C = clk predev_0.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * /address_from_pc_1.Q * address_from_pc_2.Q * address_from_pc_3.Q * /dac_data_from_pc_0.Q * predev_0.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * /address_from_pc_1.Q * address_from_pc_2.Q * address_from_pc_3.Q * dac_data_from_pc_0.Q * /predev_0.Q predev_0.C = clk predev_1.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * /address_from_pc_1.Q * address_from_pc_2.Q * address_from_pc_3.Q * /dac_data_from_pc_1.Q * predev_1.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * /address_from_pc_1.Q * address_from_pc_2.Q * address_from_pc_3.Q * dac_data_from_pc_1.Q * /predev_1.Q predev_1.C = clk predev_2.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * /address_from_pc_1.Q * address_from_pc_2.Q * address_from_pc_3.Q * /dac_data_from_pc_2.Q * predev_2.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * /address_from_pc_1.Q * address_from_pc_2.Q * address_from_pc_3.Q * dac_data_from_pc_2.Q * /predev_2.Q predev_2.C = clk predev_3.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * /address_from_pc_1.Q * address_from_pc_2.Q * address_from_pc_3.Q * /dac_data_from_pc_3.Q * predev_3.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * /address_from_pc_1.Q * address_from_pc_2.Q * address_from_pc_3.Q * dac_data_from_pc_3.Q * /predev_3.Q predev_3.C = clk shdn(0) = VCC shdn(1) = VCC shdn(2) = VCC shift_0.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * address_from_pc_2.Q * address_from_pc_3.Q * /dac_data_from_pc_0.Q * shift_0.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * address_from_pc_2.Q * address_from_pc_3.Q * dac_data_from_pc_0.Q * /shift_0.Q shift_0.C = clk shift_1.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * address_from_pc_2.Q * address_from_pc_3.Q * /dac_data_from_pc_1.Q * shift_1.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * address_from_pc_2.Q * address_from_pc_3.Q * dac_data_from_pc_1.Q * /shift_1.Q shift_1.C = clk shift_2.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * address_from_pc_2.Q * address_from_pc_3.Q * /dac_data_from_pc_2.Q * shift_2.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * address_from_pc_2.Q * address_from_pc_3.Q * dac_data_from_pc_2.Q * /shift_2.Q shift_2.C = clk /sinphase_zeros.D = S_2.CMB + S_1.CMB sinphase_zeros.C = \spg:iclk\.Q sp_ack.D = /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_2\.Q * sp_req.Q * /to_dac_from_pc_req.Q + \dacwr:dac_stateSBV_1\.Q * /\dacwr:dac_stateSBV_2\.Q sp_ack.C = clk sp_req.D = /\spg:kdacSBV_0\.Q * \spg:kick_dac\.Q * /sp_req.Q + /sp_ack.Q * sp_req.Q sp_req.C = clk steplen_0.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_0.Q * steplen_0.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_0.Q * /steplen_0.Q steplen_0.C = clk steplen_1.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_1.Q * steplen_1.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_1.Q * /steplen_1.Q steplen_1.C = clk steplen_2.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_2.Q * steplen_2.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_2.Q * /steplen_2.Q steplen_2.C = clk steplen_3.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_3.Q * steplen_3.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_3.Q * /steplen_3.Q steplen_3.C = clk steplen_4.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_4.Q * steplen_4.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_4.Q * /steplen_4.Q steplen_4.C = clk steplen_5.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_5.Q * steplen_5.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_5.Q * /steplen_5.Q steplen_5.C = clk steplen_6.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_6.Q * steplen_6.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_6.Q * /steplen_6.Q steplen_6.C = clk steplen_7.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_7.Q * steplen_7.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_7.Q * /steplen_7.Q steplen_7.C = clk steplen_8.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_8.Q * steplen_8.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_8.Q * /steplen_8.Q steplen_8.C = clk steplen_9.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_9.Q * steplen_9.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_9.Q * /steplen_9.Q steplen_9.C = clk this_chip_selected.T = /\rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_1\.Q * \rio:il_read_stateSBV_2\.Q * dac_data_from_pc_10.Q * /dac_data_from_pc_11.Q * dac_data_from_pc_15.Q * /dac_data_from_pc_9.Q * /this_chip_selected.Q + /\rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_1\.Q * \rio:il_read_stateSBV_2\.Q * dac_data_from_pc_15.Q * dac_data_from_pc_9.Q * this_chip_selected.Q + /\rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_1\.Q * \rio:il_read_stateSBV_2\.Q * dac_data_from_pc_11.Q * dac_data_from_pc_15.Q * this_chip_selected.Q + /\rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_1\.Q * \rio:il_read_stateSBV_2\.Q * /dac_data_from_pc_10.Q * dac_data_from_pc_15.Q * this_chip_selected.Q this_chip_selected.AP = GND this_chip_selected.AR = reset this_chip_selected.C = clk to_dac_from_pc_ack.D = /\dacwr:dac_stateSBV_0\.Q * /\dacwr:dac_stateSBV_1\.Q * to_dac_from_pc_req.Q + /\dacwr:dac_stateSBV_1\.Q * \dacwr:dac_stateSBV_2\.Q to_dac_from_pc_ack.C = clk to_dac_from_pc_req.D = \rio:il_read_stateSBV_0\.Q * \rio:il_read_stateSBV_2\.Q to_dac_from_pc_req.C = clk val0_0.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * /address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_0.Q * val0_0.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * /address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_0.Q * /val0_0.Q val0_0.C = clk val0_1.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * /address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_1.Q * val0_1.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * /address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_1.Q * /val0_1.Q val0_1.C = clk val0_2.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * /address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_2.Q * val0_2.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * /address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_2.Q * /val0_2.Q val0_2.C = clk val0_3.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * /address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_3.Q * val0_3.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * /address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_3.Q * /val0_3.Q val0_3.C = clk val0_4.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * /address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_4.Q * val0_4.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * /address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_4.Q * /val0_4.Q val0_4.C = clk val0_5.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * /address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_5.Q * val0_5.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * /address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_5.Q * /val0_5.Q val0_5.C = clk val0_6.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * /address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_6.Q * val0_6.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * /address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_6.Q * /val0_6.Q val0_6.C = clk val0_7.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * /address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_7.Q * val0_7.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * /address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_7.Q * /val0_7.Q val0_7.C = clk val1_0.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_0.Q * val1_0.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_0.Q * /val1_0.Q val1_0.C = clk val1_1.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_1.Q * val1_1.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_1.Q * /val1_1.Q val1_1.C = clk val1_2.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_2.Q * val1_2.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_2.Q * /val1_2.Q val1_2.C = clk val1_3.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_3.Q * val1_3.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_3.Q * /val1_3.Q val1_3.C = clk val1_4.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_4.Q * val1_4.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_4.Q * /val1_4.Q val1_4.C = clk val1_5.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_5.Q * val1_5.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_5.Q * /val1_5.Q val1_5.C = clk val1_6.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_6.Q * val1_6.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_6.Q * /val1_6.Q val1_6.C = clk val1_7.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_7.Q * val1_7.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_7.Q * /val1_7.Q val1_7.C = clk val2_0.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_0.Q * val2_0.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_0.Q * /val2_0.Q val2_0.C = clk val2_1.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_1.Q * val2_1.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_1.Q * /val2_1.Q val2_1.C = clk val2_2.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_2.Q * val2_2.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_2.Q * /val2_2.Q val2_2.C = clk val2_3.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_3.Q * val2_3.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_3.Q * /val2_3.Q val2_3.C = clk val2_4.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_4.Q * val2_4.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_4.Q * /val2_4.Q val2_4.C = clk val2_5.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_5.Q * val2_5.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_5.Q * /val2_5.Q val2_5.C = clk val2_6.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_6.Q * val2_6.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_6.Q * /val2_6.Q val2_6.C = clk val2_7.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_7.Q * val2_7.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_7.Q * /val2_7.Q val2_7.C = clk val3_0.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_0.Q * val3_0.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_0.Q * /val3_0.Q val3_0.C = clk val3_1.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_1.Q * val3_1.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_1.Q * /val3_1.Q val3_1.C = clk val3_2.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_2.Q * val3_2.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_2.Q * /val3_2.Q val3_2.C = clk val3_3.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_3.Q * val3_3.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_3.Q * /val3_3.Q val3_3.C = clk val3_4.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_4.Q * val3_4.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_4.Q * /val3_4.Q val3_4.C = clk val3_5.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_5.Q * val3_5.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_5.Q * /val3_5.Q val3_5.C = clk val3_6.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_6.Q * val3_6.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_6.Q * /val3_6.Q val3_6.C = clk val3_7.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * /dac_data_from_pc_7.Q * val3_7.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * address_from_pc_1.Q * address_from_pc_2.Q * /address_from_pc_3.Q * dac_data_from_pc_7.Q * /val3_7.Q val3_7.C = clk val4_0.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * /dac_data_from_pc_0.Q * val4_0.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * dac_data_from_pc_0.Q * /val4_0.Q val4_0.C = clk val4_1.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * /dac_data_from_pc_1.Q * val4_1.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * dac_data_from_pc_1.Q * /val4_1.Q val4_1.C = clk val4_2.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * /dac_data_from_pc_2.Q * val4_2.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * dac_data_from_pc_2.Q * /val4_2.Q val4_2.C = clk val4_3.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * /dac_data_from_pc_3.Q * val4_3.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * dac_data_from_pc_3.Q * /val4_3.Q val4_3.C = clk val4_4.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * /dac_data_from_pc_4.Q * val4_4.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * dac_data_from_pc_4.Q * /val4_4.Q val4_4.C = clk val4_5.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * /dac_data_from_pc_5.Q * val4_5.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * dac_data_from_pc_5.Q * /val4_5.Q val4_5.C = clk val4_6.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * /dac_data_from_pc_6.Q * val4_6.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * dac_data_from_pc_6.Q * /val4_6.Q val4_6.C = clk val4_7.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * /dac_data_from_pc_7.Q * val4_7.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * dac_data_from_pc_7.Q * /val4_7.Q val4_7.C = clk val5_0.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * /dac_data_from_pc_0.Q * val5_0.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * dac_data_from_pc_0.Q * /val5_0.Q val5_0.C = clk val5_1.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * /dac_data_from_pc_1.Q * val5_1.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * dac_data_from_pc_1.Q * /val5_1.Q val5_1.C = clk val5_2.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * /dac_data_from_pc_2.Q * val5_2.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * dac_data_from_pc_2.Q * /val5_2.Q val5_2.C = clk val5_3.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * /dac_data_from_pc_3.Q * val5_3.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * dac_data_from_pc_3.Q * /val5_3.Q val5_3.C = clk val5_4.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * /dac_data_from_pc_4.Q * val5_4.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * dac_data_from_pc_4.Q * /val5_4.Q val5_4.C = clk val5_5.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * /dac_data_from_pc_5.Q * val5_5.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * dac_data_from_pc_5.Q * /val5_5.Q val5_5.C = clk val5_6.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * /dac_data_from_pc_6.Q * val5_6.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * dac_data_from_pc_6.Q * /val5_6.Q val5_6.C = clk val5_7.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * /dac_data_from_pc_7.Q * val5_7.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * /address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * dac_data_from_pc_7.Q * /val5_7.Q val5_7.C = clk val6_0.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * /dac_data_from_pc_0.Q * val6_0.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * dac_data_from_pc_0.Q * /val6_0.Q val6_0.C = clk val6_1.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * /dac_data_from_pc_1.Q * val6_1.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * dac_data_from_pc_1.Q * /val6_1.Q val6_1.C = clk val6_2.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * /dac_data_from_pc_2.Q * val6_2.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * dac_data_from_pc_2.Q * /val6_2.Q val6_2.C = clk val6_3.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * /dac_data_from_pc_3.Q * val6_3.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * dac_data_from_pc_3.Q * /val6_3.Q val6_3.C = clk val6_4.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * /dac_data_from_pc_4.Q * val6_4.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * dac_data_from_pc_4.Q * /val6_4.Q val6_4.C = clk val6_5.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * /dac_data_from_pc_5.Q * val6_5.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * dac_data_from_pc_5.Q * /val6_5.Q val6_5.C = clk val6_6.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * /dac_data_from_pc_6.Q * val6_6.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * dac_data_from_pc_6.Q * /val6_6.Q val6_6.C = clk val6_7.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * /dac_data_from_pc_7.Q * val6_7.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * /address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * dac_data_from_pc_7.Q * /val6_7.Q val6_7.C = clk val7_0.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * /dac_data_from_pc_0.Q * val7_0.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * dac_data_from_pc_0.Q * /val7_0.Q val7_0.C = clk val7_1.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * /dac_data_from_pc_1.Q * val7_1.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * dac_data_from_pc_1.Q * /val7_1.Q val7_1.C = clk val7_2.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * /dac_data_from_pc_2.Q * val7_2.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * dac_data_from_pc_2.Q * /val7_2.Q val7_2.C = clk val7_3.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * /dac_data_from_pc_3.Q * val7_3.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * dac_data_from_pc_3.Q * /val7_3.Q val7_3.C = clk val7_4.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * /dac_data_from_pc_4.Q * val7_4.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * dac_data_from_pc_4.Q * /val7_4.Q val7_4.C = clk val7_5.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * /dac_data_from_pc_5.Q * val7_5.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * dac_data_from_pc_5.Q * /val7_5.Q val7_5.C = clk val7_6.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * /dac_data_from_pc_6.Q * val7_6.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * dac_data_from_pc_6.Q * /val7_6.Q val7_6.C = clk val7_7.T = \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * /dac_data_from_pc_7.Q * val7_7.Q + \rio:il_read_stateSBV_0\.Q * /\rio:il_read_stateSBV_2\.Q * address_from_pc_0.Q * address_from_pc_1.Q * /address_from_pc_2.Q * address_from_pc_3.Q * dac_data_from_pc_7.Q * /val7_7.Q val7_7.C = clk Completed Successfully ---------------------------------------------------------------------------- PLD Compiler Software: C37KFIT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 DESIGN RULE CHECK (17:51:45) Messages: None. Summary: Error Count = 0 Warning Count = 0 Completed Successfully ---------------------------------------------------------------------------- PLD Compiler Software: C37KFIT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 PARTITION LOGIC (17:51:48) Messages: Information: Initializing Logic Block structures. Information: Forming input seeds. Information: Checking for duplicate NODE logic. Information: Forming input seeds. Information: Assigning fixed logic to Logic Blocks. Information: Processing banked global preset, reset and output enable. Information: Separating output logic set to GND/VCC. Information: Validating Logic Block's with pre-placed signals. Information: Separating input register logic. Information: Assigning initializing equations to empty Logic Blocks. Information: Separating output combinatorial logic. Information: Separating disjoint output logic. Information: Separating output node logic. Information: Assigning floating outputs to Logic Blocks. Information: Compacting Logic Block interconnect. .................+..............................................+...... .............................................................+......... ..........................................................+............ ....................................................................... ..................................................................... Information: Separating output logic with >= 4628112 pt's. Information: Assigning floating outputs to Logic Blocks. Information: Minimizing interconnect between Logic Blocks. ......+.+............... Start=17:51:51 End=17:51:51 Information: Separating disjoint output logic. Information: Separating output node logic. Information: Assigning floating outputs to Logic Blocks. Information: Assigning floating outputs to Logic Blocks. Information: Assigning floating outputs to Logic Blocks. Information: Minimizing interconnect between Logic Blocks. .+.+++++.+++.++.+....++..+.+.+.+..+........+..+..+.+...+.+............ ..+............... Start=17:51:56 End=17:52:08 Information: Assigning floating outputs to Logic Blocks. Information: Assigning floating outputs to Logic Blocks. Information: Minimizing interconnect between Logic Blocks. ............... Start=17:52:08 End=17:52:12 Information: Condensing mcell usuage in Logic Blocks with high routing (1). ..............++. Information: Assigning floating outputs to Logic Blocks. Information: Condensing mcell usuage in Logic Blocks with high routing (2). ...+.+...+.+.++.++.++..++.++.+ Start=17:52:14 End=17:53:13 Information: Assigning floating outputs to Logic Blocks. Information: Reducing logic on list of signals still to be fit. Start=17:53:13 End=17:53:13 Summary: Error Count = 0 Warning Count = 0 Completed Successfully ---------------------------------------------------------------------------- PLD Compiler Software: C37KFIT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 DESIGN SIGNAL PLACEMENT (17:53:13) Messages: Information: Fitting signals to Logic Block A. Information: Assigning Signals to Macrocells. Information: Improving Macrocell Assignment ................ Information: Assigning Product Terms to Allocator Information: Fitting signals to Logic Block B. Information: Assigning Signals to Macrocells. Information: Improving Macrocell Assignment ................ Information: Assigning Product Terms to Allocator Information: Fitting signals to Logic Block C. Information: Assigning Signals to Macrocells. Information: Improving Macrocell Assignment ................ Information: Assigning Product Terms to Allocator Information: Combining 'address_from_pc_0' definition with input pin 'id(3)'. Information: Combining 'dac_data_from_pc_1' definition with input pin 'id(2)'. Information: Combining 'dac_data_from_pc_12' definition with input pin 'id(4)'. Information: Combining 'dac_data_from_pc_5' definition with input pin 'id(5)'. Information: Combining 'phase1_10' definition with input pin 'id(1)'. Information: Combining 'phase2_5' definition with input pin 'id(6)'. Information: Combining 'val7_5' definition with input pin 'id(0)'. Information: Fitting signals to Logic Block D. Information: Assigning Signals to Macrocells. Information: Improving Macrocell Assignment ................ Information: Assigning Product Terms to Allocator Information: Combining 'phase1_5' definition with input pin 'id(10)'. Information: Combining 'phase2_3' definition with input pin 'id(11)'. Information: Combining 'val0_3' definition with input pin 'id(9)'. Information: Combining 'val0_4' definition with input pin 'id(12)'. Information: Combining 'val1_3' definition with input pin 'id(8)'. Information: Combining 'val2_5' definition with input pin 'id(7)'. Information: Fitting signals to Logic Block E. Information: Assigning Signals to Macrocells. Information: Improving Macrocell Assignment ................ Information: Assigning Product Terms to Allocator Information: Combining 'val6_3' definition with input pin 'id(15)'. Information: Fitting signals to Logic Block F. Information: Assigning Signals to Macrocells. Information: Improving Macrocell Assignment .....+.................+...............+........................... Information: Assigning Product Terms to Allocator Information: Assigning Signals to Macrocells. Information: Improving Macrocell Assignment .............+................... Information: Assigning Product Terms to Allocator Information: Assigning Signals to Macrocells. Information: Improving Macrocell Assignment ................ Information: Assigning Product Terms to Allocator Information: Fitting signals to Logic Block G. Information: Assigning Signals to Macrocells. Information: Improving Macrocell Assignment ................ Information: Assigning Product Terms to Allocator Information: Fitting signals to Logic Block H. Information: Assigning Signals to Macrocells. Information: Improving Macrocell Assignment ................ Information: Assigning Product Terms to Allocator Information: Combining '\rio:il_read_stateSBV_1\' definition with input pin 'ao_from_pc_strobe'. Information: Fitting signals to Logic Block I. Information: Assigning Signals to Macrocells. Information: Improving Macrocell Assignment ................ Information: Assigning Product Terms to Allocator Information: Fitting signals to Logic Block J. Information: Assigning Signals to Macrocells. Information: Improving Macrocell Assignment ..+..+...............+............................. Information: Assigning Product Terms to Allocator Information: Fitting signals to Logic Block K. Information: Assigning Signals to Macrocells. Information: Improving Macrocell Assignment ................ Information: Assigning Product Terms to Allocator Information: Fitting signals to Logic Block L. Information: Assigning Signals to Macrocells. Information: Improving Macrocell Assignment ................ Information: Assigning Product Terms to Allocator Information: Fitting signals to Logic Block M. Information: Assigning Signals to Macrocells. Information: Improving Macrocell Assignment ..+................+.............................. Information: Assigning Product Terms to Allocator Information: Fitting signals to Logic Block N. Information: Assigning Signals to Macrocells. Information: Improving Macrocell Assignment ................ Information: Assigning Product Terms to Allocator Information: Fitting signals to Logic Block O. Information: Assigning Signals to Macrocells. Information: Improving Macrocell Assignment ................ Information: Assigning Product Terms to Allocator Information: Fitting signals to Logic Block P. Information: Assigning Signals to Macrocells. Information: Improving Macrocell Assignment ................ Information: Assigning Product Terms to Allocator Information: Routing signals to Logic Blocks. Summary: Error Count = 0 Warning Count = 0 Completed Successfully ---------------------------------------------------------------------------- PLD Compiler Software: C37KFIT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 LOGIC BLOCK A PLACEMENT (17:53:13) Messages: ________________________________________________________________________________ 1111111111222222222233333333334444444444555555555566666666667777777777 01234567890123456789012345678901234567890123456789012345678901234567890123456789 ________________________________________________________________________________ | 0 |(\spg:MODULE_8:g1:a0:gx:u0:eq_5\) XXXXXXXXXXXX++++................................................................ | 1 |(\spg:current_phase_9\) ......++++++XXX+++++++.......................................................... | 2 |(\spg:current_phase_7\) ..........+++++XXX++++++++...................................................... | 3 |(\spg:current_phase_4\) ..............++++X+XX++++++++.................................................. | 4 |(\spg:current_phase_2\) ..................+X+++X+++X++++++.............................................. | 5 |(\spg:current_phase_12\) ......................X+XX++++++++++++.......................................... | 6 |(\spg:current_phase_10\) ..........................X+XX++++++++++++...................................... | 7 |(\spg:MODULE_7:g1:a0:gx:u0:geq(0):c3:u1\) ..............................XXXX++++++++++++.................................. | 8 |(\spg:current_phase_11\) ..................................XXX+++++++++++++.............................. | 9 |(\spg:current_phase_1\) ......................................XXX+++++++++++++.......................... |10 |(\spg:current_phase_3\) ..........................................XXX+++++++++++++...................... |11 |(\spg:current_phase_5\) ..............................................XXX+++++++++++++.................. |12 |(\spg:current_phase_6\) ..................................................XXX+++++++++++++.............. |13 |(\spg:current_phase_8\) ......................................................XXX+++++++++++++.......... |14 |(\spg:current_phase_0\) ..........................................................XX++++++++++++++...... |15 |(\spg:MODULE_7:g1:a0:gx:u0:eq_5\) ................................................................XXXXXXXXXXXX++++ ________________________________________________________________________________ Total count of outputs placed = 16 Total count of unique Product Terms = 66 Total Product Terms to be assigned = 66 Max Product Terms used / available = 66 / 80 = 82.51 % Control Signals for Logic Block A --------------------------------- CLK pin 19 : CLK pin 22 : CLK pin 99 : CLK pin 102 : CLK PT : AH : \spg:iclk\.Q PRESET : AH : RESET : AH : OE 0 : AH : OE 1 : AH : OE 2 : AH : OE 3 : AH : Logic Block A ____________________________________________ | |= >\spg:curren.. | | | |= >\spg:curren.. | | | |= >\spg:curren.. | | | |> not used:265 | | | |= >\spg:iclk\.Q |143|= (\spg:MODULE_8:g1:a0:gx:u0:eq_5\) | |= >\spg:curren.. | | | |= >phase2_5.Q (\spg:current_phase_9\) =| | | |= >\spg:curren.. | | | |= >\spg:curren.. |144|= (\spg:current_phase_7\) | |= >phase1_5.Q | | | |= >\spg:curren.. (\spg:current_phase_4\) =| | | |= >phase1_7.Q | | | |= >phase1_6.Q |145|= (\spg:current_phase_2\) | |= >phase1_2.Q | | | |= >\spg:curren.. (\spg:current_phase_12\) =| | | |= >phase2_0.Q | | | |> not used:278 |146|= (\spg:current_phase_10\) | |= >\spg:curren.. | | | |= >phase2_3.Q (\spg:MODULE_7:g1:a0:gx:u0:geq(0):c3:u1\) =| | | |= >phase2_2.Q | | | |= >\spg:curren.. |147|= (\spg:current_phase_11\) | |> not used:283 | | | |= >\spg:curren.. (\spg:current_phase_1\) =| | | |= >\spg:curren.. | | | |= >\spg:curren.. |148|= (\spg:current_phase_3\) | |= >phase1_1.Q | | | |= >\spg:MODULE.. (\spg:current_phase_5\) =| | | |> not used:289 | | | |> not used:290 |149|= (\spg:current_phase_6\) | |= >phase1_0.Q | | | |= >phase1_4.Q (\spg:current_phase_8\) =| | | |= >phase1_3.Q | | | |> not used:294 |150|= (\spg:current_phase_0\) | |= >\spg:cmp_vv.. | | | |= >phase2_1.Q (\spg:MODULE_7:g1:a0:gx:u0:eq_5\) =| | | |> not used:297 | | | |> not used:298 | | | |= >phase2_4.Q | | | |= >\spg:cmp_vv.. | | ____________________________________________ Information: Macrocell Utilization. Description Used Max ______________________________________ | I/O Macrocells | 8 | 8 | | Buried Macrocells | 8 | 8 | | PIM Input Connects | 31 | 36 | ______________________________________ 47 / 52 = 90 % ---------------------------------------------------------------------------- PLD Compiler Software: C37KFIT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 LOGIC BLOCK B PLACEMENT (17:53:13) Messages: ________________________________________________________________________________ 1111111111222222222233333333334444444444555555555566666666667777777777 01234567890123456789012345678901234567890123456789012345678901234567890123456789 ________________________________________________________________________________ | 0 |(\spg:cmp_vv_us_MODGEN_1\) XXXXXXXX++++++++................................................................ | 1 |(steplen_3) ......++XX++++++++++++.......................................................... | 2 |(shift_1) ..........XX++++++++++++++...................................................... | 3 |(predev_1) ..............XX++++++++++++++.................................................. | 4 |(phase2_1) ..................XX++++++++++++++.............................................. | 5 |(\spg:precount_3\) ......................XX++++++++++++++.......................................... | 6 |(\spg:precount_1\) ..........................XX++++++++++++++...................................... | 7 |(val7_3) ..............................XX++++++++++++++.................................. | 8 |(\spg:precount_2\) ..................................XX++++++++++++++.............................. | 9 |(phase1_0) ......................................XX++++++++++++++.......................... |10 |(predev_0) ..........................................XX++++++++++++++...................... |11 |(predev_3) ..............................................XX++++++++++++++.................. |12 |(shift_0) ..................................................XX++++++++++++++.............. |13 |(steplen_0) ......................................................XX++++++++++++++.......... |14 |(val3_1) ..........................................................XX++++++++++++++...... |15 |(\dacwr:dac_hold_10\) ................................................................XXXX++X+++++++++ ________________________________________________________________________________ Total count of outputs placed = 16 Total count of unique Product Terms = 41 Total Product Terms to be assigned = 41 Max Product Terms used / available = 41 / 80 = 51.26 % Control Signals for Logic Block B --------------------------------- CLK pin 19 : CLK pin 22 : clk CLK pin 99 : CLK pin 102 : CLK PT : AH : PRESET : AH : RESET : AH : OE 0 : AH : OE 1 : AH : OE 2 : AH : OE 3 : AH : Logic Block B ____________________________________________ | |= >shift_0.Q | | | |= >phase2_1.Q | | | |= >dac_data_fr.. | | | |= >dac_data_fr.. | | | |= >val3_1.Q |152|= (\spg:cmp_vv_us_MODGEN_1\) | |= >address_fro.. | | | |= >address_fro.. (steplen_3) =| | | |= >\spg:precou.. | | | |= >\rio:il_rea.. |153|= (shift_1) | |= >address_fro.. | | | |= >predev_0.Q (predev_1) =| | | |= >\dacwr:dac_.. | | | |= >\rio:il_rea.. |154|= (phase2_1) | |= >\spg:precou.. | | | |= >\spg:precou.. (\spg:precount_3\) =| | | |= >\dacwr:dac_.. | | | |= >val7_3.Q |155|= (\spg:precount_1\) | |= >\spg:cmp_vv.. | | | |= >predev_2.Q (val7_3) =| | | |= >phase1_0.Q | | | |= >to_dac_from.. |156|= (\spg:precount_2\) | |= >shift_1.Q | | | |= >dac_data_fr.. (phase1_0) =| | | |= >address_fro.. | | | |= >steplen_0.Q |157|= (predev_0) | |= >sp_req.Q | | | |> not used:327 (predev_3) =| | | |= >dac_data_fr.. | | | |= >\dacwr:dac_.. |158|= (shift_0) | |= >\dacwr:dac_.. | | | |= >steplen_3.Q (steplen_0) =| | | |> not used:332 | | | |= >predev_3.Q |159|= (val3_1) | |= >\dacwr:cmp_.. | | | |= >predev_1.Q (\dacwr:dac_hold_10\) =| | | |> not used:336 | | | |= >\spg:precou.. | | | |= >\dacwr:dac_.. | | | |> not used:339 | | ____________________________________________ Information: Macrocell Utilization. Description Used Max ______________________________________ | I/O Macrocells | 8 | 8 | | Buried Macrocells | 8 | 8 | | PIM Input Connects | 35 | 36 | ______________________________________ 51 / 52 = 98 % ---------------------------------------------------------------------------- PLD Compiler Software: C37KFIT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 LOGIC BLOCK C PLACEMENT (17:53:14) Messages: ________________________________________________________________________________ 1111111111222222222233333333334444444444555555555566666666667777777777 01234567890123456789012345678901234567890123456789012345678901234567890123456789 ________________________________________________________________________________ | 0 |(val7_5)id(0) XX++++++++++++++................................................................ | 1 |(phase2_2) ......XX++++++++++++++.......................................................... | 2 |(phase1_10)id(1) ..........XX++++++++++++++...................................................... | 3 |(dac_data_from_pc_3) ..............XX++++++++++++++.................................................. | 4 |(dac_data_from_pc_1)id(2) ..................XX++++++++++++++.............................................. | 5 |(address_from_pc_3) ......................XX++++++++++++++.......................................... | 6 |(address_from_pc_0)id(3) ..........................XX++++++++++++++...................................... | 7 |(steplen_5) ..............................XX++++++++++++++.................................. | 8 |(address_from_pc_1) ..................................XX++++++++++++++.............................. | 9 |(dac_data_from_pc_0) ......................................XX++++++++++++++.......................... |10 |(dac_data_from_pc_12)id(4) ..........................................XX++++++++++++++...................... |11 |(dac_data_from_pc_4) ..............................................XX++++++++++++++.................. |12 |(dac_data_from_pc_5)id(5) ..................................................XX++++++++++++++.............. |13 |(phase2_10) ......................................................XX++++++++++++++.......... |14 |(phase2_5)id(6) ..........................................................XX++++++++++++++...... |15 |(val6_5) ................................................................XX++++++++++++++ ________________________________________________________________________________ Total count of outputs placed = 16 Total count of unique Product Terms = 32 Total Product Terms to be assigned = 32 Max Product Terms used / available = 32 / 80 = 40.1 % Control Signals for Logic Block C --------------------------------- CLK pin 19 : CLK pin 22 : clk CLK pin 99 : CLK pin 102 : CLK PT : AH : PRESET : AH : RESET : AH : OE 0 : AH : OE 1 : AH : OE 2 : AH : OE 3 : AH : Logic Block C ____________________________________________ | |= >id(1) | | | |= >address_fro.. | | | |= >dac_data_fr.. | | | |= >id(5) | | | |= >dac_data_fr.. | 2|= (val7_5)id(0) | |= >address_fro.. | | | |= >address_fro.. (phase2_2) =| | | |= >ao_from_pc_.. | | | |= >\rio:il_rea.. | 3|= (phase1_10)id(1) | |= >id(0) | | | |= >phase2_2.Q (dac_data_from_pc_3) =| | | |= >dac_data_fr.. | | | |= >phase1_10.Q | 4|= (dac_data_from_pc_1)id(2) | |= >phase2_5.Q | | | |= >dac_data_fr.. (address_from_pc_3) =| | | |= >id(3) | | | |= >\rio:il_rea.. | 5|= (address_from_pc_0)id(3) | |= >val7_5.Q | | | |= >dac_data_fr.. (steplen_5) =| | | |> not used:359 | | | |= >dac_data_fr.. | 6|= (address_from_pc_1) | |= >id(12) | | | |= >dac_data_fr.. (dac_data_from_pc_0) =| | | |> not used:363 | | | |= >dac_data_fr.. | 7|= (dac_data_from_pc_12)id(4) | |= >dac_data_fr.. | | | |> not used:366 (dac_data_from_pc_4) =| | | |= >id(4) | | | |= >dac_data_fr.. | 8|= (dac_data_from_pc_5)id(5) | |> not used:369 | | | |> not used:370 (phase2_10) =| | | |= >phase2_10.Q | | | |= >\rio:il_rea.. | 9|= (phase2_5)id(6) | |= >dac_data_fr.. | | | |> not used:374 (val6_5) =| | | |= >val6_5.Q | | | |> not used:376 | | | |= >steplen_5.Q | | | |= >address_fro.. | | ____________________________________________ Information: Macrocell Utilization. Description Used Max ______________________________________ | I/O Macrocells | 8 | 8 | | Buried Macrocells | 8 | 8 | | PIM Input Connects | 32 | 36 | ______________________________________ 48 / 52 = 92 % ---------------------------------------------------------------------------- PLD Compiler Software: C37KFIT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 LOGIC BLOCK D PLACEMENT (17:53:14) Messages: ________________________________________________________________________________ 1111111111222222222233333333334444444444555555555566666666667777777777 01234567890123456789012345678901234567890123456789012345678901234567890123456789 ________________________________________________________________________________ | 0 |(val2_5)id(7) XX++++++++++++++................................................................ | 1 |(val1_5) ......XX++++++++++++++.......................................................... | 2 |(val1_3)id(8) ..........XX++++++++++++++...................................................... | 3 |(val0_5) ..............XX++++++++++++++.................................................. | 4 |(val0_3)id(9) ..................XX++++++++++++++.............................................. | 5 |(steplen_4) ......................XX++++++++++++++.......................................... | 6 |(phase1_5)id(10) ..........................XX++++++++++++++...................................... | 7 |(val2_1) ..............................XX++++++++++++++.................................. | 8 |(phase2_3)id(11) ..................................XX++++++++++++++.............................. | 9 |(val0_1) ......................................XX++++++++++++++.......................... |10 |(val0_4)id(12) ..........................................XX++++++++++++++...................... |11 |(val1_0) ..............................................XX++++++++++++++.................. |12 |(val1_1) ..................................................XX++++++++++++++.............. |13 |(val1_4) ......................................................XX++++++++++++++.......... |14 |(val2_0) ..........................................................XX++++++++++++++...... |15 |(val2_3) ................................................................XX++++++++++++++ ________________________________________________________________________________ Total count of outputs placed = 16 Total count of unique Product Terms = 32 Total Product Terms to be assigned = 32 Max Product Terms used / available = 32 / 80 = 40.1 % Control Signals for Logic Block D --------------------------------- CLK pin 19 : CLK pin 22 : clk CLK pin 99 : CLK pin 102 : CLK PT : AH : PRESET : AH : RESET : AH : OE 0 : AH : OE 1 : AH : OE 2 : AH : OE 3 : AH : Logic Block D ____________________________________________ | |= >val1_5.Q | | | |= >dac_data_fr.. | | | |= >dac_data_fr.. | | | |= >dac_data_fr.. | | | |= >val1_0.Q | 11|= (val2_5)id(7) | |= >address_fro.. | | | |= >address_fro.. (val1_5) =| | | |= >val1_4.Q | | | |= >\rio:il_rea.. | 12|= (val1_3)id(8) | |= >phase1_5.Q | | | |> not used:389 (val0_5) =| | | |= >val2_5.Q | | | |= >phase2_3.Q | 13|= (val0_3)id(9) | |> not used:392 | | | |= >val2_0.Q (steplen_4) =| | | |> not used:394 | | | |= >val2_3.Q | 14|= (phase1_5)id(10) | |= >address_fro.. | | | |> not used:397 (val2_1) =| | | |= >dac_data_fr.. | | | |= >val0_4.Q | 15|= (phase2_3)id(11) | |= >val1_3.Q | | | |= >\rio:il_rea.. (val0_1) =| | | |= >address_fro.. | | | |> not used:403 | 16|= (val0_4)id(12) | |= >val0_3.Q | | | |> not used:405 (val1_0) =| | | |> not used:406 | | | |= >val1_1.Q | 17|= (val1_1) | |= >val0_5.Q | | | |= >dac_data_fr.. (val1_4) =| | | |> not used:410 | | | |> not used:411 | 18|= (val2_0) | |= >steplen_4.Q | | | |> not used:413 (val2_3) =| | | |> not used:414 | | | |= >val2_1.Q | | | |= >val0_1.Q | | | |> not used:417 | | ____________________________________________ Information: Macrocell Utilization. Description Used Max ______________________________________ | I/O Macrocells | 8 | 8 | | Buried Macrocells | 8 | 8 | | PIM Input Connects | 27 | 36 | ______________________________________ 43 / 52 = 82 % ---------------------------------------------------------------------------- PLD Compiler Software: C37KFIT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 LOGIC BLOCK E PLACEMENT (17:53:14) Messages: ________________________________________________________________________________ 1111111111222222222233333333334444444444555555555566666666667777777777 01234567890123456789012345678901234567890123456789012345678901234567890123456789 ________________________________________________________________________________ | 0 |(val6_3)id(15) XX++++++++++++++................................................................ | 1 |(val5_4) ......XX++++++++++++++.......................................................... | 2 |(val5_1) ..........XX++++++++++++++...................................................... | 3 |(val4_4) ..............XX++++++++++++++.................................................. | 4 |(val4_1) ..................XX++++++++++++++.............................................. | 5 |(val3_5) ......................XX++++++++++++++.......................................... | 6 |(phase1_3) ..........................XX++++++++++++++...................................... | 7 |(val6_0) ..............................XX++++++++++++++.................................. | 8 |(val3_3) ..................................XX++++++++++++++.............................. | 9 |(val4_0) ......................................XX++++++++++++++.......................... |10 |(val4_3) ..........................................XX++++++++++++++...................... |11 |(val4_5) ..............................................XX++++++++++++++.................. |12 |(val5_0) ..................................................XX++++++++++++++.............. |13 |(val5_3) ......................................................XX++++++++++++++.......... |14 |(val5_5) ..........................................................XX++++++++++++++...... |15 |(val6_1) ................................................................XX++++++++++++++ ________________________________________________________________________________ Total count of outputs placed = 16 Total count of unique Product Terms = 32 Total Product Terms to be assigned = 32 Max Product Terms used / available = 32 / 80 = 40.1 % Control Signals for Logic Block E --------------------------------- CLK pin 19 : CLK pin 22 : clk CLK pin 99 : CLK pin 102 : CLK PT : AH : PRESET : AH : RESET : AH : OE 0 : AH : OE 1 : AH : OE 2 : AH : OE 3 : AH : Logic Block E ____________________________________________ | |= >val3_3.Q | | | |= >address_fro.. | | | |= >dac_data_fr.. | | | |= >dac_data_fr.. | | | |> not used:422 | 23|= (val6_3)id(15) | |= >address_fro.. | | | |= >address_fro.. (val5_4) =| | | |= >val4_1.Q | | | |= >\rio:il_rea.. | 24|= (val5_1) | |= >val3_5.Q | | | |= >val6_3.Q (val4_4) =| | | |= >dac_data_fr.. | | | |= >\rio:il_rea.. | 25|= (val4_1) | |= >val5_5.Q | | | |= >phase1_3.Q (val3_5) =| | | |= >val6_1.Q | | | |= >val6_0.Q | 26|= (phase1_3) | |= >address_fro.. | | | |= >val4_0.Q (val6_0) =| | | |= >val4_3.Q | | | |= >val5_1.Q | 27|= (val3_3) | |= >dac_data_fr.. | | | |= >dac_data_fr.. (val4_0) =| | | |> not used:441 | | | |= >val5_3.Q | 28|= (val4_3) | |> not used:443 | | | |= >val4_4.Q (val4_5) =| | | |> not used:445 | | | |> not used:446 | 29|= (val5_0) | |> not used:447 | | | |> not used:448 (val5_3) =| | | |> not used:449 | | | |> not used:450 | 30|= (val5_5) | |> not used:451 | | | |> not used:452 (val6_1) =| | | |= >val5_4.Q | | | |> not used:454 | | | |= >val4_5.Q | | | |= >val5_0.Q | | ____________________________________________ Information: Macrocell Utilization. Description Used Max ______________________________________ | I/O Macrocells | 8 | 8 | | Buried Macrocells | 8 | 8 | | PIM Input Connects | 27 | 36 | ______________________________________ 43 / 52 = 82 % ---------------------------------------------------------------------------- PLD Compiler Software: C37KFIT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 LOGIC BLOCK F PLACEMENT (17:53:14) Messages: ________________________________________________________________________________ 1111111111222222222233333333334444444444555555555566666666667777777777 01234567890123456789012345678901234567890123456789012345678901234567890123456789 ________________________________________________________________________________ | 0 |dio_tristate ++X+++++++++++++................................................................ | 1 |(\dacwr:cmp_vv_us_MODGEN_10\) ......XXXX++XX++++++++.......................................................... | 2 |(\dacwr:timeout_1\) ..........XX++XXXX++++++++...................................................... | 3 |(\dacwr:timeout_0\) ..............X+++++XX++XX++++.................................................. | 4 |(\dacwr:timeout_2\) ..................XX++XX++++XX++++.............................................. | 5 |(\dacwr:dac_stateSBV_0\) ......................++++XX+++XXX++++.......................................... | 6 |(\dacwr:dac_stateSBV_1\) ..........................+X++X+++++++++++...................................... | 7 |(\dacwr:dac_stateSBV_2\) ..............................++++XX+++++++X++.................................. | 8 |(to_dac_from_pc_ack) ..................................++++X++++X++++++.............................. | 9 |(sp_ack) ......................................+XX+++++++++++++.......................... |10 |(\spg:cmp_vv_us_MODGEN_4\) ..........................................X+++++++++++++++...................... |11 |(\dacwr:dac_hold_4\) ..............................................XXXXXXXXXXXXX+XX.................. |12 |UNUSED ..................................................++++++++++++++++.............. |13 |UNUSED ......................................................++++++++++++++++.......... |14 |UNUSED ..........................................................++++++++++++++++...... |15 |(\dacwr:dac_hold_3\) ................................................................XXXXXXXXXXXXXXX+ ________________________________________________________________________________ Total count of outputs placed = 13 Total count of unique Product Terms = 66 Total Product Terms to be assigned = 69 Max Product Terms used / available = 66 / 80 = 82.51 % Control Signals for Logic Block F --------------------------------- CLK pin 19 : CLK pin 22 : clk CLK pin 99 : CLK pin 102 : CLK PT : AH : PRESET : AH : RESET : AH : OE 0 : AH : OE 1 : AH : OE 2 : AH : OE 3 : AH : Logic Block F ____________________________________________ | |= >shift_0.Q | | | |= >val2_4.Q | | | |= >val1_3.Q | | | |= >val4_3.Q | | | |= >\spg:sample.. | 32|= dio_tristate | |= >\dacwr:dac_.. | | | |= >val7_4.Q (\dacwr:cmp_vv_us_MODGEN_10\) =| | | |= >val1_4.Q | | | |= >to_dac_from.. | 33|= (\dacwr:timeout_1\) | |= >\dacwr:time.. | | | |= >shift_1.Q (\dacwr:timeout_0\) =| | | |= >\dacwr:dac_.. | | | |= >\dacwr:dac_.. | 34|= (\dacwr:timeout_2\) | |= >\spg:sample.. | | | |= >\spg:sample.. (\dacwr:dac_stateSBV_0\) =| | | |= >\dacwr:dac_.. | | | |= >val7_3.Q | 35|= (\dacwr:dac_stateSBV_1\) | |= >val6_3.Q | | | |= >val5_4.Q (\dacwr:dac_stateSBV_2\) =| | | |> not used:476 | | | |= >\dacwr:time.. | 36|= (to_dac_from_pc_ack) | |= >val3_4.Q | | | |= >val6_4.Q (sp_ack) =| | | |= >shift_2.Q | | | |= >val5_3.Q | 37|= (\spg:cmp_vv_us_MODGEN_4\) | |= >val0_3.Q | | | |= >val4_4.Q (\dacwr:dac_hold_4\) =| | | |= >\dacwr:dac_.. | | | |= >dac_data_fr.. | 38|* not used | |> not used:486 | | | |= >dac_data_fr.. not used:979 >| | | |= >sp_req.Q | | | |= >val3_3.Q | 39|* not used | |= >\dacwr:cmp_.. | | | |= >val2_3.Q (\dacwr:dac_hold_3\) =| | | |= >\dacwr:dac_.. | | | |> not used:493 | | | |= >\dacwr:time.. | | | |= >val0_4.Q | | ____________________________________________ Information: Macrocell Utilization. Description Used Max ______________________________________ | I/O Macrocells | 6 | 8 | | Buried Macrocells | 7 | 8 | | PIM Input Connects | 36 | 36 | ______________________________________ 49 / 52 = 94 % ---------------------------------------------------------------------------- PLD Compiler Software: C37KFIT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 LOGIC BLOCK G PLACEMENT (17:53:14) Messages: ________________________________________________________________________________ 1111111111222222222233333333334444444444555555555566666666667777777777 01234567890123456789012345678901234567890123456789012345678901234567890123456789 ________________________________________________________________________________ | 0 |(\spg:cmp_vv_us_MODGEN_8\) XXXXXXXXXXX+++++................................................................ | 1 |UNUSED ......++++++++++++++++.......................................................... | 2 |[i/p] ..........++++++++++++++++...................................................... | 3 |UNUSED ..............++++++++++++++++.................................................. | 4 |UNUSED ..................++++++++++++++++.............................................. | 5 |UNUSED ......................++++++++++++++++.......................................... | 6 |(\spg:sample_0\) ..........................XX++++++++++++++...................................... | 7 |(phase2_12) ..............................XX++++++++++++++.................................. | 8 |(phase1_12) ..................................XX++++++++++++++.............................. | 9 |UNUSED ......................................++++++++++++++++.......................... |10 |UNUSED ..........................................++++++++++++++++...................... |11 |UNUSED ..............................................++++++++++++++++.................. |12 |UNUSED ..................................................++++++++++++++++.............. |13 |UNUSED ......................................................++++++++++++++++.......... |14 |UNUSED ..........................................................++++++++++++++++...... |15 |(\spg:MODULE_3:g1:a0:gx:u0:geq(0):c3:u1\) ................................................................XXXX++++++++++++ ________________________________________________________________________________ Total count of outputs placed = 5 Total count of unique Product Terms = 21 Total Product Terms to be assigned = 21 Max Product Terms used / available = 21 / 80 = 26.26 % Control Signals for Logic Block G --------------------------------- CLK pin 19 : CLK pin 22 : clk CLK pin 99 : CLK pin 102 : CLK PT : AH : \spg:iclk\.Q PRESET : AH : RESET : AH : OE 0 : AH : OE 1 : AH : OE 2 : AH : OE 3 : AH : Logic Block G ____________________________________________ | |= >\spg:curren.. | | | |= >address_fro.. | | | |= >\spg:cmp_vv.. | | | |= >phase2_12.Q | | | |= >phase2_9.Q | 42|= (\spg:cmp_vv_us_MODGEN_8\) | |= >address_fro.. | | | |= >address_fro.. not used:983 >| | | |> not used:503 | | | |= >\rio:il_rea.. | 43|= reset | |= >\spg:MODULE.. | | | |> not used:506 not used:985 >| | | |> not used:507 | | | |= >dac_data_fr.. | 44|* not used | |= >\spg:curren.. | | | |= >\spg:curren.. not used:987 >| | | |> not used:511 | | | |= >phase1_12.Q | 45|= (\spg:sample_0\) | |= >address_fro.. | | | |= >\spg:curren.. (phase2_12) =| | | |= >phase2_8.Q | | | |= >steplen_6.Q | 46|= (phase1_12) | |= >\spg:iclk\.Q | | | |= >steplen_7.Q not used:991 >| | | |= >\spg:curren.. | | | |= >phase2_10.Q | 47|* not used | |= >\spg:MODULE.. | | | |> not used:522 not used:993 >| | | |> not used:523 | | | |> not used:524 | 48|* not used | |= >\spg:curren.. | | | |> not used:526 not used:995 >| | | |= >\spg:curren.. | | | |= >\rio:il_rea.. | 49|* not used | |= >\spg:cmp_vv.. | | | |= >phase2_11.Q (\spg:MODULE_3:g1:a0:gx:u0:geq(0):c3:u1\) =| | | |> not used:531 | | | |> not used:532 | | | |> not used:533 | | | |= >\spg:sample.. | | ____________________________________________ Information: Macrocell Utilization. Description Used Max ______________________________________ | I/O Macrocells | 4 | 8 | | Buried Macrocells | 2 | 8 | | PIM Input Connects | 28 | 36 | ______________________________________ 34 / 52 = 65 % ---------------------------------------------------------------------------- PLD Compiler Software: C37KFIT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 LOGIC BLOCK H PLACEMENT (17:53:14) Messages: ________________________________________________________________________________ 1111111111222222222233333333334444444444555555555566666666667777777777 01234567890123456789012345678901234567890123456789012345678901234567890123456789 ________________________________________________________________________________ | 0 |(phase1_7) XX++++++++++++++................................................................ | 1 |(dac_data_from_pc_8) ......XX++++++++++++++.......................................................... | 2 |(dac_data_from_pc_2) ..........XX++++++++++++++...................................................... | 3 |(this_chip_selected) ..............XXXX++++++++++++.................................................. | 4 |(\rio:il_read_stateSBV_1\)ao_from_pc_strobe ..................XX++X+++++++++++.............................................. | 5 |(\rio:il_read_stateSBV_2\) ......................XXXX++++++++X+++.......................................... | 6>|ao_from_pc_ack ..........................X+++++++++++++++...................................... | 7 |(\rio:this_is_a_ctrl_transaction\) ..............................XXXX++X+++++++++.................................. | 8 |(\rio:il_read_stateSBV_0\) ..................................XX++++++++++++++.............................. | 9 |(address_from_pc_2) ......................................XX++++++++++++++.......................... |10 |(dac_data_from_pc_10) ..........................................XX++++++++++++++...................... |11 |(dac_data_from_pc_11) ..............................................XX++++++++++++++.................. |12 |(dac_data_from_pc_15) ..................................................XX++++++++++++++.............. |13 |(dac_data_from_pc_7) ......................................................XX++++++++++++++.......... |14 |(dac_data_from_pc_9) ..........................................................XX++++++++++++++...... |15 |(phase1_8) ................................................................XX++++++++++++++ ________________________________________________________________________________ Total count of outputs placed = 16 Total count of unique Product Terms = 38 Total Product Terms to be assigned = 40 Max Product Terms used / available = 38 / 80 = 47.51 % Control Signals for Logic Block H --------------------------------- CLK pin 19 : CLK pin 22 : clk CLK pin 99 : CLK pin 102 : CLK PT : AH : PRESET : AH : GND RESET : AH : reset OE 0 : AH : this_chip_selected.Q OE 1 : AH : OE 2 : AH : this_chip_selected.Q OE 3 : AH : Logic Block H ____________________________________________ | |= >id(15) | | | |= >address_fro.. | | | |= >dac_data_fr.. | | | |= >id(8) | | | |= >id(2) | 51|= (phase1_7) | |= >dac_data_fr.. | | | |= >\rio:il_rea.. (dac_data_from_pc_8) =| | | |= >ao_from_pc_.. | | | |= >reset | 52|= (dac_data_from_pc_2) | |= >dac_data_fr.. | | | |= >id(10) (this_chip_selected) =| | | |= >\rio:this_i.. | | | |= >id(7) | 53|= (\rio:il_read_stateSBV_1\)ao_from_pc_strobe | |= >id(9) | | | |= >address_fro.. (\rio:il_read_stateSBV_2\) =| | | |> not used:550 | | | |= >to_dac_from.. | 54|= ao_from_pc_ack | |= >address_fro.. | | | |= >id(11) (\rio:this_is_a_ctrl_transaction\) =| | | |> not used:554 | | | |= >phase1_8.Q | 55|= (\rio:il_read_stateSBV_0\) | |> not used:556 | | | |= >\rio:il_rea.. (address_from_pc_2) =| | | |= >dac_data_fr.. | | | |= >dac_data_fr.. | 56|= (dac_data_from_pc_10) | |> not used:560 | | | |> not used:561 (dac_data_from_pc_11) =| | | |> not used:562 | | | |= >\rio:il_rea.. | 57|= (dac_data_from_pc_15) | |> not used:564 | | | |> not used:565 (dac_data_from_pc_7) =| | | |> not used:566 | | | |> not used:567 | 58|= (dac_data_from_pc_9) | |= >phase1_7.Q | | | |= >address_fro.. (phase1_8) =| | | |= >dac_data_fr.. | | | |> not used:571 | | | |= >this_chip_s.. | | | |= >dac_data_fr.. | | ____________________________________________ Information: Macrocell Utilization. Description Used Max ______________________________________ | I/O Macrocells | 8 | 8 | | Buried Macrocells | 8 | 8 | | PIM Input Connects | 28 | 36 | ______________________________________ 44 / 52 = 84 % ---------------------------------------------------------------------------- PLD Compiler Software: C37KFIT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 LOGIC BLOCK I PLACEMENT (17:53:14) Messages: ________________________________________________________________________________ 1111111111222222222233333333334444444444555555555566666666667777777777 01234567890123456789012345678901234567890123456789012345678901234567890123456789 ________________________________________________________________________________ | 0 |(\dacwr:dac_hold_2\) XXXXXXXXXXXXXXX+................................................................ | 1 |(val4_2) ......++++++++++XX++++.......................................................... | 2 |(val2_2) ..........++++++++++XX++++...................................................... | 3 |(steplen_9) ..............+X++X+++++++++++.................................................. | 4 |(shift_2) ..................+X++X+++++++++++.............................................. | 5 |(phase2_9) ......................++XX++++++++++++.......................................... | 6 |(phase1_2) ..........................XX++++++++++++++...................................... | 7 |(val6_2) ..............................XX++++++++++++++.................................. | 8 |(phase1_9) ..................................XX++++++++++++++.............................. | 9 |(predev_2) ......................................XX++++++++++++++.......................... |10 |(steplen_2) ..........................................XX++++++++++++++...................... |11 |(val0_2) ..............................................XX++++++++++++++.................. |12 |(val1_2) ..................................................XX++++++++++++++.............. |13 |(val3_2) ......................................................XX++++++++++++++.......... |14 |(val5_2) ..........................................................XX++++++++++++++...... |15 |(val7_2) ................................................................XX++++++++++++++ ________________________________________________________________________________ Total count of outputs placed = 16 Total count of unique Product Terms = 45 Total Product Terms to be assigned = 45 Max Product Terms used / available = 45 / 80 = 56.26 % Control Signals for Logic Block I --------------------------------- CLK pin 19 : CLK pin 22 : clk CLK pin 99 : CLK pin 102 : CLK PT : AH : PRESET : AH : RESET : AH : OE 0 : AH : OE 1 : AH : OE 2 : AH : OE 3 : AH : Logic Block I ____________________________________________ | |= >steplen_9.Q | | | |= >\dacwr:dac_.. | | | |= >dac_data_fr.. | | | |= >val3_2.Q | | | |= >phase2_9.Q | 63|= (\dacwr:dac_hold_2\) | |= >\dacwr:dac_.. | | | |= >sp_req.Q (val4_2) =| | | |= >val4_2.Q | | | |= >to_dac_from.. | 64|= (val2_2) | |= >address_fro.. | | | |= >predev_2.Q (steplen_9) =| | | |= >steplen_2.Q | | | |= >\rio:il_rea.. | 65|= (shift_2) | |= >phase1_2.Q | | | |= >val7_2.Q (phase2_9) =| | | |= >val6_2.Q | | | |= >phase1_9.Q | 66|= (phase1_2) | |= >\spg:sample.. | | | |= >\rio:il_rea.. (val6_2) =| | | |> not used:593 | | | |= >val0_2.Q | 67|= (phase1_9) | |= >val1_2.Q | | | |> not used:596 (predev_2) =| | | |= >shift_2.Q | | | |> not used:598 | 68|= (steplen_2) | |= >val5_2.Q | | | |= >\spg:sample.. (val0_2) =| | | |= >dac_data_fr.. | | | |= >\dacwr:dac_.. | 69|= (val1_2) | |= >\dacwr:dac_.. | | | |= >\dacwr:dac_.. (val3_2) =| | | |= >val2_2.Q | | | |= >address_fro.. | 70|= (val5_2) | |= >\dacwr:cmp_.. | | | |= >\spg:sample.. (val7_2) =| | | |= >address_fro.. | | | |> not used:610 | | | |> not used:611 | | | |= >\spg:sample.. | | ____________________________________________ Information: Macrocell Utilization. Description Used Max ______________________________________ | I/O Macrocells | 8 | 8 | | Buried Macrocells | 8 | 8 | | PIM Input Connects | 34 | 36 | ______________________________________ 50 / 52 = 96 % ---------------------------------------------------------------------------- PLD Compiler Software: C37KFIT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 LOGIC BLOCK J PLACEMENT (17:53:14) Messages: ________________________________________________________________________________ 1111111111222222222233333333334444444444555555555566666666667777777777 01234567890123456789012345678901234567890123456789012345678901234567890123456789 ________________________________________________________________________________ | 0 |(\spg:kick_dac\) ++X+++++++++++++................................................................ | 1 |(S_1) ......XXXX+XXX++++++++.......................................................... | 2 |(\spg:current_count_0\) ..........X+++++++++++++++...................................................... | 3 |(S_2) ..............XXXXXXXXXXXXXXXX.................................................. | 4 |(\spg:current_count_7\) ..................++++++++++++++XX.............................................. | 5 |(\spg:current_count_6\) ......................++++++++++++++XX.......................................... | 6 |(\spg:current_count_5\) ..........................++++++++++++XX++...................................... | 7 |(\spg:current_count_4\) ..............................XX++++++++++++++.................................. | 8 |(\spg:current_count_3\) ..................................XX++++++++++++++.............................. | 9 |(\spg:current_count_2\) ......................................++XX++++++++++++.......................... |10 |(\spg:current_count_1\) ..........................................XX++++++++++++++...................... |11 |(\spg:cmp_vv_us_MODGEN_3\) ..............................................XXXX++++++++++++.................. |12 |(\spg:current_count_9\) ..................................................XX++++++++++++++.............. |13 |(\spg:current_count_8\) ......................................................XX++++++++++++++.......... |14>|sinphase_zeros ..........................................................XX++++++++++++++...... |15 |(\spg:MODULE_3:g1:a0:gx:u0:eq_5\) ................................................................XXXXXXXXXXXX++++ ________________________________________________________________________________ Total count of outputs placed = 16 Total count of unique Product Terms = 61 Total Product Terms to be assigned = 61 Max Product Terms used / available = 61 / 80 = 76.26 % Control Signals for Logic Block J --------------------------------- CLK pin 19 : CLK pin 22 : CLK pin 99 : CLK pin 102 : CLK PT : AH : \spg:iclk\.Q PRESET : AH : RESET : AH : OE 0 : AH : OE 1 : AH : OE 2 : AH : OE 3 : AH : Logic Block J ____________________________________________ | |= >steplen_9.Q | | | |= >\spg:curren.. | | | |= >\spg:cmp_vv.. | | | |= >\spg:MODULE.. | | | |= >\spg:curren.. | 72|= (\spg:kick_dac\) | |= >\spg:curren.. | | | |= >\spg:curren.. (S_1) =| | | |= >sinphase_ze.. | | | |= >phase1_9.Q | 73|= (\spg:current_count_0\) | |= >steplen_1.Q | | | |= >\spg:curren.. (S_2) =| | | |= >steplen_2.Q | | | |= >\spg:curren.. | 74|= (\spg:current_count_7\) | |= >\spg:curren.. | | | |= >\spg:curren.. (\spg:current_count_6\) =| | | |= >phase1_11.Q | | | |= >phase1_12.Q | 75|= (\spg:current_count_5\) | |= >\spg:curren.. | | | |= >S_1.CMB (\spg:current_count_4\) =| | | |= >\spg:curren.. | | | |= >phase1_8.Q | 76|= (\spg:current_count_3\) | |= >phase1_10.Q | | | |> not used:635 (\spg:current_count_2\) =| | | |= >steplen_8.Q | | | |= >steplen_0.Q | 77|= (\spg:current_count_1\) | |> not used:638 | | | |= >\spg:curren.. (\spg:cmp_vv_us_MODGEN_3\) =| | | |= >S_2.CMB | | | |= >\spg:MODULE.. | 78|= (\spg:current_count_9\) | |= >\spg:cmp_vv.. | | | |= >steplen_3.Q (\spg:current_count_8\) =| | | |= >\spg:curren.. | | | |> not used:645 | 79|= sinphase_zeros | |= >steplen_4.Q | | | |= >\spg:curren.. (\spg:MODULE_3:g1:a0:gx:u0:eq_5\) =| | | |= >\spg:curren.. | | | |= >\spg:curren.. | | | |= >steplen_5.Q | | | |= >\spg:iclk\.Q | | ____________________________________________ Information: Macrocell Utilization. Description Used Max ______________________________________ | I/O Macrocells | 8 | 8 | | Buried Macrocells | 8 | 8 | | PIM Input Connects | 36 | 36 | ______________________________________ 52 / 52 = 100 % ---------------------------------------------------------------------------- PLD Compiler Software: C37KFIT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 LOGIC BLOCK K PLACEMENT (17:53:14) Messages: ________________________________________________________________________________ 1111111111222222222233333333334444444444555555555566666666667777777777 01234567890123456789012345678901234567890123456789012345678901234567890123456789 ________________________________________________________________________________ | 0>|dad(0) XXXX++++++++++++................................................................ | 1 |UNUSED ......++++++++++++++++.......................................................... | 2>|dad(1) ..........XXXX++++++++++++...................................................... | 3 |(\spg:iclk\) ..............X+++++++++++++++.................................................. | 4>|dad(2) ..................XXXX++++++++++++.............................................. | 5 |UNUSED ......................++++++++++++++++.......................................... | 6>|dad(3) ..........................XXXX++++++++++++...................................... | 7 |UNUSED ..............................++++++++++++++++.................................. | 8>|dad(4) ..................................XXXX++++++++++++.............................. | 9 |UNUSED ......................................++++++++++++++++.......................... |10>|dad(5) ..........................................XXXX++++++++++++...................... |11 |UNUSED ..............................................++++++++++++++++.................. |12>|dad(6) ..................................................XXXX++++++++++++.............. |13 |UNUSED ......................................................++++++++++++++++.......... |14>|dad(7) ..........................................................XXXX++++++++++++...... |15 |(\dacwr:dac_hold_1\) ................................................................XXXXXXXXXXXXXXX+ ________________________________________________________________________________ Total count of outputs placed = 10 Total count of unique Product Terms = 46 Total Product Terms to be assigned = 48 Max Product Terms used / available = 48 / 80 = 60.1 % Control Signals for Logic Block K --------------------------------- CLK pin 19 : CLK pin 22 : clk CLK pin 99 : CLK pin 102 : CLK PT : AH : PRESET : AH : RESET : AH : OE 0 : AH : OE 1 : AH : OE 2 : AH : OE 3 : AH : Logic Block K ____________________________________________ | |> not used:652 | | | |= >\dacwr:dac_.. | | | |= >dad(1).Q | | | |= >dac_data_fr.. | | | |= >\spg:sample.. | 82|= dad(0) | |= >val1_1.Q | | | |= >\spg:cmp_vv.. not used:1047 >| | | |= >\dacwr:dac_.. | | | |= >to_dac_from.. | 83|= dad(1) | |= >dad(3).Q | | | |= >\dacwr:dac_.. (\spg:iclk\) =| | | |= >dad(0).Q | | | |= >\dacwr:dac_.. | 84|= dad(2) | |= >\dacwr:dac_.. | | | |= >\dacwr:dac_.. not used:1051 >| | | |= >val6_1.Q | | | |= >dad(4).Q | 85|= dad(3) | |= >\dacwr:dac_.. | | | |= >dad(5).Q not used:1053 >| | | |= >val0_1.Q | | | |= >val5_1.Q | 86|= dad(4) | |= >dad(6).Q | | | |> not used:674 not used:1055 >| | | |= >dad(2).Q | | | |= >val7_1.Q | 87|= dad(5) | |= >dad(7).Q | | | |= >\spg:sample.. not used:1057 >| | | |= >\dacwr:dac_.. | | | |= >val4_1.Q | 88|= dad(6) | |= >\dacwr:dac_.. | | | |= >\dacwr:dac_.. not used:1059 >| | | |= >sp_req.Q | | | |> not used:684 | 89|= dad(7) | |= >\dacwr:cmp_.. | | | |> not used:686 (\dacwr:dac_hold_1\) =| | | |= >val3_1.Q | | | |= >val2_1.Q | | | |= >\dacwr:dac_.. | | | |= >\spg:sample.. | | ____________________________________________ Information: Macrocell Utilization. Description Used Max ______________________________________ | I/O Macrocells | 8 | 8 | | Buried Macrocells | 2 | 8 | | PIM Input Connects | 35 | 36 | ______________________________________ 45 / 52 = 86 % ---------------------------------------------------------------------------- PLD Compiler Software: C37KFIT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 LOGIC BLOCK L PLACEMENT (17:53:14) Messages: ________________________________________________________________________________ 1111111111222222222233333333334444444444555555555566666666667777777777 01234567890123456789012345678901234567890123456789012345678901234567890123456789 ________________________________________________________________________________ | 0>|dad(8) XXXX++++++++++++................................................................ | 1 |UNUSED ......++++++++++++++++.......................................................... | 2>|dad(9) ..........XXXX++++++++++++...................................................... | 3 |(\dacwr:dac_hold_12\) ..............XXXX++++XXXX++++.................................................. | 4>|dad(10) ..................XXXX++++++++++++.............................................. | 5 |(\dacwr:dac_hold_11\) ......................++++X+XX++XX++++.......................................... | 6>|dad(11) ..........................+X++X+++++XX++++...................................... | 7 |(\dacwr:dac_hold_9\) ..............................+X++XX++XX++++++.................................. | 8>|dad(12) ..................................++++++XX++XX++++.............................. | 9 |(dac_data_from_pc_6) ......................................++++++++++XX++++.......................... |10>|daaddr(0) ..........................................XX+++++++++++X++...................... |11 |(phase2_11) ..............................................XX++++++++++++++.................. |12>|daaddr(1) ..................................................XX++X+++++++++++.............. |13 |UNUSED ......................................................++++++++++++++++.......... |14>|daaddr(2) ..........................................................XX++X+++++++++++...... |15 |UNUSED ................................................................++++++++++++++++ ________________________________________________________________________________ Total count of outputs placed = 13 Total count of unique Product Terms = 51 Total Product Terms to be assigned = 51 Max Product Terms used / available = 51 / 80 = 63.76 % Control Signals for Logic Block L --------------------------------- CLK pin 19 : CLK pin 22 : clk CLK pin 99 : CLK pin 102 : CLK PT : AH : PRESET : AH : RESET : AH : OE 0 : AH : OE 1 : AH : OE 2 : AH : OE 3 : AH : Logic Block L ____________________________________________ | |= >\dacwr:dac_.. | | | |= >\dacwr:dac_.. | | | |= >shift_2.Q | | | |= >dac_data_fr.. | | | |= >dad(9).Q | 91|= dad(8) | |= >address_fro.. | | | |= >phase2_11.Q not used:1063 >| | | |= >daaddr(1).Q | | | |= >\rio:il_rea.. | 92|= dad(9) | |= >address_fro.. | | | |= >\dacwr:dac_.. (\dacwr:dac_hold_12\) =| | | |= >dad(11).Q | | | |= >dac_data_fr.. | 93|= dad(10) | |= >\dacwr:dac_.. | | | |= >address_fro.. (\dacwr:dac_hold_11\) =| | | |= >dad(12).Q | | | |= >\rio:il_rea.. | 94|= dad(11) | |= >ao_from_pc_.. | | | |= >daaddr(0).Q (\dacwr:dac_hold_9\) =| | | |> not used:710 | | | |= >to_dac_from.. | 95|= dad(12) | |= >shift_1.Q | | | |= >shift_0.Q (dac_data_from_pc_6) =| | | |= >address_fro.. | | | |> not used:715 | 96|= daaddr(0) | |= >daaddr(2).Q | | | |> not used:717 (phase2_11) =| | | |= >dac_data_fr.. | | | |= >\dacwr:dac_.. | 97|= daaddr(1) | |= >\dacwr:dac_.. | | | |= >dad(8).Q not used:1075 >| | | |= >sp_req.Q | | | |= >\rio:il_rea.. | 98|= daaddr(2) | |= >\dacwr:cmp_.. | | | |= >id(6) not used:1077 >| | | |= >dac_data_fr.. | | | |= >\dacwr:dac_.. | | | |= >\dacwr:dac_.. | | | |= >dad(10).Q | | ____________________________________________ Information: Macrocell Utilization. Description Used Max ______________________________________ | I/O Macrocells | 8 | 8 | | Buried Macrocells | 5 | 8 | | PIM Input Connects | 36 | 36 | ______________________________________ 49 / 52 = 94 % ---------------------------------------------------------------------------- PLD Compiler Software: C37KFIT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 LOGIC BLOCK M PLACEMENT (17:53:14) Messages: ________________________________________________________________________________ 1111111111222222222233333333334444444444555555555566666666667777777777 01234567890123456789012345678901234567890123456789012345678901234567890123456789 ________________________________________________________________________________ | 0>|da_not_wr ++X+++++++++++++................................................................ | 1 |(\spg:sample_2\) ......XX++++++++++++++.......................................................... | 2>|da_not_cs ..........X+++++++++++++++...................................................... | 3 |UNUSED ..............++++++++++++++++.................................................. | 4>|da_not_ldcd ..................X+++++++++++++++.............................................. | 5 |(\spg:MODULE_8:g1:a0:gx:u0:geq(0):c3:u1\) ......................XXXX++++++++++++.......................................... | 6>|da_not_ldab ..........................X+++++++++++++++...................................... | 7 |(\spg:sample_1\) ..............................XX++++++++++++++.................................. | 8>|da_not_ldef ..................................X+++++++++++++++.............................. | 9 |(\dacwr:dac_hold_5\) ......................................XXXXXXXXXXXXX+XX.......................... |10>|da_not_ldgh ..........................................+++++++++X++++++...................... |11 |(to_dac_from_pc_req) ..............................................++++++++X+++++++.................. |12 |UNUSED ..................................................++++++++++++++++.............. |13 |UNUSED ......................................................++++++++++++++++.......... |14 |UNUSED ..........................................................++++++++++++++++...... |15 |UNUSED ................................................................++++++++++++++++ ________________________________________________________________________________ Total count of outputs placed = 11 Total count of unique Product Terms = 30 Total Product Terms to be assigned = 30 Max Product Terms used / available = 30 / 80 = 37.51 % Control Signals for Logic Block M --------------------------------- CLK pin 19 : CLK pin 22 : clk CLK pin 99 : CLK pin 102 : CLK PT : AH : \spg:iclk\.Q PRESET : AH : GND RESET : AH : reset OE 0 : AH : OE 1 : AH : OE 2 : AH : OE 3 : AH : Logic Block M ____________________________________________ | |= >val1_5.Q | | | |= >\spg:sample.. | | | |= >dac_data_fr.. | | | |= >\dacwr:cmp_.. | | | |= >\spg:sample.. |103|= da_not_wr | |= >\spg:cmp_vv.. | | | |= >sp_req.Q (\spg:sample_2\) =| | | |= >\dacwr:dac_.. | | | |= >phase2_6.Q |104|= da_not_cs | |= >val3_5.Q | | | |= >val5_5.Q not used:1081 >| | | |= >\spg:curren.. | | | |= >\dacwr:dac_.. |105|= da_not_ldcd | |= >\dacwr:dac_.. | | | |= >\spg:sample.. (\spg:MODULE_8:g1:a0:gx:u0:geq(0):c3:u1\) =| | | |= >\dacwr:dac_.. | | | |= >\spg:MODULE.. |106|= da_not_ldab | |= >val7_5.Q | | | |= >val2_5.Q (\spg:sample_1\) =| | | |> not used:749 | | | |= >\spg:cmp_vv.. |107|= da_not_ldef | |= >daaddr(1).Q | | | |= >\rio:il_rea.. (\dacwr:dac_hold_5\) =| | | |= >val0_5.Q | | | |= >phase2_7.Q |108|= da_not_ldgh | |= >daaddr(2).Q | | | |> not used:756 (to_dac_from_pc_req) =| | | |> not used:757 | | | |= >\rio:il_rea.. |109|* not used | |= >\dacwr:dac_.. | | | |> not used:760 not used:1091 >| | | |> not used:761 | | | |= >to_dac_from.. |110|* not used | |= >\spg:curren.. | | | |= >reset not used:1093 >| | | |= >val6_5.Q | | | |> not used:766 | | | |= >val4_5.Q | | | |= >\spg:iclk\.Q | | ____________________________________________ Information: Macrocell Utilization. Description Used Max ______________________________________ | I/O Macrocells | 6 | 8 | | Buried Macrocells | 5 | 8 | | PIM Input Connects | 33 | 36 | ______________________________________ 44 / 52 = 84 % ---------------------------------------------------------------------------- PLD Compiler Software: C37KFIT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 LOGIC BLOCK N PLACEMENT (17:53:14) Messages: ________________________________________________________________________________ 1111111111222222222233333333334444444444555555555566666666667777777777 01234567890123456789012345678901234567890123456789012345678901234567890123456789 ________________________________________________________________________________ | 0>|da_not_clr ++X+++++++++++++................................................................ | 1 |(val7_4) ......XX++++++++++++++.......................................................... | 2 |(val7_0) ..........XX++++++++++++++...................................................... | 3 |(val3_4) ..............XX++++++++++++++.................................................. | 4 |(val3_0) ..................XX++++++++++++++.............................................. | 5 |(val2_4) ......................XX++++++++++++++.......................................... | 6 |(val0_0) ..........................XX++++++++++++++...................................... | 7 |(phase2_4) ..............................XX++++++++++++++.................................. | 8 |(phase2_0) ..................................XX++++++++++++++.............................. | 9 |(\dacwr:dac_hold_0\) ......................................XXXXXXXXXXXX++XX.......................... |10>|shdn(0) ..........................................++++++++X+++++++...................... |11 |(phase1_4) ..............................................+++++X++X+++++++.................. |12>|shdn(1) ..................................................X+++++++X+++++++.............. |13 |(val6_4) ......................................................++XX++++++++++++.......... |14>|shdn(2) ..........................................................X+++++++++++++++...... |15 |(\spg:precount_0\) ................................................................++X+++++++++++++ ________________________________________________________________________________ Total count of outputs placed = 16 Total count of unique Product Terms = 36 Total Product Terms to be assigned = 39 Max Product Terms used / available = 38 / 80 = 47.51 % Control Signals for Logic Block N --------------------------------- CLK pin 19 : CLK pin 22 : clk CLK pin 99 : CLK pin 102 : CLK PT : AH : PRESET : AH : GND RESET : AH : reset OE 0 : AH : OE 1 : AH : OE 2 : AH : OE 3 : AH : Logic Block N ____________________________________________ | |= >val6_4.Q | | | |= >address_fro.. | | | |= >val0_0.Q | | | |= >\dacwr:cmp_.. | | | |= >val1_0.Q |112|= da_not_clr | |= >address_fro.. | | | |= >val7_4.Q (val7_4) =| | | |= >\dacwr:dac_.. | | | |= >reset |113|= (val7_0) | |= >val2_0.Q | | | |= >phase1_4.Q (val3_4) =| | | |= >\dacwr:dac_.. | | | |= >\rio:il_rea.. |114|= (val3_0) | |= >\spg:precou.. | | | |= >\dacwr:dac_.. (val2_4) =| | | |= >phase2_0.Q | | | |= >val6_0.Q |115|= (val0_0) | |= >address_fro.. | | | |= >\rio:il_rea.. (phase2_4) =| | | |= >val7_0.Q | | | |= >to_dac_from.. |116|= (phase2_0) | |= >dac_data_fr.. | | | |= >val5_0.Q (\dacwr:dac_hold_0\) =| | | |= >val3_0.Q | | | |= >val2_4.Q |117|= shdn(0) | |= >sp_req.Q | | | |= >\spg:sample.. (phase1_4) =| | | |= >dac_data_fr.. | | | |= >\spg:cmp_vv.. |118|= shdn(1) | |= >\dacwr:dac_.. | | | |= >\spg:sample.. (val6_4) =| | | |> not used:800 | | | |= >val3_4.Q |119|= shdn(2) | |> not used:802 | | | |= >val4_0.Q (\spg:precount_0\) =| | | |= >address_fro.. | | | |> not used:805 | | | |= >phase2_4.Q | | | |= >\spg:sample.. | | ____________________________________________ Information: Macrocell Utilization. Description Used Max ______________________________________ | I/O Macrocells | 8 | 8 | | Buried Macrocells | 8 | 8 | | PIM Input Connects | 36 | 36 | ______________________________________ 52 / 52 = 100 % ---------------------------------------------------------------------------- PLD Compiler Software: C37KFIT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 LOGIC BLOCK O PLACEMENT (17:53:14) Messages: ________________________________________________________________________________ 1111111111222222222233333333334444444444555555555566666666667777777777 01234567890123456789012345678901234567890123456789012345678901234567890123456789 ________________________________________________________________________________ | 0 |(\dacwr:dac_hold_7\) XXXXXXXXXXXXXXX+................................................................ | 1 |(val6_7) ......++++++++++XX++++.......................................................... | 2 |(val4_7) ..........++++++++++XX++++...................................................... | 3 |(val1_7) ..............+X++X+++++++++++.................................................. | 4 |(steplen_7) ..................+X++X+++++++++++.............................................. | 5 |(phase2_7) ......................++XX++++++++++++.......................................... | 6 |(phase1_1) ..........................XX++++++++++++++...................................... | 7 |(val7_7) ..............................XX++++++++++++++.................................. | 8 |(phase1_11) ..................................XX++++++++++++++.............................. | 9 |(steplen_1) ......................................XX++++++++++++++.......................... |10 |(val0_7) ..........................................XX++++++++++++++...................... |11 |(val2_7) ..............................................XX++++++++++++++.................. |12 |(val3_7) ..................................................XX++++++++++++++.............. |13 |(val5_7) ......................................................XX++++++++++++++.......... |14 |(val7_1) ..........................................................XX++++++++++++++...... |15 |(\dacwr:dac_hold_8\) ................................................................XXXX++X+++++++++ ________________________________________________________________________________ Total count of outputs placed = 16 Total count of unique Product Terms = 48 Total Product Terms to be assigned = 48 Max Product Terms used / available = 48 / 80 = 60.1 % Control Signals for Logic Block O --------------------------------- CLK pin 19 : CLK pin 22 : clk CLK pin 99 : CLK pin 102 : CLK PT : AH : PRESET : AH : RESET : AH : OE 0 : AH : OE 1 : AH : OE 2 : AH : OE 3 : AH : Logic Block O ____________________________________________ | |= >dac_data_fr.. | | | |= >\dacwr:dac_.. | | | |= >\spg:sample.. | | | |= >dac_data_fr.. | | | |= >\spg:sample.. |122|= (\dacwr:dac_hold_7\) | |= >address_fro.. | | | |= >address_fro.. (val6_7) =| | | |= >phase1_11.Q | | | |= >to_dac_from.. |123|= (val4_7) | |= >address_fro.. | | | |= >val4_7.Q (val1_7) =| | | |= >\dacwr:dac_.. | | | |= >\rio:il_rea.. |124|= (steplen_7) | |= >\dacwr:dac_.. | | | |= >val7_7.Q (phase2_7) =| | | |= >\dacwr:dac_.. | | | |= >dac_data_fr.. |125|= (phase1_1) | |= >steplen_1.Q | | | |= >val0_7.Q (val7_7) =| | | |> not used:827 | | | |= >val2_7.Q |126|= (phase1_11) | |= >val1_7.Q | | | |= >val5_7.Q (steplen_1) =| | | |= >address_fro.. | | | |= >val7_1.Q |127|= (val0_7) | |= >phase1_1.Q | | | |= >val6_7.Q (val2_7) =| | | |= >val3_7.Q | | | |= >\rio:il_rea.. |128|= (val3_7) | |= >\dacwr:dac_.. | | | |= >steplen_7.Q (val5_7) =| | | |= >sp_req.Q | | | |= >phase2_7.Q |129|= (val7_1) | |= >\dacwr:cmp_.. | | | |> not used:842 (\dacwr:dac_hold_8\) =| | | |= >dac_data_fr.. | | | |> not used:844 | | | |= >\dacwr:dac_.. | | | |= >\spg:sample.. | | ____________________________________________ Information: Macrocell Utilization. Description Used Max ______________________________________ | I/O Macrocells | 8 | 8 | | Buried Macrocells | 8 | 8 | | PIM Input Connects | 36 | 36 | ______________________________________ 52 / 52 = 100 % ---------------------------------------------------------------------------- PLD Compiler Software: C37KFIT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 LOGIC BLOCK P PLACEMENT (17:53:14) Messages: ________________________________________________________________________________ 1111111111222222222233333333334444444444555555555566666666667777777777 01234567890123456789012345678901234567890123456789012345678901234567890123456789 ________________________________________________________________________________ | 0 |(\dacwr:dac_hold_6\) XXXXXXXXXXXXXXX+................................................................ | 1 |(val4_6) ......++++++++++XX++++.......................................................... | 2 |(val2_6) ..........++++++++++XX++++...................................................... | 3 |(steplen_8) ..............+X++X+++++++++++.................................................. | 4 |(sp_req) ..................+X++X+++++++++++.............................................. | 5 |(phase2_6) ......................++XX++++++++++++.......................................... | 6 |(\spg:kdacSBV_0\) ..........................XX++++++++++++++...................................... | 7 |(val6_6) ..............................XX++++++++++++++.................................. | 8 |(phase1_6) ..................................XX++++++++++++++.............................. | 9 |(phase2_8) ......................................XX++++++++++++++.......................... |10 |(steplen_6) ..........................................XX++++++++++++++...................... |11 |(val0_6) ..............................................XX++++++++++++++.................. |12 |(val1_6) ..................................................XX++++++++++++++.............. |13 |(val3_6) ......................................................XX++++++++++++++.......... |14 |(val5_6) ..........................................................XX++++++++++++++...... |15 |(val7_6) ................................................................XX++++++++++++++ ________________________________________________________________________________ Total count of outputs placed = 16 Total count of unique Product Terms = 45 Total Product Terms to be assigned = 45 Max Product Terms used / available = 45 / 80 = 56.26 % Control Signals for Logic Block P --------------------------------- CLK pin 19 : CLK pin 22 : clk CLK pin 99 : CLK pin 102 : CLK PT : AH : PRESET : AH : RESET : AH : OE 0 : AH : OE 1 : AH : OE 2 : AH : OE 3 : AH : Logic Block P ____________________________________________ | |= >dac_data_fr.. | | | |= >\dacwr:dac_.. | | | |= >val2_6.Q | | | |= >\dacwr:cmp_.. | | | |= >sp_ack.Q |131|= (\dacwr:dac_hold_6\) | |= >\dacwr:dac_.. | | | |= >address_fro.. (val4_6) =| | | |= >val3_6.Q | | | |= >to_dac_from.. |132|= (val2_6) | |= >val5_6.Q | | | |= >\dacwr:dac_.. (steplen_8) =| | | |= >val7_6.Q | | | |= >phase1_6.Q |133|= (sp_req) | |= >\dacwr:dac_.. | | | |= >\dacwr:dac_.. (phase2_6) =| | | |= >\spg:kdacSB.. | | | |= >\spg:kick_d.. |134|= (\spg:kdacSBV_0\) | |= >address_fro.. | | | |= >\rio:il_rea.. (val6_6) =| | | |= >val4_6.Q | | | |= >steplen_6.Q |135|= (phase1_6) | |> not used:868 | | | |= >val0_6.Q (phase2_8) =| | | |= >address_fro.. | | | |> not used:871 |136|= (steplen_6) | |= >sp_req.Q | | | |= >\spg:sample.. (val0_6) =| | | |> not used:874 | | | |= >val1_6.Q |137|= (val1_6) | |= >steplen_8.Q | | | |= >\spg:sample.. (val3_6) =| | | |= >dac_data_fr.. | | | |= >\rio:il_rea.. |138|= (val5_6) | |= >phase2_6.Q | | | |= >address_fro.. (val7_6) =| | | |> not used:882 | | | |= >val6_6.Q | | | |= >phase2_8.Q | | | |= >\spg:sample.. | | ____________________________________________ Information: Macrocell Utilization. Description Used Max ______________________________________ | I/O Macrocells | 8 | 8 | | Buried Macrocells | 8 | 8 | | PIM Input Connects | 35 | 36 | ______________________________________ 51 / 52 = 98 % ---------------------------------------------------------------------------- PLD Compiler Software: C37KFIT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 PINOUT INFORMATION (17:53:14) Device: cy37256p160 Package: cy37256p160-125ac 1 : GND > 2 : (val7_5)id(0) > 3 : (phase1_10)id(1) > 4 : (dac_data_from_pc_1)id(2) > 5 : (address_from_pc_0)id(3) 6 : (address_from_pc_1) > 7 : (dac_data_from_pc_12)id(4) > 8 : (dac_data_from_pc_5)id(5) > 9 : (phase2_5)id(6) 10 : GND > 11 : (val2_5)id(7) > 12 : (val1_3)id(8) > 13 : (val0_3)id(9) > 14 : (phase1_5)id(10) > 15 : (phase2_3)id(11) > 16 : (val0_4)id(12) 17 : (val1_1) 18 : (val2_0) 19 : Not Used 20 : VCC 21 : GND > 22 : clk > 23 : (val6_3)id(15) 24 : (val5_1) 25 : (val4_1) 26 : (phase1_3) 27 : (val3_3) 28 : (val4_3) 29 : (val5_0) 30 : (val5_5) 31 : GND 32 : dio_tristate 33 : (\dacwr:timeout_1\) 34 : (\dacwr:timeout_2\) 35 : (\dacwr:dac_stateSBV_1\) 36 : (to_dac_from_pc_ack) 37 : (\spg:cmp_vv_us_MODGEN_4\) 38 : Not Used 39 : Not Used 40 : VCC 41 : GND 42 : (\spg:cmp_vv_us_MODGEN_8\) > 43 : reset 44 : Not Used 45 : (\spg:sample_0\) 46 : (phase1_12) 47 : Not Used 48 : Not Used 49 : Not Used 50 : GND 51 : (phase1_7) 52 : (dac_data_from_pc_2) > 53 : (\rio:il_read_stateSBV_1\)ao_from_pc_strobe > 54 : ao_from_pc_ack 55 : (\rio:il_read_stateSBV_0\) 56 : (dac_data_from_pc_10) 57 : (dac_data_from_pc_15) 58 : (dac_data_from_pc_9) 59 : Not Used 60 : VCC 61 : GND 62 : VCC 63 : (\dacwr:dac_hold_2\) 64 : (val2_2) 65 : (shift_2) 66 : (phase1_2) 67 : (phase1_9) 68 : (steplen_2) 69 : (val1_2) 70 : (val5_2) 71 : GND 72 : (\spg:kick_dac\) 73 : (\spg:current_count_0\) 74 : (\spg:current_count_7\) 75 : (\spg:current_count_5\) 76 : (\spg:current_count_3\) 77 : (\spg:current_count_1\) 78 : (\spg:current_count_9\) > 79 : sinphase_zeros 80 : VCC 81 : GND > 82 : dad(0) > 83 : dad(1) > 84 : dad(2) > 85 : dad(3) > 86 : dad(4) > 87 : dad(5) > 88 : dad(6) > 89 : dad(7) 90 : GND > 91 : dad(8) > 92 : dad(9) > 93 : dad(10) > 94 : dad(11) > 95 : dad(12) > 96 : daaddr(0) > 97 : daaddr(1) > 98 : daaddr(2) 99 : Not Used 100 : VCC 101 : GND 102 : Not Used > 103 : da_not_wr > 104 : da_not_cs > 105 : da_not_ldcd > 106 : da_not_ldab > 107 : da_not_ldef > 108 : da_not_ldgh 109 : Not Used 110 : Not Used 111 : GND > 112 : da_not_clr 113 : (val7_0) 114 : (val3_0) 115 : (val0_0) 116 : (phase2_0) > 117 : shdn(0) > 118 : shdn(1) > 119 : shdn(2) 120 : VCC 121 : GND 122 : (\dacwr:dac_hold_7\) 123 : (val4_7) 124 : (steplen_7) 125 : (phase1_1) 126 : (phase1_11) 127 : (val0_7) 128 : (val3_7) 129 : (val7_1) 130 : GND 131 : (\dacwr:dac_hold_6\) 132 : (val2_6) 133 : (sp_req) 134 : (\spg:kdacSBV_0\) 135 : (phase1_6) 136 : (steplen_6) 137 : (val1_6) 138 : (val5_6) 139 : Not Used 140 : VCC 141 : GND 142 : VCC 143 : (\spg:MODULE_8:g1:a0:gx:u0:eq_5\) 144 : (\spg:current_phase_7\) 145 : (\spg:current_phase_2\) 146 : (\spg:current_phase_10\) 147 : (\spg:current_phase_11\) 148 : (\spg:current_phase_3\) 149 : (\spg:current_phase_6\) 150 : (\spg:current_phase_0\) 151 : GND 152 : (\spg:cmp_vv_us_MODGEN_1\) 153 : (shift_1) 154 : (phase2_1) 155 : (\spg:precount_1\) 156 : (\spg:precount_2\) 157 : (predev_0) 158 : (shift_0) 159 : (val3_1) 160 : VCC ---------------------------------------------------------------------------- PLD Compiler Software: C37KFIT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 RESOURCE UTILIZATION (17:53:14) Information: Macrocell Utilization. Description Used Max ______________________________________ | Dedicated Inputs | 0 | 1 | | Clock/Inputs | 1 | 4 | | I/O Macrocells | 120 | 128 | | Buried Macrocells | 109 | 128 | | PIM Input Connects | 525 | 624 | ______________________________________ 755 / 885 = 85 % Required Max (Available) CLOCK/LATCH ENABLE signals 2 20 Input REG/LATCH signals 0 133 Input PIN signals 1 5 Input PINs using I/O cells 1 1 Output PIN signals 119 127 Total PIN signals 121 133 Macrocells Used 228 256 Unique Product Terms 675 1280 ---------------------------------------------------------------------------- PLD Compiler Software: C37KFIT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 PRESET/RESET AND OUTPUT ENABLE COMBINATIONS PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 195 count of output equations = 175 ==>OE: this_chip_selected.Q Used by Logic Blocks: H count of OE equations = 1 ==>OE: GND or VCC count of OE equations = 174 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 3 count of output equations = 0 ==>OE: GND or VCC count of OE equations = 0 PRESET: GND RESET : reset CLOCK PT : NULL Used by Logic Blocks: HN Total unique inputs = 11 count of output equations = 4 ==>OE: GND or VCC count of OE equations = 4 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 87 count of output equations = 21 ==>OE: GND or VCC count of OE equations = 21 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 3 count of output equations = 0 ==>OE: GND or VCC count of OE equations = 0 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 4 count of output equations = 0 ==>OE: GND or VCC count of OE equations = 0 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 5 count of output equations = 0 ==>OE: GND or VCC count of OE equations = 0 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 6 count of output equations = 0 ==>OE: GND or VCC count of OE equations = 0 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 7 count of output equations = 0 ==>OE: GND or VCC count of OE equations = 0 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 8 count of output equations = 0 ==>OE: GND or VCC count of OE equations = 0 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 9 count of output equations = 0 ==>OE: GND or VCC count of OE equations = 0 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 10 count of output equations = 0 ==>OE: GND or VCC count of OE equations = 0 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 11 count of output equations = 0 ==>OE: GND or VCC count of OE equations = 0 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 12 count of output equations = 0 ==>OE: GND or VCC count of OE equations = 0 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 4 count of output equations = 0 ==>OE: GND or VCC count of OE equations = 0 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 14 count of output equations = 0 ==>OE: GND or VCC count of OE equations = 0 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 15 count of output equations = 0 ==>OE: GND or VCC count of OE equations = 0 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 16 count of output equations = 0 ==>OE: GND or VCC count of OE equations = 0 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 5 count of output equations = 0 ==>OE: GND or VCC count of OE equations = 0 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 6 count of output equations = 0 ==>OE: GND or VCC count of OE equations = 0 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 7 count of output equations = 0 ==>OE: GND or VCC count of OE equations = 0 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 8 count of output equations = 0 ==>OE: GND or VCC count of OE equations = 0 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 9 count of output equations = 0 ==>OE: GND or VCC count of OE equations = 0 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 10 count of output equations = 0 ==>OE: GND or VCC count of OE equations = 0 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 11 count of output equations = 0 ==>OE: GND or VCC count of OE equations = 0 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 12 count of output equations = 0 ==>OE: GND or VCC count of OE equations = 0 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 13 count of output equations = 0 ==>OE: GND or VCC count of OE equations = 0 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 2 count of output equations = 0 ==>OE: GND or VCC count of OE equations = 0 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 4 count of output equations = 0 ==>OE: GND or VCC count of OE equations = 0 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 5 count of output equations = 0 ==>OE: GND or VCC count of OE equations = 0 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 6 count of output equations = 0 ==>OE: GND or VCC count of OE equations = 0 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 6 count of output equations = 1 ==>OE: GND or VCC count of OE equations = 1 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 5 count of output equations = 1 ==>OE: GND or VCC count of OE equations = 1 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 16 count of output equations = 1 ==>OE: GND or VCC count of OE equations = 1 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 15 count of output equations = 1 ==>OE: GND or VCC count of OE equations = 1 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 14 count of output equations = 1 ==>OE: GND or VCC count of OE equations = 1 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 13 count of output equations = 1 ==>OE: GND or VCC count of OE equations = 1 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 12 count of output equations = 1 ==>OE: GND or VCC count of OE equations = 1 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 11 count of output equations = 1 ==>OE: GND or VCC count of OE equations = 1 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 10 count of output equations = 1 ==>OE: GND or VCC count of OE equations = 1 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 9 count of output equations = 1 ==>OE: GND or VCC count of OE equations = 1 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 8 count of output equations = 1 ==>OE: GND or VCC count of OE equations = 1 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 7 count of output equations = 1 ==>OE: GND or VCC count of OE equations = 1 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 4 count of output equations = 1 ==>OE: GND or VCC count of OE equations = 1 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 4 count of output equations = 1 ==>OE: GND or VCC count of OE equations = 1 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 3 count of output equations = 1 ==>OE: GND or VCC count of OE equations = 1 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 12 count of output equations = 1 ==>OE: GND or VCC count of OE equations = 1 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 11 count of output equations = 1 ==>OE: GND or VCC count of OE equations = 1 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 10 count of output equations = 1 ==>OE: GND or VCC count of OE equations = 1 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 9 count of output equations = 1 ==>OE: GND or VCC count of OE equations = 1 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 8 count of output equations = 1 ==>OE: GND or VCC count of OE equations = 1 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 7 count of output equations = 1 ==>OE: GND or VCC count of OE equations = 1 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 6 count of output equations = 1 ==>OE: GND or VCC count of OE equations = 1 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 5 count of output equations = 1 ==>OE: GND or VCC count of OE equations = 1 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 4 count of output equations = 1 ==>OE: GND or VCC count of OE equations = 1 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 3 count of output equations = 1 ==>OE: GND or VCC count of OE equations = 1 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 2 count of output equations = 1 ==>OE: GND or VCC count of OE equations = 1 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 6 count of output equations = 1 ==>OE: GND or VCC count of OE equations = 1 PRESET: NONE-COMBINATORIAL RESET : NONE-COMBINATORIAL CLOCK PT : NULL Total unique inputs = 5 count of output equations = 1 ==>OE: GND or VCC count of OE equations = 1 ---------------------------------------------------------------------------- PLD Compiler Software: C37KFIT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 JEDEC ASSEMBLE (17:53:14) Messages: Information: Processing JEDEC for Logic Block 1. Information: Processing JEDEC for Logic Block 2. Information: Processing JEDEC for Logic Block 3. Information: Processing JEDEC for Logic Block 4. Information: Processing JEDEC for Logic Block 5. Information: Processing JEDEC for Logic Block 6. Information: Processing JEDEC for Logic Block 7. Information: Processing JEDEC for Logic Block 8. Information: Processing JEDEC for Logic Block 9. Information: Processing JEDEC for Logic Block 10. Information: Processing JEDEC for Logic Block 11. Information: Processing JEDEC for Logic Block 12. Information: Processing JEDEC for Logic Block 13. Information: Processing JEDEC for Logic Block 14. Information: Processing JEDEC for Logic Block 15. Information: Processing JEDEC for Logic Block 16. Information: JEDEC output file 'pc_remote_sinphase.pin' created. Information: JEDEC output file 'pc_remote_sinphase.jed' created. Summary: Error Count = 0 Warning Count = 0 Completed Successfully at 17:53:17 ---------------------------------------------------------------------------- PLD Compiler Software: C37KFIT.EXE 06/JUN/2000 [v4.02 ] 6.0.1 IR 18 TIMING PATH ANALYSIS (17:53:17) using Package: cy37256p160-125ac Messages: ---------------------------------------------------------------------------- Signal Name | Delay Type | tmax | Path Description ---------------------------------------------------------------------------- reg::(val7_5)id(0)[2] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val7_5 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(phase1_10)id(1)[3] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::phase1_10 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(dac_data_from_pc_1)id(2)[4] inp::ao_from_pc_strobe ---->ao_from_pc_strobe tS 4.0 ns 1 pass inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::dac_data_from_pc_1 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(address_from_pc_0)id(3)[5] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::address_from_pc_0 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(address_from_pc_1)[6] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::address_from_pc_1 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(dac_data_from_pc_12)id(4)[7] inp::ao_from_pc_strobe ---->ao_from_pc_strobe tS 4.0 ns 1 pass inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::dac_data_from_pc_12 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(dac_data_from_pc_5)id(5)[8] inp::ao_from_pc_strobe ---->ao_from_pc_strobe tS 4.0 ns 1 pass inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::dac_data_from_pc_5 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(phase2_5)id(6)[9] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::phase2_5 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val2_5)id(7)[11] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val2_5 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val1_3)id(8)[12] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val1_3 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val0_3)id(9)[13] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val0_3 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(phase1_5)id(10)[14] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::phase1_5 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(phase2_3)id(11)[15] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::phase2_3 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val0_4)id(12)[16] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val0_4 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val1_1)[17] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val1_1 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val2_0)[18] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val2_0 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val6_3)id(15)[23] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val6_3 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val5_1)[24] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val5_1 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val4_1)[25] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val4_1 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(phase1_3)[26] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::phase1_3 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val3_3)[27] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val3_3 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val4_3)[28] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val4_3 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val5_0)[29] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val5_0 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val5_5)[30] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val5_5 tCO 6.5 ns ---------------------------------------------------------------------------- cmb::dio_tristate[32] ---------------------------------------------------------------------------- reg::(\dacwr:timeout_1\)[33] inp::\dacwr:timeout_0\.Q ---->\dacwr:cmp_vv_us_MODGEN_10\ tSCS 14.0 ns 2 passes out::\dacwr:timeout_1\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\dacwr:timeout_2\)[34] inp::\dacwr:timeout_0\.Q ---->\dacwr:cmp_vv_us_MODGEN_10\ tSCS 14.0 ns 2 passes out::\dacwr:timeout_2\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\dacwr:dac_stateSBV_1\)[35] inp::\dacwr:dac_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::\dacwr:dac_stateSBV_1\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::(to_dac_from_pc_ack)[36] inp::\dacwr:dac_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::to_dac_from_pc_ack tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\spg:sample_0\)[45] inp::\spg:current_count_0\.Q ---->\spg:MODULE_3:g1:a0:gx:u0:eq_5\ ---->\spg:MODULE_3:g1:a0:gx:u0:geq(0):c3:u1\ ---->\spg:cmp_vv_us_MODGEN_3\ tSCS 30.0 ns 4 passes out::\spg:sample_0\ tCOpt 13.5 ns 1 pass ---------------------------------------------------------------------------- reg::(phase1_12)[46] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::phase1_12 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(phase1_7)[51] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::phase1_7 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(dac_data_from_pc_2)[52] inp::ao_from_pc_strobe ---->ao_from_pc_strobe tS 4.0 ns 1 pass inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::dac_data_from_pc_2 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\rio:il_read_stateSBV_1\)ao_from_pc_strobe[53] inp::ao_from_pc_strobe ---->ao_from_pc_strobe tS 4.0 ns 1 pass inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::\rio:il_read_stateSBV_1\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::ao_from_pc_ack[54] inp::\rio:il_read_stateSBV_1\.Q tSCS 8.0 ns 1 pass out::ao_from_pc_ack tCO 6.5 ns inp::this_chip_selected.Q tER 16.5 ns 1 pass ---------------------------------------------------------------------------- reg::(\rio:il_read_stateSBV_0\)[55] inp::ao_from_pc_strobe ---->ao_from_pc_strobe tS 4.0 ns 1 pass inp::\rio:il_read_stateSBV_1\.Q tSCS 8.0 ns 1 pass out::\rio:il_read_stateSBV_0\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::(dac_data_from_pc_10)[56] inp::ao_from_pc_strobe ---->ao_from_pc_strobe tS 4.0 ns 1 pass inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::dac_data_from_pc_10 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(dac_data_from_pc_15)[57] inp::ao_from_pc_strobe ---->ao_from_pc_strobe tS 4.0 ns 1 pass inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::dac_data_from_pc_15 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(dac_data_from_pc_9)[58] inp::ao_from_pc_strobe ---->ao_from_pc_strobe tS 4.0 ns 1 pass inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::dac_data_from_pc_9 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\dacwr:dac_hold_2\)[63] inp::\dacwr:timeout_0\.Q ---->\dacwr:cmp_vv_us_MODGEN_10\ tSCS 14.0 ns 2 passes out::\dacwr:dac_hold_2\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val2_2)[64] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val2_2 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(shift_2)[65] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::shift_2 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(phase1_2)[66] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::phase1_2 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(phase1_9)[67] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::phase1_9 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(steplen_2)[68] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::steplen_2 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val1_2)[69] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val1_2 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val5_2)[70] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val5_2 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\spg:kick_dac\)[72] inp::\spg:current_count_0\.Q ---->\spg:MODULE_3:g1:a0:gx:u0:eq_5\ ---->\spg:MODULE_3:g1:a0:gx:u0:geq(0):c3:u1\ ---->\spg:cmp_vv_us_MODGEN_3\ tSCS 30.0 ns 4 passes out::\spg:kick_dac\ tCOpt 13.5 ns 1 pass ---------------------------------------------------------------------------- reg::(\spg:current_count_0\)[73] inp::\spg:current_count_0\.Q ---->\spg:MODULE_3:g1:a0:gx:u0:eq_5\ ---->\spg:MODULE_3:g1:a0:gx:u0:geq(0):c3:u1\ ---->\spg:cmp_vv_us_MODGEN_3\ tSCS 30.0 ns 4 passes out::\spg:current_count_0\ tCOpt 13.5 ns 1 pass ---------------------------------------------------------------------------- reg::(\spg:current_count_7\)[74] inp::\spg:current_count_0\.Q ---->\spg:MODULE_3:g1:a0:gx:u0:eq_5\ ---->\spg:MODULE_3:g1:a0:gx:u0:geq(0):c3:u1\ ---->\spg:cmp_vv_us_MODGEN_3\ tSCS 26.0 ns 4 passes out::\spg:current_count_7\ tCOpt 13.5 ns 1 pass ---------------------------------------------------------------------------- reg::(\spg:current_count_5\)[75] inp::\spg:current_count_0\.Q ---->\spg:MODULE_3:g1:a0:gx:u0:eq_5\ ---->\spg:MODULE_3:g1:a0:gx:u0:geq(0):c3:u1\ ---->\spg:cmp_vv_us_MODGEN_3\ tSCS 26.0 ns 4 passes out::\spg:current_count_5\ tCOpt 13.5 ns 1 pass ---------------------------------------------------------------------------- reg::(\spg:current_count_3\)[76] inp::\spg:current_count_0\.Q ---->\spg:MODULE_3:g1:a0:gx:u0:eq_5\ ---->\spg:MODULE_3:g1:a0:gx:u0:geq(0):c3:u1\ ---->\spg:cmp_vv_us_MODGEN_3\ tSCS 26.0 ns 4 passes out::\spg:current_count_3\ tCOpt 13.5 ns 1 pass ---------------------------------------------------------------------------- reg::(\spg:current_count_1\)[77] inp::\spg:current_count_0\.Q ---->\spg:MODULE_3:g1:a0:gx:u0:eq_5\ ---->\spg:MODULE_3:g1:a0:gx:u0:geq(0):c3:u1\ ---->\spg:cmp_vv_us_MODGEN_3\ tSCS 30.0 ns 4 passes out::\spg:current_count_1\ tCOpt 13.5 ns 1 pass ---------------------------------------------------------------------------- reg::(\spg:current_count_9\)[78] inp::\spg:current_count_0\.Q ---->\spg:MODULE_3:g1:a0:gx:u0:eq_5\ ---->\spg:MODULE_3:g1:a0:gx:u0:geq(0):c3:u1\ ---->\spg:cmp_vv_us_MODGEN_3\ tSCS 26.0 ns 4 passes out::\spg:current_count_9\ tCOpt 13.5 ns 1 pass ---------------------------------------------------------------------------- reg::sinphase_zeros[79] inp::\spg:current_count_0\.Q ---->\spg:MODULE_3:g1:a0:gx:u0:eq_5\ ---->\spg:MODULE_3:g1:a0:gx:u0:geq(0):c3:u1\ ---->\spg:cmp_vv_us_MODGEN_3\ ---->S_2 tSCS 36.0 ns 5 passes out::sinphase_zeros tCOpt 13.5 ns 1 pass ---------------------------------------------------------------------------- reg::dad(0)[82] inp::\dacwr:dac_hold_0\.Q tSCS 8.0 ns 1 pass out::dad(0) tCO 6.5 ns ---------------------------------------------------------------------------- reg::dad(1)[83] inp::\dacwr:dac_hold_1\.Q tSCS 8.0 ns 1 pass out::dad(1) tCO 6.5 ns ---------------------------------------------------------------------------- reg::dad(2)[84] inp::\dacwr:dac_hold_2\.Q tSCS 8.0 ns 1 pass out::dad(2) tCO 6.5 ns ---------------------------------------------------------------------------- reg::dad(3)[85] inp::\dacwr:dac_hold_3\.Q tSCS 8.0 ns 1 pass out::dad(3) tCO 6.5 ns ---------------------------------------------------------------------------- reg::dad(4)[86] inp::\dacwr:dac_hold_4\.Q tSCS 8.0 ns 1 pass out::dad(4) tCO 6.5 ns ---------------------------------------------------------------------------- reg::dad(5)[87] inp::\dacwr:dac_hold_5\.Q tSCS 8.0 ns 1 pass out::dad(5) tCO 6.5 ns ---------------------------------------------------------------------------- reg::dad(6)[88] inp::\dacwr:dac_hold_6\.Q tSCS 8.0 ns 1 pass out::dad(6) tCO 6.5 ns ---------------------------------------------------------------------------- reg::dad(7)[89] inp::\dacwr:dac_hold_7\.Q tSCS 8.0 ns 1 pass out::dad(7) tCO 6.5 ns ---------------------------------------------------------------------------- reg::dad(8)[91] inp::\dacwr:dac_hold_8\.Q tSCS 8.0 ns 1 pass out::dad(8) tCO 6.5 ns ---------------------------------------------------------------------------- reg::dad(9)[92] inp::\dacwr:dac_hold_9\.Q tSCS 8.0 ns 1 pass out::dad(9) tCO 6.5 ns ---------------------------------------------------------------------------- reg::dad(10)[93] inp::\dacwr:dac_hold_10\.Q tSCS 8.0 ns 1 pass out::dad(10) tCO 6.5 ns ---------------------------------------------------------------------------- reg::dad(11)[94] inp::\dacwr:dac_hold_11\.Q tSCS 8.0 ns 1 pass out::dad(11) tCO 6.5 ns ---------------------------------------------------------------------------- reg::dad(12)[95] inp::\dacwr:dac_hold_12\.Q tSCS 8.0 ns 1 pass out::dad(12) tCO 6.5 ns ---------------------------------------------------------------------------- reg::daaddr(0)[96] inp::\dacwr:dac_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::daaddr(0) tCO 6.5 ns ---------------------------------------------------------------------------- reg::daaddr(1)[97] inp::\dacwr:dac_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::da_not_ldab tCO 12.5 ns 1 pass ---------------------------------------------------------------------------- reg::daaddr(2)[98] inp::\dacwr:dac_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::da_not_ldab tCO 12.5 ns 1 pass ---------------------------------------------------------------------------- reg::da_not_wr[103] inp::\dacwr:dac_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::da_not_wr tCO 6.5 ns ---------------------------------------------------------------------------- reg::da_not_cs[104] inp::reset tRO 13.5 ns 1 pass out::da_not_cs tCO 6.5 ns ---------------------------------------------------------------------------- cmb::da_not_ldcd[105] inp::daaddr(1).Q tCO 12.5 ns 1 pass ---------------------------------------------------------------------------- cmb::da_not_ldab[106] inp::daaddr(1).Q tCO 12.5 ns 1 pass ---------------------------------------------------------------------------- cmb::da_not_ldef[107] inp::daaddr(1).Q tCO 12.5 ns 1 pass ---------------------------------------------------------------------------- cmb::da_not_ldgh[108] inp::daaddr(1).Q tCO 12.5 ns 1 pass ---------------------------------------------------------------------------- reg::da_not_clr[112] inp::reset tRO 13.5 ns 1 pass out::da_not_clr tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val7_0)[113] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val7_0 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val3_0)[114] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val3_0 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val0_0)[115] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val0_0 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(phase2_0)[116] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::phase2_0 tCO 6.5 ns ---------------------------------------------------------------------------- cmb::shdn(0)[117] ---------------------------------------------------------------------------- cmb::shdn(1)[118] ---------------------------------------------------------------------------- cmb::shdn(2)[119] ---------------------------------------------------------------------------- reg::(\dacwr:dac_hold_7\)[122] inp::\dacwr:timeout_0\.Q ---->\dacwr:cmp_vv_us_MODGEN_10\ tSCS 14.0 ns 2 passes out::\dacwr:dac_hold_7\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val4_7)[123] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val4_7 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(steplen_7)[124] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::steplen_7 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(phase1_1)[125] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::phase1_1 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(phase1_11)[126] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::phase1_11 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val0_7)[127] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val0_7 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val3_7)[128] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val3_7 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val7_1)[129] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val7_1 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\dacwr:dac_hold_6\)[131] inp::\dacwr:timeout_0\.Q ---->\dacwr:cmp_vv_us_MODGEN_10\ tSCS 14.0 ns 2 passes out::\dacwr:dac_hold_6\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val2_6)[132] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val2_6 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(sp_req)[133] inp::\spg:kdacSBV_0\.Q tSCS 8.0 ns 1 pass out::sp_req tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\spg:kdacSBV_0\)[134] inp::sp_ack.Q tSCS 8.0 ns 1 pass out::\spg:kdacSBV_0\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::(phase1_6)[135] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::phase1_6 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(steplen_6)[136] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::steplen_6 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val1_6)[137] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val1_6 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val5_6)[138] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val5_6 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\spg:current_phase_7\)[144] inp::\spg:current_count_0\.Q ---->\spg:MODULE_3:g1:a0:gx:u0:eq_5\ ---->\spg:MODULE_3:g1:a0:gx:u0:geq(0):c3:u1\ ---->\spg:cmp_vv_us_MODGEN_3\ tSCS 26.0 ns 4 passes out::\spg:current_phase_7\ tCOpt 13.5 ns 1 pass ---------------------------------------------------------------------------- reg::(\spg:current_phase_2\)[145] inp::\spg:current_count_0\.Q ---->\spg:MODULE_3:g1:a0:gx:u0:eq_5\ ---->\spg:MODULE_3:g1:a0:gx:u0:geq(0):c3:u1\ ---->\spg:cmp_vv_us_MODGEN_3\ tSCS 26.0 ns 4 passes out::\spg:current_phase_2\ tCOpt 13.5 ns 1 pass ---------------------------------------------------------------------------- reg::(\spg:current_phase_10\)[146] inp::\spg:current_count_0\.Q ---->\spg:MODULE_3:g1:a0:gx:u0:eq_5\ ---->\spg:MODULE_3:g1:a0:gx:u0:geq(0):c3:u1\ ---->\spg:cmp_vv_us_MODGEN_3\ tSCS 26.0 ns 4 passes out::\spg:current_phase_10\ tCOpt 13.5 ns 1 pass ---------------------------------------------------------------------------- reg::(\spg:current_phase_11\)[147] inp::\spg:current_count_0\.Q ---->\spg:MODULE_3:g1:a0:gx:u0:eq_5\ ---->\spg:MODULE_3:g1:a0:gx:u0:geq(0):c3:u1\ ---->\spg:cmp_vv_us_MODGEN_3\ tSCS 26.0 ns 4 passes out::\spg:current_phase_11\ tCOpt 13.5 ns 1 pass ---------------------------------------------------------------------------- reg::(\spg:current_phase_3\)[148] inp::\spg:current_count_0\.Q ---->\spg:MODULE_3:g1:a0:gx:u0:eq_5\ ---->\spg:MODULE_3:g1:a0:gx:u0:geq(0):c3:u1\ ---->\spg:cmp_vv_us_MODGEN_3\ tSCS 26.0 ns 4 passes out::\spg:current_phase_3\ tCOpt 13.5 ns 1 pass ---------------------------------------------------------------------------- reg::(\spg:current_phase_6\)[149] inp::\spg:current_count_0\.Q ---->\spg:MODULE_3:g1:a0:gx:u0:eq_5\ ---->\spg:MODULE_3:g1:a0:gx:u0:geq(0):c3:u1\ ---->\spg:cmp_vv_us_MODGEN_3\ tSCS 26.0 ns 4 passes out::\spg:current_phase_6\ tCOpt 13.5 ns 1 pass ---------------------------------------------------------------------------- reg::(\spg:current_phase_0\)[150] inp::\spg:current_count_0\.Q ---->\spg:MODULE_3:g1:a0:gx:u0:eq_5\ ---->\spg:MODULE_3:g1:a0:gx:u0:geq(0):c3:u1\ ---->\spg:cmp_vv_us_MODGEN_3\ tSCS 30.0 ns 4 passes out::\spg:current_phase_0\ tCOpt 13.5 ns 1 pass ---------------------------------------------------------------------------- reg::(shift_1)[153] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::shift_1 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(phase2_1)[154] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::phase2_1 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\spg:precount_1\)[155] inp::\spg:precount_0\.Q ---->\spg:cmp_vv_us_MODGEN_1\ tSCS 14.0 ns 2 passes out::\spg:precount_1\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\spg:precount_2\)[156] inp::\spg:precount_0\.Q ---->\spg:cmp_vv_us_MODGEN_1\ tSCS 14.0 ns 2 passes out::\spg:precount_2\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::(predev_0)[157] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::predev_0 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(shift_0)[158] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::shift_0 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val3_1)[159] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val3_1 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\spg:current_phase_9\)[887] inp::\spg:current_count_0\.Q ---->\spg:MODULE_3:g1:a0:gx:u0:eq_5\ ---->\spg:MODULE_3:g1:a0:gx:u0:geq(0):c3:u1\ ---->\spg:cmp_vv_us_MODGEN_3\ tSCS 26.0 ns 4 passes out::\spg:current_phase_9\ tCOpt 13.5 ns 1 pass ---------------------------------------------------------------------------- reg::(\spg:current_phase_4\)[889] inp::\spg:current_count_0\.Q ---->\spg:MODULE_3:g1:a0:gx:u0:eq_5\ ---->\spg:MODULE_3:g1:a0:gx:u0:geq(0):c3:u1\ ---->\spg:cmp_vv_us_MODGEN_3\ tSCS 26.0 ns 4 passes out::\spg:current_phase_4\ tCOpt 13.5 ns 1 pass ---------------------------------------------------------------------------- reg::(\spg:current_phase_12\)[891] inp::\spg:current_count_0\.Q ---->\spg:MODULE_3:g1:a0:gx:u0:eq_5\ ---->\spg:MODULE_3:g1:a0:gx:u0:geq(0):c3:u1\ ---->\spg:cmp_vv_us_MODGEN_3\ tSCS 26.0 ns 4 passes out::\spg:current_phase_12\ tCOpt 13.5 ns 1 pass ---------------------------------------------------------------------------- reg::(\spg:current_phase_1\)[895] inp::\spg:current_count_0\.Q ---->\spg:MODULE_3:g1:a0:gx:u0:eq_5\ ---->\spg:MODULE_3:g1:a0:gx:u0:geq(0):c3:u1\ ---->\spg:cmp_vv_us_MODGEN_3\ tSCS 30.0 ns 4 passes out::\spg:current_phase_1\ tCOpt 13.5 ns 1 pass ---------------------------------------------------------------------------- reg::(\spg:current_phase_5\)[897] inp::\spg:current_count_0\.Q ---->\spg:MODULE_3:g1:a0:gx:u0:eq_5\ ---->\spg:MODULE_3:g1:a0:gx:u0:geq(0):c3:u1\ ---->\spg:cmp_vv_us_MODGEN_3\ tSCS 26.0 ns 4 passes out::\spg:current_phase_5\ tCOpt 13.5 ns 1 pass ---------------------------------------------------------------------------- reg::(\spg:current_phase_8\)[899] inp::\spg:current_count_0\.Q ---->\spg:MODULE_3:g1:a0:gx:u0:eq_5\ ---->\spg:MODULE_3:g1:a0:gx:u0:geq(0):c3:u1\ ---->\spg:cmp_vv_us_MODGEN_3\ tSCS 26.0 ns 4 passes out::\spg:current_phase_8\ tCOpt 13.5 ns 1 pass ---------------------------------------------------------------------------- reg::(steplen_3)[903] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::steplen_3 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(predev_1)[905] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::predev_1 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\spg:precount_3\)[907] inp::\spg:precount_0\.Q ---->\spg:cmp_vv_us_MODGEN_1\ tSCS 14.0 ns 2 passes out::\spg:precount_3\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val7_3)[909] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val7_3 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(phase1_0)[911] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::phase1_0 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(predev_3)[913] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::predev_3 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(steplen_0)[915] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::steplen_0 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\dacwr:dac_hold_10\)[917] inp::\dacwr:timeout_0\.Q ---->\dacwr:cmp_vv_us_MODGEN_10\ tSCS 14.0 ns 2 passes out::\dacwr:dac_hold_10\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::(phase2_2)[919] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::phase2_2 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(dac_data_from_pc_3)[921] inp::ao_from_pc_strobe ---->ao_from_pc_strobe tS 4.0 ns 1 pass inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::dac_data_from_pc_3 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(address_from_pc_3)[923] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::address_from_pc_3 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(steplen_5)[925] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::steplen_5 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(dac_data_from_pc_0)[927] inp::ao_from_pc_strobe ---->ao_from_pc_strobe tS 4.0 ns 1 pass inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::dac_data_from_pc_0 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(dac_data_from_pc_4)[929] inp::ao_from_pc_strobe ---->ao_from_pc_strobe tS 4.0 ns 1 pass inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::dac_data_from_pc_4 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(phase2_10)[931] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::phase2_10 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val6_5)[933] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val6_5 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val1_5)[935] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val1_5 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val0_5)[937] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val0_5 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(steplen_4)[939] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::steplen_4 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val2_1)[941] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val2_1 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val0_1)[943] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val0_1 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val1_0)[945] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val1_0 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val1_4)[947] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val1_4 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val2_3)[949] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val2_3 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val5_4)[951] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val5_4 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val4_4)[953] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val4_4 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val3_5)[955] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val3_5 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val6_0)[957] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val6_0 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val4_0)[959] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val4_0 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val4_5)[961] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val4_5 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val5_3)[963] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val5_3 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val6_1)[965] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val6_1 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\dacwr:timeout_0\)[969] inp::\dacwr:timeout_0\.Q ---->\dacwr:cmp_vv_us_MODGEN_10\ tSCS 14.0 ns 2 passes out::\dacwr:timeout_0\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\dacwr:dac_stateSBV_0\)[971] inp::\dacwr:dac_stateSBV_1\.Q tSCS 8.0 ns 1 pass out::\dacwr:dac_stateSBV_0\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\dacwr:dac_stateSBV_2\)[973] inp::\dacwr:timeout_0\.Q ---->\dacwr:cmp_vv_us_MODGEN_10\ tSCS 14.0 ns 2 passes out::\dacwr:dac_stateSBV_2\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::(sp_ack)[975] inp::\dacwr:dac_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::sp_ack tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\dacwr:dac_hold_4\)[977] inp::\dacwr:timeout_0\.Q ---->\dacwr:cmp_vv_us_MODGEN_10\ tSCS 14.0 ns 2 passes out::\dacwr:dac_hold_4\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\dacwr:dac_hold_3\)[981] inp::\dacwr:timeout_0\.Q ---->\dacwr:cmp_vv_us_MODGEN_10\ tSCS 14.0 ns 2 passes out::\dacwr:dac_hold_3\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::(phase2_12)[989] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::phase2_12 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(dac_data_from_pc_8)[999] inp::ao_from_pc_strobe ---->ao_from_pc_strobe tS 4.0 ns 1 pass inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::dac_data_from_pc_8 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(this_chip_selected)[1001] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass inp::reset tRO 13.5 ns 1 pass out::this_chip_selected tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\rio:il_read_stateSBV_2\)[1003] inp::ao_from_pc_strobe ---->ao_from_pc_strobe tS 4.0 ns 1 pass inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::\rio:il_read_stateSBV_2\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\rio:this_is_a_ctrl_transaction\)[1005] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass inp::reset tRO 13.5 ns 1 pass out::\rio:this_is_a_ctrl_transaction\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::(address_from_pc_2)[1007] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::address_from_pc_2 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(dac_data_from_pc_11)[1009] inp::ao_from_pc_strobe ---->ao_from_pc_strobe tS 4.0 ns 1 pass inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::dac_data_from_pc_11 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(dac_data_from_pc_7)[1011] inp::ao_from_pc_strobe ---->ao_from_pc_strobe tS 4.0 ns 1 pass inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::dac_data_from_pc_7 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(phase1_8)[1013] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::phase1_8 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val4_2)[1015] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val4_2 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(steplen_9)[1017] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::steplen_9 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(phase2_9)[1019] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::phase2_9 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val6_2)[1021] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val6_2 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(predev_2)[1023] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::predev_2 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val0_2)[1025] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val0_2 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val3_2)[1027] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val3_2 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val7_2)[1029] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val7_2 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\spg:current_count_6\)[1035] inp::\spg:current_count_0\.Q ---->\spg:MODULE_3:g1:a0:gx:u0:eq_5\ ---->\spg:MODULE_3:g1:a0:gx:u0:geq(0):c3:u1\ ---->\spg:cmp_vv_us_MODGEN_3\ tSCS 26.0 ns 4 passes out::\spg:current_count_6\ tCOpt 13.5 ns 1 pass ---------------------------------------------------------------------------- reg::(\spg:current_count_4\)[1037] inp::\spg:current_count_0\.Q ---->\spg:MODULE_3:g1:a0:gx:u0:eq_5\ ---->\spg:MODULE_3:g1:a0:gx:u0:geq(0):c3:u1\ ---->\spg:cmp_vv_us_MODGEN_3\ tSCS 26.0 ns 4 passes out::\spg:current_count_4\ tCOpt 13.5 ns 1 pass ---------------------------------------------------------------------------- reg::(\spg:current_count_2\)[1039] inp::\spg:current_count_0\.Q ---->\spg:MODULE_3:g1:a0:gx:u0:eq_5\ ---->\spg:MODULE_3:g1:a0:gx:u0:geq(0):c3:u1\ ---->\spg:cmp_vv_us_MODGEN_3\ tSCS 26.0 ns 4 passes out::\spg:current_count_2\ tCOpt 13.5 ns 1 pass ---------------------------------------------------------------------------- reg::(\spg:current_count_8\)[1043] inp::\spg:current_count_0\.Q ---->\spg:MODULE_3:g1:a0:gx:u0:eq_5\ ---->\spg:MODULE_3:g1:a0:gx:u0:geq(0):c3:u1\ ---->\spg:cmp_vv_us_MODGEN_3\ tSCS 26.0 ns 4 passes out::\spg:current_count_8\ tCOpt 13.5 ns 1 pass ---------------------------------------------------------------------------- reg::(\spg:iclk\)[1049] inp::\spg:precount_0\.Q ---->\spg:cmp_vv_us_MODGEN_1\ tSCS 14.0 ns 2 passes out::\spg:iclk\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\dacwr:dac_hold_1\)[1061] inp::\dacwr:timeout_0\.Q ---->\dacwr:cmp_vv_us_MODGEN_10\ tSCS 14.0 ns 2 passes out::\dacwr:dac_hold_1\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\dacwr:dac_hold_12\)[1065] inp::\dacwr:timeout_0\.Q ---->\dacwr:cmp_vv_us_MODGEN_10\ tSCS 14.0 ns 2 passes out::\dacwr:dac_hold_12\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\dacwr:dac_hold_11\)[1067] inp::\dacwr:timeout_0\.Q ---->\dacwr:cmp_vv_us_MODGEN_10\ tSCS 14.0 ns 2 passes out::\dacwr:dac_hold_11\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\dacwr:dac_hold_9\)[1069] inp::\dacwr:timeout_0\.Q ---->\dacwr:cmp_vv_us_MODGEN_10\ tSCS 14.0 ns 2 passes out::\dacwr:dac_hold_9\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::(dac_data_from_pc_6)[1071] inp::ao_from_pc_strobe ---->ao_from_pc_strobe tS 4.0 ns 1 pass inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::dac_data_from_pc_6 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(phase2_11)[1073] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::phase2_11 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\spg:sample_2\)[1079] inp::\spg:current_count_0\.Q ---->\spg:MODULE_3:g1:a0:gx:u0:eq_5\ ---->\spg:MODULE_3:g1:a0:gx:u0:geq(0):c3:u1\ ---->\spg:cmp_vv_us_MODGEN_3\ tSCS 26.0 ns 4 passes out::\spg:sample_2\ tCOpt 13.5 ns 1 pass ---------------------------------------------------------------------------- reg::(\spg:sample_1\)[1085] inp::\spg:current_count_0\.Q ---->\spg:MODULE_3:g1:a0:gx:u0:eq_5\ ---->\spg:MODULE_3:g1:a0:gx:u0:geq(0):c3:u1\ ---->\spg:cmp_vv_us_MODGEN_3\ tSCS 26.0 ns 4 passes out::\spg:sample_1\ tCOpt 13.5 ns 1 pass ---------------------------------------------------------------------------- reg::(\dacwr:dac_hold_5\)[1087] inp::\dacwr:timeout_0\.Q ---->\dacwr:cmp_vv_us_MODGEN_10\ tSCS 14.0 ns 2 passes out::\dacwr:dac_hold_5\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::(to_dac_from_pc_req)[1089] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::to_dac_from_pc_req tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val7_4)[1095] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val7_4 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val3_4)[1097] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val3_4 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val2_4)[1099] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val2_4 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(phase2_4)[1101] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::phase2_4 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\dacwr:dac_hold_0\)[1103] inp::\dacwr:timeout_0\.Q ---->\dacwr:cmp_vv_us_MODGEN_10\ tSCS 14.0 ns 2 passes out::\dacwr:dac_hold_0\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::(phase1_4)[1105] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::phase1_4 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val6_4)[1107] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val6_4 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\spg:precount_0\)[1109] inp::\spg:precount_0\.Q ---->\spg:cmp_vv_us_MODGEN_1\ tSCS 14.0 ns 2 passes out::\spg:precount_0\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val6_7)[1111] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val6_7 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val1_7)[1113] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val1_7 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(phase2_7)[1115] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::phase2_7 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val7_7)[1117] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val7_7 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(steplen_1)[1119] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::steplen_1 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val2_7)[1121] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val2_7 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val5_7)[1123] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val5_7 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(\dacwr:dac_hold_8\)[1125] inp::\dacwr:timeout_0\.Q ---->\dacwr:cmp_vv_us_MODGEN_10\ tSCS 14.0 ns 2 passes out::\dacwr:dac_hold_8\ tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val4_6)[1127] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val4_6 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(steplen_8)[1129] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::steplen_8 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(phase2_6)[1131] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::phase2_6 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val6_6)[1133] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val6_6 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(phase2_8)[1135] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::phase2_8 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val0_6)[1137] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val0_6 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val3_6)[1139] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val3_6 tCO 6.5 ns ---------------------------------------------------------------------------- reg::(val7_6)[1141] inp::\rio:il_read_stateSBV_0\.Q tSCS 8.0 ns 1 pass out::val7_6 tCO 6.5 ns ---------------------------------------------------------------------------- Worst Case Path Summary ----------------------- tS = 4.0 ns for dac_data_from_pc_1.T tSCS = 36.0 ns for sinphase_zeros.D tCO = 13.5 ns for \spg:sample_0\.C tRO = 13.5 ns for da_not_cs.AR tER = 16.5 ns for ao_from_pc_ack.OE Summary: Error Count = 0 Warning Count = 0 Completed Successfully