H85 AO MFB CPLDs Mike Thompson 8/4/03 ------------------------------------------------------------------------------ This file contains information on some of the MFB board's CPLD images that are being used in H85's development. All of the CPLD images, and their supporting files, are stored on duke.ifa.hawaii.edu. As of the ADLINK lab work in the week of 7/7/03 some of these images were changed/updated. Previously the images had not changed in quite a while and this configuration is referred to as the (venerable) "Old Configuration". This file provides pointers to the directories and files that are associated with the Old Configuration and the new configuration (Adlink). TO RETURN TO THE OLD CONFIGURATION, THE PC MFB DIO CPLD AND COUNTER/HVA MFB PC_REMOTE_BUS CPLDs NEED TO BE REPROGRAMMED BACK TO THE OLD IMAGES. To do this you'll need the AO_LAPTOP which Mike Thompson is currently using to run the Cypress ISR Programming Software and the ISR cable. The ISR cable plugs into the parallel (printer) port and into a CPLD's JTAG port. There's a root directory for all of the changes we've made for the ADLINK DIO card. Eventually the finalized and verified versions of these files will be moved to the design directory. Anyway, the working code is in: /shared_ifa/AO/H85_project/Electronics/Hardware/Adlink cable converter/Adlink testing NOTE: TO SEE THE CPLD's CHECKSUMS LOOK AT THE VERY END OF THE JEDEC (.jed) FILE in the folder that contains the VHDL code. ================= == PC MFB == ================= There are 2 MFB boards to consider in this discussion. First is the PC MFB, also called pc_local, which is the MFB mounted on the back of the HVA chassis with a connection to the H85 RT server via the DIO cable. The PC MFB has 2 CPLDs to consider, the FiberBus and DIO CPLDs. The DIO CPLD controls handshaking with the RT server's DIO card. The DIO CPLD was changed to implement the ADLINK DIO Card's (blessedly sane) handshaking protocol. The FiberBus CPLD was not changed. ---------------------------------- OLD CONFIGURATION PC MFB DIO CPLD ---------------------------------- This is for use with the National Instruments DIO Card's "handshaking" "protocol" (a generous appellation). /shared_ifa/AO/Electronics/arc_2001_1_17/vhdl/interface/interface/pc-direct/dio/dio.jed Note: Fuse Checksum = C0650 ---------------------------------------- New Configuration ADLINK PC MFB DIO CPLD ---------------------------------------- FOLDER: pc_local_dio_adlink This CPLD is for use with the ADLINK DIO card. Just the handshaking to the ADLINK card has been changed. /shared_ifa/AO/H85_project/Electronics/Hardware/Adlink cable converter/Adlink testing/pc_local_dio_adlink/adlink_dio/dio.jed Note: Fuse Checksum = CF90B --------------------------------------- OLD CONFIGURATION PC MFB Fiber Bus CPLD --------------------------------------- This is the code for the Fiber Bus CPLD in the old and new configuration, as it was not changed. /shared_ifa/AO/Electronics/arc_2001_1_17/vhdl/interface/interface/pc-local/fiber_v5.jed Note: Fuse Checksum = CE20E ============================================================== == Remote MFBs == ============================================================== The Remote MFBs in the Counter and HVA Chassis are supposed to be identical. This hasn't always been the case during development. As of 8/12/03 both MFBs are running the same CPLD code, but with the Dipswitch switch 8 set differently. There is some legacy information for MFB CPLD code below in which the CPLD images differed under the sections Counter MFB and HVA MFB. -------------------------------------------------------- New CONFIGURATION ADLINK REMOTE MFB pc_remote_Bus CPLD RESET -------------------------------------------------------- FOLDER: pc_remote_bus_rev2.1_reset Previously almost no signals were reset during power up reset. Here I've added all signals to the reset of all sequential logic. That includes all entity outputs and internal signals, especially state registers. \\Duke\shared_ifa\AO\H85_project\Electronics\Hardware\pc_remote_bus_rev2.1_reset Note: Fuse Checksum = C428E -------------------------------------------------------- New CONFIGURATION ADLINK REMOTE MFB pc_remote_Bus CPLD -------------------------------------------------------- FOLDER: pc_remote_bus_rev2.0_hva_diff This version, rev2.0, of the pc_remote_bus CPLD implemented a couple things. The most significant new feature is that it differentiates between MFB implementation in an HVA and Counter Chassis. This was done because the previous versions of the code still executed backplane reads of counts. These reads clashed with HVA corrections that the CPLD writes to the HVA boards in an HVA Chassis implementation. So a signal, hva_chassis_en_l, from the MFB's DIP Switch, position 8, was added to the CPLD on pin 55. When the switch is ON (logic 0) backplane reads are disabled. When the switch is OFF (logic 1) backplane reads are not disabled. This maintains the current default values of the Counter MFB's dipswitch settings (all OFF). Also this version cleaned up the quick fix revision (pc_remote_dio_adlink) we (peter onaka, mike thompson, jim wright, mark chun) did in the lab to remove the delays associated with the National Instruments' DIO card. \\Duke\shared_ifa\AO\H85_project\Electronics\Hardware\pc_remote_bus_rev2.0_hva_diff Note: Fuse Checksum = CC881 -------------------------------------------------------- OLD CONFIGURATION NI REMOTE MFB pc_remote_Bus CPLD -------------------------------------------------------- FOLDER: Mutifunction board bus Rob This CPLD is outdated and has been replaced with pc_remote_dio_adlink. This CPLD is for use with the National Instruments DIO card. After every 4th word a 5.25us delay is inserted. The same image was run on both the HVA and Counter MFB. Though it never really worked right in the HVA MFB. /shared_ifa/AO/H85_project/Electronics/Hardware/Mutifunction board bus Rob/pc_remote_bus_every4_525us.jed Note: Fuse Checksum = C8EE3 ====================== == Counter MFB == ====================== The second board to consider is the Counter Chassis' MFB, also referred to as pc_remote. This board has several CPLDs. The one we changed was pc_remote_bus. This CPLD originally contained 5.25us delays every 4th word sent towards the PC MFB to compensate for NI DIO Card limitations. We reduced this delay to 0 for working with the ADLINK DIO card. --------------------------------------------------------- New Configuration ADLINK Counter MFB pc_remote_bus CPLD --------------------------------------------------------- FOLDER: pc_remote_dio_adlink This image is outdated and has been replaced with pc_remote_bus_rev2.0_hva_diff. This CPLD is for use with the ADLINK DIO card. The 5.25us delays were reduced to 0.0us in the Counter MFB. This version was a quick fix and has been replaced by pc_remote_bus_rev2.0_hva_diff. /shared_ifa/AO/H85_project/Electronics/Hardware/Adlink cable converter/Adlink testing/pc_remote_dio_adlink/pc_remote_bus.jed Note: Fuse Checksum = C8E71 ====================== == HVA MFB == ====================== ---------------------------------------------------------------------- New Configuration ADLINK HVA MFB pc_remote_bus CPLD No Backplane Reads ---------------------------------------------------------------------- FOLDER: pc_remote_dio_adlink_No_BP_Reads This image is outdated and has been replaced with pc_remote_bus_rev2.0_hva_diff. In the lab using the Old Configuration's pc_remote_bus CPLD we had bus clash issues on the backplane address lines in the HVA chassis. Counter reads were clashing with corrections being written by software. Since there's no need for counter read functionality in the HVA chassis, the reads were disabled in the state machine. This VHDL code was sourced from the New Configuration ADLINK Counter MFB DIO CPLD pc_remote_bus. /shared_ifa/AO/H85_project/Electronics/Hardware/Adlink cable converter/Adlink testing/pc_remote_dio_adlink_No_BP_Reads/pc_remote_bus.jed Note: Fuse Checksum = C6139