pc_remote_bus rev 2.1

This is a working directory for fixing the reset problems that the Counter Chassis' MFB board is experiencing.  The code is sourced from pc_remote_bus rev 2.0, which I've just found to be working.  I've noticed that the "spurious interrupt" problem goes away by just reprogrammng the pc_remote_bus CPLD.  The existing reset scheme on all of the MFB"s CPLDs is pretty ineffective.  Software resets, 16'H9320, do nothing... although the pc_remote_sinewave CPLD will respond to 9220.  

First I'll modify the pc_remote_bus CPLD so that resets actually reset stuff.  As it stands almost no signals are actually reset with the reset input.

Anyway, since software sends 9320 at startup and shutdown, I'm trying to implement something to reset the pc_remote_bus CPLD when that 9320 command is received.

MikeT 8/12/03




the readme file from prev rev 2.0

This directory contains files that are for the remote MFB boards' (Counter and HVA Chassis) pc_remote_bus CPLD.  The VHDL source and pinout files were sourced from Redline under the directory:

/scr2/AO/H85_project/Electronics/Hardware/Mutifunction board bus Rob

The archive of design files was shifted over to jeans on the server Duke.  So the source files now reside on server Duke under the directory

/netdisks/shared.ifa/AO/H85_project/Electronics/Hardware/Mutifunction board bus Rob


The VHDL code has been modified to remove the delays programmed into the pc_remote_bus CPLD that were placed there for working with the slow National Instruments' DIO card.  With the new DIO card from Adlink these delays are not necessary.

Another change has been made to correct some differences between the H85 and NICI implementations (that we're currently developing) and the IRTF 36 element system.  In the current implementations the Counter and HVA boards are implemented in seperate chassis.  The old MFB code continued try to execute counter reads of the backplane in the HVA chassis.  They're not necessary and cause some clashes with the corrections being written to the HVA boards from the MFB.  SO, the VHDL code has been modified to look at an input pin to the chip from a DIP Switch on the MFB board.  This pin indicates whether the board is inserted into an HVA chassis or Counter chassis.  When configured for use in the HVA chassis, backplane reads are disabled to avoid the bus clash.

In addition I've cleaned up some of the random comments left around from the last couple years of design and degugging.


Mike Thompson  7/10/03