------------------------------------------------------------------------------- -- Revision history -- -- Date Rev Eng Description -- -------- --- -------------- ---------------------- -- 8/18/03 2.1 Mike Thompson Previously almost no signals were reset during -- power up reset. Here I've added all signals to -- the reset of all sequential logic including all -- entity outputs and internal signals, especially -- state registers. -- -- 8/4/03 2.0 Mike Thompson Removed delays in read_counters that were -- implemented for the National Instruments' -- DIO card. Added input from DIP switch pin 8 -- to chip input signal hva_chassis_en_l to -- stop backplane writes when configured as an -- HVA MFB in entity read_counters. See other -- notes below by searching on "mt". -- -- 3/20/03 1 PMO added counter reset at end of timeout -- Edited for 85 channel version -- r1 3/3/03 added 85 delay boundary for DIO ACK problem -- -- -- Signal naming conventions -- ON- chip signals are not preficed -- Upper part of the on-board bus signale preficed with iu_ -- Lower part of the on-board bus signals preficed with il_ -- Upper part of pc bus pu_ -- Lower part of pc bus pl_ -- Backplane bus bp_ -- fiber output fo_ -- fiber input fi_ --------------------------------------------------------------------------- -- -- take care of writing data to the onboard bus -- library ieee; use ieee.std_logic_1164.all; use work.numeric_std.all; entity write_to_ibus is port ( clk : in std_logic; reset : in std_logic; iu_req : out std_logic; iu_ack : in std_logic; iu_io : out std_logic_vector(15 downto 0); data : in std_logic_vector(15 downto 0); req : in std_logic; ack : out std_logic); end write_to_ibus; architecture write_to_ibus_arch of write_to_ibus is type iu_write_state is (idle,hs,iu_hs1,iu_hs2); signal iu_write : iu_write_state; signal timeout : unsigned(3 downto 0); begin -- write_to_ibus_arch iu_writer: process (clk, reset) begin -- process iu_writer if reset = '1' then -- asynchronous reset (active low) --mt rev2.1: Previously no signals were reset. All signals below added in this rev. iu_req <= '0'; iu_io <= (others => '0'); ack <= '0'; iu_write <= idle; timeout <= "0000"; elsif clk'event and clk = '1' then -- rising clock edge ack <= '0'; iu_req <= '0'; case iu_write is when idle => if (req = '1') then iu_io <= data; ack <= '1'; iu_write <= hs; timeout <= "0000"; end if; when hs => ack <= '1'; iu_req <= '1'; if (req = '0') then iu_write <= iu_hs1; timeout <= "0000"; else if (timeout = "1111") then iu_write <= iu_hs1; timeout <= "0000"; else timeout <= timeout+1; end if; end if; when iu_hs1 => iu_req <= '1'; if (iu_ack = '1') then iu_req <= '0'; iu_write <= iu_hs2; else if (timeout = "1111") then iu_write <= idle; else timeout <= timeout+1; end if; end if; when iu_hs2 => -- no timeout here because by this -- stage we know there is something -- at the other end if (iu_ack = '0') then iu_write <= idle; end if; when others => iu_write <= idle; end case; end if; end process iu_writer; end write_to_ibus_arch; library ieee; use ieee.std_logic_1164.all; use work.numeric_std.all; -- -- This block reads data from the on board bus when addressed. It captures and -- acts on command data and places other data or address info in the on -- chip buffers. -- Each transaction typically consists of two transfers, an address transfer -- followed by a data transfer. There are a few exceptions where only an -- address transfer is required, namelly a soft reset and switching to -- loopback mode. -- When the code detects an address transfer it check to see if it is being -- addressed. If it is then enables itself. Thie chip stays enabled untill -- another address transfer occurs. In this way the chip can accept follow -- up data transfers. -- entity read_from_ibus is port ( clk : in std_logic; reset : in std_logic; il_req : in std_logic; il_ack : out std_logic; il_io : in std_logic_vector(15 downto 0); data : buffer std_logic_vector(15 downto 0); address:buffer std_logic_vector(7 downto 0); req : out std_logic; ack : in std_logic; i_am_remote:in std_logic; my_data_address:in std_logic_vector(3 downto 0); my_ctrl_address:in std_logic_vector(3 downto 0); loopback_state:buffer std_logic; request_reset:out std_logic; counter_start:out unsigned(7 downto 0); counter_end:out unsigned(7 downto 0); il_i_am_addressed: buffer std_logic; dip_switch:in std_logic_vector(7 downto 0)); end read_from_ibus; architecture read_from_ibus_arch of read_from_ibus is type il_read_type is (idle,am_i_addressed,il_hs_for_address,il_hs_for_data, il_use_ctrl_data,internal_ack1,internal_ack2); signal il_read_state : il_read_type; signal timeout : unsigned(3 downto 0); --signal il_i_am_addressed : std_logic; signal this_is_a_ctrl_transaction : std_logic; begin -- read_from_ibus_arch -- purpose: read from the on-board bus -- type : sequential -- inputs : clk, reset -- outputs: read_ibus: process (clk, reset) begin -- process read_ibus if reset = '1' then -- asynchronous reset (active low) il_i_am_addressed <= '0'; this_is_a_ctrl_transaction <= '0'; loopback_state <= '0'; -- by default load counter counter_start <= "11111111"; counter_end <= "11111111"; --mt rev2.1: Added these signals below to reset. --Output signals il_ack <= '0'; data <= (others => '0'); address <= (others => '0'); req <= '0'; request_reset <= '0'; --Internal signals to this entity. il_read_state <= idle; timeout <= "0000"; elsif clk'event and clk = '1' then -- rising clock edge il_ack <= '0'; req <= '0'; request_reset <= '0'; case (il_read_state) is when idle => loopback_state <= '0'; -- disable loopback until things are working if (il_req = '1') then data <= il_io; il_read_state <= am_i_addressed; timeout <= "0000"; end if; when am_i_addressed => il_read_state <= idle; if (data(15) = '1') then -- this is an address il_i_am_addressed <= '0'; -- any addtress transaction should -- reset select bits on all chips this_is_a_ctrl_transaction <= '0'; if (data(12) = i_am_remote) then if (data(11 downto 8) = my_ctrl_address) then this_is_a_ctrl_transaction <= '1'; il_i_am_addressed <= '1'; -- loopback_state <= data(4); -- disable loopback until things are working request_reset <= data(5); address <= data(7 downto 0); il_read_state <= il_hs_for_address; end if; if (data(11 downto 8) = my_data_address) then il_i_am_addressed <= '1'; address <= data(7 downto 0); il_read_state <= il_hs_for_address; end if; end if; else -- -- This is not an address, but if this chip is already addressed -- then this will be a data transaction to complete the previous -- address transaction -- if (il_i_am_addressed = '1') then il_read_state <= il_hs_for_data; else il_read_state <= idle; end if; end if; when il_hs_for_address => il_ack <= '1'; if (il_req = '0') then -- -- Only do an ack cycle if we are in loopback mode -- if (loopback_state = '1') then il_read_state <= internal_ack1; else il_read_state <= idle; end if; else if (timeout = "1111") then -- Hmm this timeout will lead to a spurious transaction, but not -- to worry, there must be a serious problem somewhere else in -- this case il_read_state <= idle; else timeout <= timeout+1; end if; end if; when il_hs_for_data => il_ack <= '1'; if (il_req = '0') then -- -- things to do once the external transaction has completed -- if (this_is_a_ctrl_transaction = '1') then il_read_state <= il_use_ctrl_data; else il_read_state <= internal_ack1; timeout <= "0000"; end if; else if (timeout = "1111") then -- -- If this timeout is triggered we are likely to keep looping. -- By gong to an idle state we ensure that only 1 data transaction -- can take place anyway, thought there is a possibility of -- losing a transaction as well. -- il_read_state <= idle; else timeout <= timeout+1; end if; end if; if (this_is_a_ctrl_transaction = '0') then -- -- Get a jump start on completing internal transactions -- req <= '1'; -- attempt to transfer data out end if; when il_use_ctrl_data => -- -- What we do with the control data is completely dependent on the -- chip all of the rest of this code should be fairly generic, if -- a littl over elaborate in most cases -- if (address(1 downto 0) = "01") then c1: for i in 0 to 7 loop counter_start(i) <= data(i); counter_end(i) <= data(i+8); end loop c1; end if; -- Only do an ack if this is a loopback if (loopback_state = '1') then il_read_state <= internal_ack1; else il_read_state <= idle; end if; when internal_ack1 => req <= '1'; if (ack = '1') then timeout <= "0000"; req <= '0'; il_read_state <= internal_ack2; else if (timeout = "1111") then il_read_state <= idle; else timeout <= timeout+1; end if; end if; when internal_ack2 => req <= '0'; if (ack = '0') then il_read_state <= idle; else if (timeout = "1111") then il_read_state <= idle; else timeout <= timeout+1; end if; end if; when others => il_read_state <= idle; end case; end if; end process read_ibus; end read_from_ibus_arch; library ieee; use ieee.std_logic_1164.all; use work.numeric_std.all; entity backplane_io is port ( clk : in std_logic; reset : in std_logic; --broken_hva : in std_logic; bp_ctrl_bus : in std_logic_vector(15 downto 0); write_to_bp_addr : in std_logic_vector(7 downto 0); write_to_bp_req : in std_logic; write_to_bp_ack : out std_logic; bp_strobe : buffer std_logic; bp_data : in std_logic_vector(15 downto 0); read_from_bp_addr : in std_logic_vector(7 downto 0); read_from_bp_data : out std_logic_vector(14 downto 0); read_from_bp_req : in std_logic; read_from_bp_ack : out std_logic; bp_addr_tristate : out std_logic; bp_addr : out std_logic_vector(7 downto 0); bp_data_tristate : out std_logic; bp_data_direction_is_write: buffer std_logic; led1 : out std_logic); end backplane_io; architecture backplane_io of backplane_io is type bp_access_type is (idle, write_wait,write_settle,write_strobe,write_ack, read_from_bp,read_strobe,read_ack); signal bp_access_state : bp_access_type; signal timeout : unsigned(2 downto 0); signal propagation_delay : unsigned(2 downto 0); begin -- backplane_io -- purpose: Read and write data to the backplane. Since data is multiplexed, -- driving backplane through 1 process ensures no conflict can occur. -- type : sequential -- inputs : clk, reset -- outputs: -- propagation_delay <= "010"; -- about 80ns bp_access: process (clk, reset) begin -- process bp_access if reset = '1' then -- asynchronous reset (active low) --mt rev2.1: No signals were previously reset. All signals below added. --Output signals write_to_bp_ack <= '0'; bp_strobe <= '0'; read_from_bp_data <= (others => '0'); read_from_bp_ack <= '0'; bp_addr_tristate <= '1'; bp_addr <= (others => '0'); bp_data_tristate <= '1'; bp_data_direction_is_write <= '0'; led1 <= '1'; --Internal signals bp_access_state <= idle; timeout <= (others => '0'); elsif clk'event and clk = '1' then -- rising clock edge write_to_bp_ack <= '0'; read_from_bp_ack <= '0'; bp_data_direction_is_write <= '0'; -- default to zero since this implies -- lower power dissipation bp_data_tristate <= '1'; bp_strobe <= '0'; bp_addr_tristate <= '1'; led1 <= '1'; case (bp_access_state) is when idle => timeout <= (others => '0'); if (write_to_bp_req = '1') then bp_addr <= write_to_bp_addr; -- let outputs settle before enabling drivers --bp_data_tristate <= '0'; bp_data_direction_is_write <= '1'; bp_access_state <= write_wait; timeout <= (others => '0'); led1 <= '0'; --bp_addr_tristate <= '0'; else if (read_from_bp_req = '1') then bp_addr <= read_from_bp_addr; bp_data_tristate <= '0'; bp_access_state <= read_from_bp; --bp_addr_tristate <= '0'; end if; end if; when write_wait => -- -- This waitstate is needed to give the pld time to activate its output -- drive (which is done via the bp_data_direction_flag -- bp_data_direction_is_write <= '1'; bp_addr_tristate <= '0'; bp_access_state <= write_settle; when write_settle => led1 <= '0'; bp_data_direction_is_write <= '1'; bp_data_tristate <= '0'; bp_addr_tristate <= '0'; if (timeout = propagation_delay) then bp_access_state <= write_strobe; timeout <= "000"; else timeout <= timeout+1; end if; when write_strobe => led1 <= '0'; bp_data_direction_is_write <= '1'; bp_data_tristate <= '0'; bp_addr_tristate <= '0'; bp_strobe <= '1'; if (timeout = propagation_delay) then bp_access_state <= write_ack; write_to_bp_ack <= '1'; timeout <= (others => '0'); else timeout <= timeout+1; end if; when write_ack => led1 <= '0'; write_to_bp_ack <= '1'; if (write_to_bp_req = '0') then bp_access_state <= idle; else if (timeout = "111") then bp_access_state <= idle; else timeout <= timeout+1; end if; end if; when read_from_bp => bp_data_tristate <= '0'; bp_addr_tristate <= '0'; if (timeout = propagation_delay) then bp_access_state <= read_strobe; timeout <= timeout+1; else timeout <= timeout+1; end if; when read_strobe => bp_data_tristate <= '0'; bp_addr_tristate <= '0'; bp_strobe <= '1'; if (timeout = propagation_delay) then read_from_bp_data(14 downto 0) <= bp_data(14 downto 0); bp_access_state <= read_ack; read_from_bp_ack <= '1'; else timeout <= timeout+1; end if; when read_ack => read_from_bp_ack <= '1'; if (read_from_bp_req = '0') then bp_access_state <= idle; else if (timeout = "111") then bp_access_state <= idle; else timeout <= timeout+1; end if; end if; when others => bp_access_state <= idle; end case; end if; end process bp_access; end backplane_io; library ieee; use ieee.std_logic_1164.all; use work.numeric_std.all; -- -- Read the counter values on the backplane, taking into account that the -- counters are grouped in 24's so every 4 the 8 byte chunk is missing. -- entity read_counters is port ( clk : in std_logic; reset : in std_logic; phase : in std_logic; hva_chassis_en_l: in std_logic; --1=Counter MFB, 0=HVA MFB --dong data : buffer std_logic_vector(15 downto 0); not_phase : out std_logic; --mt rev2.1: Previously not_phase was a 16 bit output signal, data. But --only 1 bit was used in tout, the "not phase" bit. There was a clash --on the other 15 bits of the signal with the backplane_io output to --sensor_data. So i changed the read counter output to only 1 needed bit. req : out std_logic; ack : in std_logic; bp_address : out std_logic_vector(7 downto 0); bp_req : out std_logic; bp_ack : in std_logic; start_address :in unsigned(7 downto 0); end_address :in unsigned(7 downto 0); reset_counters :buffer std_logic); end read_counters; architecture read_counters_arch of read_counters is type counter_read_type is (idle,valid_address,increment_address,test_end, start_fetch,complete_fetch, transfer_to_pc,complete_pc_transfer, do_reset_counters); signal counter_read_state : counter_read_type; signal old_phase : std_logic; signal counter_address : unsigned(7 downto 0); signal reset_count : unsigned(2 downto 0); signal delay_count : unsigned(9 downto 0); begin -- read_counters_arch -- purpose: Take care of reading counter data from the backplane -- type : sequential -- inputs : clk, reset -- outputs: process (clk, reset) begin -- process if reset = '1' then -- asynchronous reset (active low) old_phase <= phase; --mt rev2.1: All signals below added to reset in this rev. --Output signals not_phase <= '0'; --TODO dong, here i've left the output signal, data, not reset. this should be --fixed... but i suspect it's teh source of the spurious interrupt problem --with rev 2.1 req <= '0'; bp_address <= (others => '0'); bp_req <= '0'; reset_counters <= '0'; --Internal signals counter_read_state <= idle; counter_address <= (others => '0'); reset_count <= (others => '0'); elsif clk'event and clk = '1' then -- rising clock edge bp_req <= '0'; req <= '0'; old_phase <= phase; reset_counters <= '0'; reset_count <= (others => '0'); --Counter read FSM case (counter_read_state) is when idle => --When the MFB that this pc_remote_bus CPLD resides on is configured as an --HVA MFB board with CPLD pin input hva_chassis_en_l='0' from the dipswitch switch pin --8, backplane reads are disabled. The backplane reads are only used in the --Counter Chassis implementation. This prevents bus clashes which we observed --in the lab's HVA chassis. Note that the value of the dip switch when ON is 0, --when OFF = 1. mt: rev 2.0 if(hva_chassis_en_l = '0') then counter_read_state <= idle; else if ((old_phase = not phase)) then -- Bus read triggered by change of phase. if (end_address = "00000000") then -- counter_read_state <= test_end; -- Special case (occurs after reset) which inhibits data read. -- else counter_address <= start_address; counter_read_state <= valid_address; delay_count <= "0000000000"; end if; end if; --end: if ((old_phase = not phase)) end if; --end: if(hva_chassis_en_l = '0') when valid_address => if (counter_address(4 downto 3) = "11") then -- This is not a valid address (only 24 counters per card) counter_read_state <= test_end; else counter_read_state <= start_fetch; for i in 0 to 7 loop bp_address(i) <= counter_address(i); end loop; -- i end if; when start_fetch => bp_req <= '1'; if (bp_ack = '1') then bp_req <= '0'; counter_read_state <= complete_fetch; -- -- Set most significant bit to phase -- --dong data(15) <= not phase; not_phase <= not phase; end if; when complete_fetch => req <= '1'; if (bp_ack = '0') then counter_read_state <= transfer_to_pc; end if; when transfer_to_pc => req <= '1'; if (ack = '1') then req <= '0'; counter_read_state <= complete_pc_transfer; end if; when complete_pc_transfer => if (ack = '0') then counter_read_state <= test_end; end if; when test_end => if (counter_address = end_address) then counter_read_state <= do_reset_counters; else --mt rev2.0: Originally there was a case statement here for inserting -- a delay after every 4'th packet sent to the Internal Bus. -- The delay was implemented by going to a state, "delay_packet" -- before moving to the "increment_address" state. This delay -- was removed for the H85, NICI system with the Adlink DIO board -- by jumping straight to the increment_address state from this state. counter_read_state <= increment_address; end if; --mt rev2.0: State "delay_packet" removed. Also see comment in test_end state. when increment_address => counter_address <= counter_address+1; counter_read_state <= valid_address; when do_reset_counters => reset_counters <= '1'; if (reset_count = "111") then reset_counters <= '0'; -- rev 1 added counter_read_state <= idle; else reset_count <= reset_count+1; end if; when others => counter_read_state <= idle; end case; end if; --clock'event end process; end read_counters_arch ; library ieee; use ieee.std_logic_1164.all; entity power_up is port (clk: in std_logic; fast : in std_logic; slow : in std_logic; led2: out std_logic; led3: out std_logic; reset: buffer std_logic ); end power_up; -- -- purpose: Handle graceful power-up, uses two RC filters on with -- A short time constant, one with a long time constant. May replace -- long time constant RC with counter driven by external oscillator. -- -- The main requirement is that the A/D reference buffers be shutdown -- until the negative power rail has had a chance to stabilise. -- architecture power_up_arch of power_up is begin -- power_up_arch led2 <= fast; led3 <= slow; -- -- Hold reset high during initial power up -- with (fast and (not slow)) select reset <= '1' when '1', '0' when '0', '0' when others; end power_up_arch; -- -- end of power up section -- library ieee; use ieee.std_logic_1164.all; use work.numeric_std.all; -- -- looks afte actual transactions on the data bus. -- entity tout is port (led1 : out std_logic; led2 : out std_logic; led3 : out std_logic; clk : in std_logic; fast : in std_logic; slow : in std_logic; -- -- on board data bus and associated control signals -- d: inout std_logic_vector(31 downto 0); -- -- global -- reset: buffer std_logic; -- Auxiliary interface --aux_bus_request: in std_logic; --aux_bus_grant: out std_logic; AO_FROM_PC_STROBE: buffer std_logic; AO_FROM_PC_ACK: buffer std_logic; AO_TO_PC_STROBE: out std_logic; AO_TO_PC_ACK: in std_logic; in_strobe: in std_logic; --periferal_ack: in std_logic; -- -- backplane data bus and associated control signale bpaddr : out std_logic_vector(7 downto 0); bpctrl : buffer std_logic_vector(15 downto 0); bpd : buffer std_logic_vector(15 downto 0); bpd_h_dir : out std_logic; bpd_h_tristate : out std_logic; bpd_l_dir : out std_logic; bpd_l_tristate : out std_logic; bpaddr_dir : out std_logic; bpaddr_tristate : out std_logic; bpctrl_h_dir : out std_logic; bpctrl_l_dir : out std_logic; bpctrl_h_tristate : out std_logic; bpctrl_l_tristate : out std_logic; sw : in std_logic_vector(7 downto 0); sinphase_zeros : in std_logic; hva_chassis_en_l : in std_logic --input to read_counters ); end tout; -- purpose: Collect together preceeding modules architecture tout_arch of tout is type tristate_state_type is (idle,active); signal tristate_state : tristate_state_type; signal bp_start_address : unsigned(7 downto 0); -- first counter address signal bp_end_address : unsigned(7 downto 0); -- last counter address signal il_tristate : std_logic; signal il_ack: std_logic; signal i_am_remote : std_logic; -- set to 1 for remote board 0 for local signal my_data_address : std_logic_vector(3 downto 0); signal my_ctrl_address : std_logic_vector(3 downto 0); signal from_pc_ack : std_logic; signal from_pc_req : std_logic; signal data_from_pc : std_logic_vector(15 downto 0); signal address_from_pc : std_logic_vector(7 downto 0); signal power_up_reset: std_logic; signal loopback_state: std_logic; signal soft_request_reset: std_logic; signal data_to_pc : std_logic_vector(15 downto 0); signal to_pc_ack : std_logic; signal to_pc_req : std_logic; signal this_chip_selected: std_logic; signal bp_data_tristate : std_logic; signal bp_addr_tristate: std_logic; signal sensor_address : std_logic_vector(7 downto 0); signal sensor_to_bp_read_req : std_logic; signal sensor_to_bp_read_ack : std_logic; signal sensor_to_ibus_req : std_logic; signal sensor_to_ibus_ack : std_logic; signal sensor_data: std_logic_vector(15 downto 0); signal write_to_bp_req: std_logic; signal write_to_bp_ack : std_logic; -- Note this is a dummy variable to ifdef the "broken HVA" in signal broken_hva_config : std_logic; alias bp_direction_is_write : std_logic is bpctrl(0); alias bp_phase : std_logic is bpctrl(1); alias bp_strobe : std_logic is bpctrl(2); alias bp_reset_counters : std_logic is bpctrl(3); -- -- use this alias when dealing with the newer HVA board -- -- alias backplane_data : std_logic_vector(15 downto 0) is bpd; -- -- use this alias when dealing with the broken HVA board. -- -- -- Following mods are needed when using the broken High voltege amplifier boards -- begin -- -- Following mods are needed for broken HVA board. -- broken_hva_config <= '0'; -- for newer board -- broken_hva_config <= '1'; -- for older board -- -- Static definitions -- i_am_remote <= '1'; my_data_address <= "0000"; my_ctrl_address <= "0001"; -- -- Use high control byte for outputs to attached periferals. -- Note that this is the only driver that must be permenantly -- switched on, since we cant let the strobe signals drift -- around. -- -- temporary initialisations that will be subsumed later -- -- -- permenant settings -- bpaddr_dir <= '0'; -- Permenantly set to output --bpaddr_tristate <= '0'; bpctrl_l_dir <= '0'; -- Permenently set to output bpctrl_l_tristate <= '0'; pup: power_up port map (clk,fast,slow,led2,led3,power_up_reset); reset <= power_up_reset; -- purpose: Takes care of tristating the internal lower bus ack line which is -- multi-driven by several chips. This is a clocked process because we wish to -- make sure that the ack signal is set to zero before the output is tristated. -- In this way the output holding latch always holds the line low in the -- absence of any logic drive. -- type : sequential -- inputs : clk, reset, process (clk, reset) begin -- process if reset = '1' then -- asynchronous reset (active low) --mt rev2.1: previously no signals were reset here. All signals below added --in this rev. --Internal signals tristate_state <= idle; il_tristate <= '1'; elsif clk'event and clk = '1' then -- rising clock edge case (tristate_state) is when idle => il_tristate <= '1'; if (this_chip_selected = '1') then il_tristate <= '0'; tristate_state <= active; end if; when active => if (this_chip_selected = '0') then il_tristate <= '0'; -- Lower output before tristating tristate_state <= idle; end if; when others => tristate_state <= idle; end case; end if; end process; AO_FROM_PC_ACK <= il_ack when (il_tristate = '0') else 'Z'; -- -- -- deal with signal routing depending on setting of loopback bit -- from_pc_ack <= to_pc_ack when (loopback_state = '1') else write_to_bp_ack; to_pc_req <= from_pc_req when (loopback_state = '1') else sensor_to_ibus_req; data_to_pc <= data_from_pc when (loopback_state = '1') else sensor_data; write_to_bp_req <= from_pc_req when (loopback_state = '0') else '0'; sensor_to_ibus_ack <= to_pc_ack when (loopback_state = '0') else '0'; ibus_writer : write_to_ibus port map ( clk => clk, reset => reset, iu_req => AO_TO_PC_STROBE, iu_ack => AO_TO_PC_ACK, data => data_to_pc, iu_io => d(31 downto 16), req => to_pc_req, ack => to_pc_ack); ibus_reader : read_from_ibus port map ( clk => clk, reset => reset, il_req => AO_FROM_PC_STROBE, il_ack => il_ack, il_io => d(15 downto 0), data => data_from_pc, address => address_from_pc, req => from_pc_req, ack => from_pc_ack, i_am_remote => i_am_remote, my_ctrl_address => my_ctrl_address, my_data_address => my_data_address, loopback_state => loopback_state, request_reset => soft_request_reset, counter_start => bp_start_address, counter_end => bp_end_address, il_i_am_addressed => this_chip_selected, dip_switch => sw); bp_io : backplane_io port map ( clk => clk, reset => reset, bp_ctrl_bus => bpctrl, write_to_bp_addr => address_from_pc, write_to_bp_req => write_to_bp_req, write_to_bp_ack => write_to_bp_ack, bp_strobe => bp_strobe, bp_data_direction_is_write => bp_direction_is_write, bp_data => bpd, --backplane_data, but don't believe it. read_from_bp_addr => sensor_address, read_from_bp_req => sensor_to_bp_read_req, read_from_bp_ack => sensor_to_bp_read_ack, --dong read_from_bp_data => sensor_data, read_from_bp_data => sensor_data(14 downto 0), bp_addr => bpaddr, bp_data_tristate => bp_data_tristate, bp_addr_tristate => bp_addr_tristate, led1 => led1); bpd_l_dir <= '0' when (bp_direction_is_write = '1') else '1'; bpd_h_dir <= '0' when (bp_direction_is_write = '1') else '1'; bpd_h_tristate <= bp_data_tristate; bpd_l_tristate <= bp_data_tristate; bpaddr_tristate <= bp_addr_tristate; bp_phase <= sinphase_zeros; -- -- -- -- Use this with the corrected HVA. -- -- -- --bpd <= data_from_pc when (bp_direction_is_write = '1') else (others => 'Z'); -- --bpctrl_h_tristate <= '1'; -- permanently disable -- -- -- end of correct HVA code -- -- -- Use this with the broken HVA -- bpctrl_h_dir <= '0'; -- Permenently set to output bpctrl_h_tristate <= bp_data_tristate; bpd(15 downto 10) <= data_from_pc(5 downto 0) when (bp_direction_is_write = '1') else (others =>'Z'); bpctrl(7 downto 4) <= data_from_pc(9 downto 6) when (bp_direction_is_write ='1') else (others =>'Z'); bpctrl(8) <= data_from_pc(10) when (bp_direction_is_write ='1') else 'Z'; bpctrl(11 downto 10) <= data_from_pc(12 downto 11) when (bp_direction_is_write ='1') else (others=>'Z'); sp_read : read_counters port map ( clk => clk, reset => reset, phase => sinphase_zeros, hva_chassis_en_l=> hva_chassis_en_l, --dong data => sensor_data, not_phase => sensor_data(15), req => sensor_to_ibus_req, ack => sensor_to_ibus_ack, bp_address => sensor_address, bp_req => sensor_to_bp_read_req, bp_ack => sensor_to_bp_read_ack, start_address => bp_start_address, end_address => bp_end_address, reset_counters => bp_reset_counters); end tout_arch;