0000: 80 3F JMP 0x0040 0002: 30 HALT 0003: 30 HALT FILE: .\boot.asm (0001) ;@Id: boot.tpl#6 @ (0002) ;============================================================================= (0003) ; FILENAME: boot.asm (0004) ; VERSION: 3.20 (0005) ; DATE: 10 October 2002 (0006) ; (0007) ; DESCRIPTION: (0008) ; M8C Boot Code from Reset. (0009) ; (0010) ; Copyright (C) Cypress MicroSystems 2001, 2002. All rights reserved. (0011) ; (0012) ; NOTES: (0013) ; PSoC Designer's Device Editor uses a template file, BOOT.TPL, located in (0014) ; the project's root directory to create BOOT.ASM. Any changes made to (0015) ; BOOT.ASM will be overwritten every time the project is generated; therfore (0016) ; changes should be made to BOOT.TPL not BOOT.ASM. Care must be taken when (0017) ; modifying BOOT.TPL so that replacement strings (such as @PROJECT_NAME) (0018) ; are not accidentally modified. (0019) ; (0020) ; The start of _main is at a fixed location so care must be taken when adding (0021) ; user code for any interrupts within boot.asm. If too much code is added,the (0022) ; end of BOOT.ASM will extend into _main and cause a linker error. The safest (0023) ; way to add code for an interrupt is to LCALL or LJMP to a normal routine (0024) ; located in a seperate file that contains the desired additional interrupt (0025) ; code. (0026) ;============================================================================= (0027) (0028) include ".\lib\psoc_defrost_GlobalParams.inc" (0029) include "m8c.inc" (0030) include "m8ssc.inc" (0031) (0032) ;----------------------------------------------------------------------------- (0033) ; Optimization flags (0034) ;----------------------------------------------------------------------------- (0035) (0036) C_LANGUAGE_SUPPORT: equ 1 ;Set to 0 to optimize for ASM only (0037) (0038) ;----------------------------------------------------------------------------- (0039) ; The following equate is required for proper operation. Reseting its value (0040) ; is discouraged. (0041) ;----------------------------------------------------------------------------- (0042) (0043) WAIT_FOR_32K: equ 1 ; Wait for Crystal to start before allowing main() (0044) ; Is effective only if the crystal oscillator is (0045) ; selected. If the designer choses to not WAIT, (0046) ; then the ECO and PLL_Lock process must be taken (0047) ; care of with user code. (0048) (0049) ;----------------------------------------------------------------------------- (0050) ; Export Declarations (0051) ;----------------------------------------------------------------------------- (0052) (0053) export __Start (0054) export __Exit (0055) export __bss_start (0056) (0057) export __lit_start (0058) export __idata_start (0059) export __data_start (0060) export __func_lit_start (0061) export __text_start (0062) (0063) (0064) ;----------------------------------------------------------------------------- (0065) ; Interrupt Vector Table (0066) ;----------------------------------------------------------------------------- (0067) ; (0068) ; Interrupt vector table entries are 4 bytes long and contain the code (0069) ; that services the interrupt (or causes it to be serviced). (0070) ; (0071) ;----------------------------------------------------------------------------- (0072) (0073) (0074) AREA TOP(ROM, ABS) (0075) (0076) org 0 ;Reset Interrupt Vector (0077) jmp __Start ;First instruction executed following a Reset (0078) (0079) org 04h ;Supply Monitor Interrupt Vector (0080) halt ;Stop execution if power falls too low 0004: 30 HALT (0081) reti 0005: 7E RETI 0006: 30 HALT 0007: 30 HALT (0082) (0083) org 08h ;PSoC Block DBA00 Interrupt Vector (0084) // call void_handler (0085) reti 0008: 7E RETI 0009: 30 HALT 000A: 30 HALT 000B: 30 HALT (0086) (0087) org 0Ch ;PSoC Block DBA01 Interrupt Vector (0088) // call void_handler (0089) reti 000C: 7E RETI 000D: 30 HALT 000E: 30 HALT 000F: 30 HALT (0090) (0091) org 10h ;PSoC Block DBA02 Interrupt Vector (0092) // call void_handler (0093) reti 0010: 7E RETI 0011: 30 HALT 0012: 30 HALT 0013: 30 HALT (0094) (0095) org 14h ;PSoC Block DBA03 Interrupt Vector (0096) ljmp Timer32_1INT 0014: 7D 02 72 LJMP Timer32_1INT (0097) reti 0017: 7E RETI (0098) (0099) org 18h ;PSoC Block DCA04 Interrupt Vector (0100) // call void_handler (0101) reti 0018: 7E RETI 0019: 30 HALT 001A: 30 HALT 001B: 30 HALT (0102) (0103) org 1Ch ;PSoC Block DCA05 Interrupt Vector (0104) // call void_handler (0105) reti 001C: 7E RETI 001D: 30 HALT 001E: 30 HALT 001F: 30 HALT (0106) (0107) org 20h ;PSoC Block DCA06 Interrupt Vector (0108) // call void_handler (0109) reti 0020: 7E RETI 0021: 30 HALT 0022: 30 HALT 0023: 30 HALT (0110) (0111) org 24h ;PSoC Block DCA07 Interrupt Vector (0112) // call void_handler (0113) reti 0024: 7E RETI 0025: 30 HALT 0026: 30 HALT 0027: 30 HALT (0114) (0115) org 28h ;Analog Column 0 Interrupt Vector (0116) // call void_handler (0117) reti 0028: 7E RETI 0029: 30 HALT 002A: 30 HALT 002B: 30 HALT (0118) (0119) org 2Ch ;Analog Column 1 Interrupt Vector (0120) // call void_handler (0121) reti 002C: 7E RETI 002D: 30 HALT 002E: 30 HALT 002F: 30 HALT (0122) (0123) org 30h ;Analog Column 2 Interrupt Vector (0124) // call void_handler (0125) reti 0030: 7E RETI 0031: 30 HALT 0032: 30 HALT 0033: 30 HALT (0126) (0127) org 34h ;Analog Column 3 Interrupt Vector (0128) // call void_handler (0129) reti 0034: 7E RETI 0035: 30 HALT 0036: 30 HALT 0037: 30 HALT (0130) (0131) org 38h ;GPIO Interrupt Vector (0132) // call void_handler (0133) reti 0038: 7E RETI 0039: 30 HALT 003A: 30 HALT 003B: 30 HALT (0134) (0135) org 3Ch ;Sleep Timer Interrupt Vector (0136) // call void_handler (0137) reti 003C: 7E RETI 003D: 30 HALT 003E: 30 HALT 003F: 30 HALT (0138) (0139) ;----------------------------------------------------------------------------- (0140) ; Start of Execution (0141) ; CPU is operating at 3 MHz, change to 12 MHz (0142) ; IO Bank is Bank0 (0143) ;----------------------------------------------------------------------------- (0144) org 40h (0145) __Start: (0146) mov [bSSC_KEY1] ,0 ;Lockout Flash and Supervisiory operations 0040: 55 F8 00 MOV [248],0 (0147) mov [bSSC_KEYSP],0 ;(especially after a Software Reset Supervisory op) 0043: 55 F9 00 MOV [249],0 (0148) (0149) mov A,__bss_end ;Set top of stack to end of used RAM 0046: 50 02 MOV A,2 (0150) IF (COMM_RX_PRESENT) (0151) cmp A,40h (0152) jnc .SetStack ; Stack must start at or above 40h (0153) mov A,40h (0154) ENDIF ;(COMM_RX_PRESENT) (0155) (0156) .SetStack: (0157) swap SP,A 0048: 4E SWAP SP,A (0158) (0159) ;------------------------------------------------------------------------- (0160) ; Set clock and BandGap trim if the operating voltage is 3.3V. On power (0161) ; up, 5V is loaded, so this is only needed for 3.3V operation. (0162) ;------------------------------------------------------------------------- (0163) (0164) IF (SUPPLY_VOLTAGE) ; 1 means 5.0V (0165) ELSE ; 0 means 3.3V (0166) mov [bSSC_TABLE_TableId], 1 ; Point to the Trim table (0167) SSC_Action TABLE_READ ; Perform a table read supervisor call (0168) M8C_SetBank1 (0169) mov A, [OSCILLATOR_TRIM_3V] (0170) mov reg[IMO_TR], A ; Load the 3V trim oscillator setting (0171) mov A, [VOLTAGE_TRIM_3V] (0172) mov reg[BDG_TR], A ; Load the bandgap trim setting for 3V (0173) M8C_SetBank0 (0174) ENDIF ;(SUPPLY_VOLTAGE) (0175) (0176) ;------------------------------------------------------------------------- (0177) ; If the user has requested the Crystal oscillator then turn it on and (0178) ; wait for it to stabilize and the system to switch over to it. The wait (0179) ; will be one sleep timer period, approximately 1 second. (0180) ;------------------------------------------------------------------------- (0181) (0182) IF (SELECT_32K & WAIT_FOR_32K) (0183) (0184) ; This will be used for XTAL and PLL startup, and is cancelled later on. (0185) mov reg[INT_MSK0], INT_MSK0_Sleep ; Only turn on Sleep interrupt (0186) mov reg[INT_MSK1], 0 ; Some could be on if s/w reset took place (0187) (0188) M8C_SetBank1 (0189) (0190) mov reg[PRT1DM0],00h ; P1[0] & P1[1] Drive Mode to High Z because (0191) mov reg[PRT1DM1],03h ; LoadConfigInit not run yet. (0192) IF (PLL_MODE) (0193) mov reg[ECO_TR],0Fh ; adjust ECO bias if in PLL lock mode (0194) ENDIF ;(PLL_MODE) (0195) M8C_SetBank0 (0196) M8C_ClearWDTAndSleep ; Reset the sleep timer (0197) (0198) M8C_SetBank1 (0199) mov reg[OSC_CR0], (OSC_CR0_Sleep_1Hz | SELECT_32K_JUST | OSC_CR0_CPU_12MHz) (0200) M8C_SetBank0 (0201) (0202) mov reg[INT_VC],0 ; Clear all pending interrupts (0203) .WaitFor1s: (0204) mov A, reg[INT_VC] ; read Interrupt Vector (0205) jz .WaitFor1s ; TimeOut occurs on Sleep Timer 1s (0206) (0207) M8C_SetBank1 (0208) mov reg[ILO_TR], 40h ; turn off the ILO, 32K is now from the ECO (0209) M8C_SetBank0 (0210) (0211) ELSE ;!(SELECT_32K & WAIT_FOR_32K) (0212) mov reg[INT_MSK0], 0 ; Turn off all interrupts 0049: 62 E0 00 MOV REG[224],0 (0213) mov reg[INT_MSK1], 0 ; some could be on if s/w reset took place 004C: 62 E1 00 MOV REG[225],0 (0214) M8C_SetBank1 004F: 71 10 OR F,16 (0215) mov reg[OSC_CR0], (OSC_CR0_Sleep_1Hz | OSC_CR0_CPU_12MHz) 0051: 62 E0 1A MOV REG[224],26 (0216) M8C_SetBank0 0054: 70 EF AND F,239 (0217) M8C_ClearWDTAndSleep ; Reset the sleep timer 0056: 62 E3 38 MOV REG[227],56 (0218) (0219) ENDIF ;(SELECT_32K & WAIT_FOR_32K) (0220) (0221) ;------------------------------------------------------------------------- (0222) ; Crystal is now fully operational. (0223) ;------------------------------------------------------------------------- (0224) (0225) IF (PLL_MODE) (0226) IF (SELECT_32K) (0227) M8C_SetBank1 (0228) mov reg[OSC_CR0], (PLL_MODE_JUST | OSC_CR0_Sleep_64Hz | SELECT_32K_JUST | OSC_CR0_CPU_12MHz) (0229) M8C_SetBank0 (0230) (0231) M8C_ClearWDTAndSleep ; Reset the sleep timer (0232) (0233) mov reg[INT_VC],0 ; Clear all pending interrupts (0234) .WaitFor16ms: (0235) mov A, reg[INT_VC] ; read Interrupt Vector (0236) jz .WaitFor16ms ; TimeOut occurs on Sleep Timer 16ms (0237) (0238) ELSE ;!(SELECT_32K) (0239) ERROR_PSoC Using the PLL without the Crystal is invalid. (0240) ENDIF ;(SELECT_32K) (0241) ENDIF ;(PLL_MODE) (0242) (0243) ;------------------------------------------------------------------------- (0244) ; default CT block RTopMux to OUT and RBotMux to AGND (0245) ;------------------------------------------------------------------------- (0246) (0247) mov reg[ACA00CR0],05h 0059: 62 71 05 MOV REG[113],5 (0248) mov reg[ACA01CR0],05h 005C: 62 75 05 MOV REG[117],5 (0249) mov reg[ACA02CR0],05h 005F: 62 79 05 MOV REG[121],5 (0250) mov reg[ACA03CR0],05h 0062: 62 7D 05 MOV REG[125],5 (0251) (0252) ;------------------------------------------------------------------------- (0253) ; All the user selections and UserModule selections are now loaded. (0254) ; !!! Except CPU frequency !!!! (CPU is runing at 12 MHz) (0255) ;------------------------------------------------------------------------- (0256) (0257) Config: (0258) lcall LoadConfigInit ; Configure PSoC blocks per Dev Editor 0065: 7C 01 90 LCALL 0x0190 (0259) (0260) (0261) IF (C_LANGUAGE_SUPPORT) (0262) call InitCRunTime ; Initialize for C language 0068: 90 22 CALL 0x008C (0263) ENDIF ;(C_LANGUAGE_SUPPORT) (0264) (0265) mov reg[INT_VC],0 ; Clear any pending interrupts which may 006A: 62 E2 00 MOV REG[226],0 (0266) ; have been set during the boot process. (0267) (0268) ;------------------------------------------------------------------------- (0269) ; We always enable LVD / Voltage Monitoring by default (0270) ;------------------------------------------------------------------------- (0271) (0272) M8C_EnableIntMask INT_MSK0, INT_MSK0_VoltageMonitor ; LVD only 006D: 43 E0 01 OR REG[224],1 (0273) (0274) IF (SWITCH_MODE_PUMP ^ 1) ; !!! This value is 1 if the SMP is disabled !!! (0275) ;------------------------------------------------------------------------- (0276) ; Pump is enabled, and customer requests it to work. Vcc is currently at (0277) ; or is slewing towards customer's requested Vcc. (0278) ;------------------------------------------------------------------------- (0279) (0280) IF (CPU_CLOCK_JUST ^ OSC_CR0_CPU_24MHz) ; Clock is not 24MHz (0281) ;------------------------------------------------------------------------- (0282) ; < 24 MHz operation is requested. Any reasonable Vcc is OK. (0283) ;------------------------------------------------------------------------- (0284) (0285) ELSE ;!(CPU_CLOCK_JUST ^ OSC_CR0_CPU_24MHz) (0286) ;------------------------------------------------------------------------- (0287) ; 24 MHz operation is requested. Requires 5V operation. (0288) ; Only 07h setting is valid (04h | 03h) (0289) ;------------------------------------------------------------------------- (0290) (0291) IF (SUPPLY_VOLTAGE) (0292) ;------------------------------------------------------------------------- (0293) ; 4.19 thru 5.0 V is selected (0294) ;------------------------------------------------------------------------- (0295) (0296) IF (TRIP_VOLTAGE ^ 07h) (0297) ERROR_PSoC TRIP_VOLTAGE must be 4.64V(5.00V) for 24 MHz operation (0298) (0299) ENDIF ;(TRIP_VOLTAGE ^ 07h) (0300) (0301) ELSE ;!(SUPPLY_VOLTAGE) (0302) ERROR_PSoC Only valid SMP setting is 5.0 V (0303) (0304) ENDIF ;(SUPPLY_VOLTAGE) (0305) ENDIF ;(CPU_CLOCK_JUST ^ OSC_CR0_CPU_24MHz) (0306) (0307) ;------------------------------------------------------------------------- (0308) ; But must wait for the SMP to slew from 3.1 to 5 Volts, if SMP selected. (0309) ;------------------------------------------------------------------------- (0310) M8C_EnableIntMask INT_MSK0, INT_MSK0_Sleep (0311) (0312) IF (SUPPLY_VOLTAGE) (0313) M8C_SetBank1 (0314) mov reg[OSC_CR0], OSC_CR0_Sleep_512Hz (0315) M8C_SetBank0 (0316) (0317) M8C_ClearWDTAndSleep ; Reset the sleep timer (0318) (0319) mov reg[INT_VC],0 ; Clear all pending interrupts (0320) .WaitFor2ms: (0321) mov A, reg[INT_VC] ; read Interrupt Vector (0322) jz .WaitFor2ms ; TimeOut occurs on Sleep Timer 2ms (0323) ENDIF ;(SUPPLY_VOLTAGE) (0324) (0325) ;------------------------------------------------------------------------- (0326) ; Vcc is Stable and Correct, at 5V range. Setup LVD for Brownout (0327) ;------------------------------------------------------------------------- (0328) (0329) M8C_EnableIntMask INT_MSK0, INT_MSK0_VoltageMonitor ; LVD only (0330) (0331) ELSE ;!(SWITCH_MODE_PUMP ^ 1) ; SMP is disabled (0332) ;------------------------------------------------------------------------- (0333) ; Normal operation with no pump. (0334) ;------------------------------------------------------------------------- (0335) (0336) M8C_EnableIntMask INT_MSK0, INT_MSK0_VoltageMonitor ; LVD only 0070: 43 E0 01 OR REG[224],1 (0337) (0338) IF (CPU_CLOCK_JUST ^ OSC_CR0_CPU_24MHz) (0339) ;------------------------------------------------------------------------- (0340) ; < 24 MHz operation is requested. Any reasonable Vcc is OK. (0341) ;------------------------------------------------------------------------- (0342) (0343) ELSE ;!(CPU_CLOCK_JUST ^ OSC_CR0_CPU_24MHz) (0344) ;------------------------------------------------------------------------- (0345) ; 24 MHz operation is requested. Requires 5V operation. (0346) ;------------------------------------------------------------------------- (0347) (0348) IF (SUPPLY_VOLTAGE) (0349) ; Set the CPU speed to 93.75kHz in order to slow down INT_VC read (0350) M8C_SetBank1 (0351) mov reg[OSC_CR0], (SELECT_32K_JUST | PLL_MODE_JUST | SLEEP_TIMER_JUST | OSC_CR0_CPU_93d7kHz) (0352) .LVDLoop: (0353) M8C_SetBank1 (0354) mov reg[VLT_CR], 00h ; LVD at 2.95 V (Power Good if >2.95V) (0355) M8C_SetBank0 (0356) mov reg[INT_VC],0 ; Clear LVD interrupt (0357) M8C_SetBank1 (0358) mov reg[VLT_CR], 07h ; Force LVD at 4.64 V (Power Not good if <4.64V) (0359) M8C_SetBank0 ; Must wait 10 usec before reading INT_VC (0360) mov A, reg[INT_VC] (0361) jz .GoodVcc (0362) jmp .LVDLoop ; Wait for good Vcc (0363) .GoodVcc: (0364) ;------------------------------------------------------------------------- (0365) ; Leave LVD at 4.64 V (Required, no exceptions) (0366) ;------------------------------------------------------------------------- (0367) (0368) ELSE ;!(SUPPLY_VOLTAGE) (0369) (0370) ERROR_PSoC 24 MHz at other than 5V is invalid. (0371) (0372) ENDIF ;(SUPPLY_VOLTAGE) (0373) ENDIF ;(CPU_CLOCK_JUST ^ OSC_CR0_CPU_24MHz) (0374) ENDIF ;(SWITCH_MODE_PUMP ^ 1) (0375) (0376) ;------------------------------------------------------------------------- (0377) ; Disable the Sleep interrupt that was used for timing above. (0378) ;------------------------------------------------------------------------- (0379) M8C_DisableIntMask INT_MSK0, INT_MSK0_Sleep 0073: 5D FF MOV A,REG[255] 0075: 70 FE AND F,254 0077: 41 E0 BF AND REG[224],191 007A: 21 80 AND A,128 007C: A0 03 JZ 0x0080 007E: 71 01 OR F,1 (0380) (0381) ;------------------------------------------------------------------------- (0382) ; Everything has started OK. Now select requested CPU & sleep frequency. (0383) ;------------------------------------------------------------------------- (0384) (0385) M8C_SetBank1 0080: 71 10 OR F,16 (0386) mov reg[OSC_CR0], (SELECT_32K_JUST | PLL_MODE_JUST | SLEEP_TIMER_JUST | CPU_CLOCK_JUST) 0082: 62 E0 00 MOV REG[224],0 (0387) M8C_SetBank0 0085: 70 EF AND F,239 (0388) (0389) ;------------------------------------------------------------------------- (0390) ; Global Interrupt are NOT enabled, this should be done in main(). (0391) ; LVD is set but will not occur unless Global Interrupts are enabled. (0392) ; Global Interrupts should be as soon as possible in main(). (0393) ;------------------------------------------------------------------------- (0394) (0395) lcall _main ; Call main 0087: 7C 01 F6 LCALL _main (0396) (0397) __Exit: (0398) jmp __Exit ; Wait here till power is turned off 008A: 8F FF JMP 0x008A (0399) (0400) (0401) (0402) ;----------------------------------------------------------------------------- (0403) ; C Runtime Environment Initialization (0404) ; The following code is conditionally assembled. (0405) ;----------------------------------------------------------------------------- (0406) (0407) IF (C_LANGUAGE_SUPPORT) (0408) (0409) InitCRunTime: (0410) ;----------------------------- (0411) ; clear bss segment (0412) ;----------------------------- (0413) mov A,0 008C: 50 00 MOV A,0 (0414) mov [__r0],<__bss_start 008E: 55 00 01 MOV [__r0],1 (0415) BssLoop: (0416) cmp [__r0],<__bss_end 0091: 3C 00 02 CMP [__r0],2 (0417) jz BssDone 0094: A0 05 JZ 0x009A (0418) mvi [__r0],A 0096: 3F 00 MVI [__r0],A (0419) jmp BssLoop 0098: 8F F8 JMP 0x0091 (0420) BssDone: (0421) ;---------------------------- (0422) ; copy idata to data segment (0423) ;---------------------------- (0424) mov A,>__idata_start 009A: 50 01 MOV A,1 (0425) mov X,<__idata_start 009C: 57 90 MOV X,144 (0426) mov [__r0],<__data_start 009E: 55 00 00 MOV [__r0],0 (0427) IDataLoop: (0428) cmp [__r0],<__data_end 00A1: 3C 00 00 CMP [__r0],0 (0429) jz IDataDone 00A4: A0 0B JZ 0x00B0 (0430) push A 00A6: 08 PUSH A (0431) romx 00A7: 28 ROMX (0432) mvi [__r0],A 00A8: 3F 00 MVI [__r0],A (0433) pop A 00AA: 18 POP A (0434) inc X 00AB: 75 INC X (0435) adc A,0 00AC: 09 00 ADC A,0 (0436) jmp IDataLoop 00AE: 8F F2 JMP 0x00A1 (0437) IDataDone: (0438) ret 00B0: 7F RET 00B1: 30 HALT 00B2: 30 HALT 00B3: 30 HALT 00B4: 30 HALT 00B5: 30 HALT 00B6: 30 HALT 00B7: 30 HALT 00B8: 30 HALT 00B9: 30 HALT 00BA: 30 HALT 00BB: 30 HALT 00BC: 30 HALT 00BD: 30 HALT 00BE: 30 HALT 00BF: 30 HALT 00C0: 30 HALT 00C1: 30 HALT 00C2: 30 HALT 00C3: 30 HALT 00C4: 30 HALT 00C5: 30 HALT 00C6: 30 HALT 00C7: 30 HALT 00C8: 30 HALT 00C9: 30 HALT 00CA: 30 HALT 00CB: 30 HALT 00CC: 30 HALT 00CD: 30 HALT 00CE: 30 HALT 00CF: 30 HALT 00D0: 30 HALT 00D1: 30 HALT 00D2: 30 HALT 00D3: 30 HALT 00D4: 30 HALT 00D5: 30 HALT 00D6: 30 HALT 00D7: 30 HALT 00D8: 30 HALT 00D9: 30 HALT 00DA: 30 HALT 00DB: 30 HALT 00DC: 30 HALT 00DD: 30 HALT 00DE: 30 HALT 00DF: 30 HALT 00E0: 30 HALT 00E1: 30 HALT 00E2: 30 HALT 00E3: 30 HALT 00E4: 30 HALT 00E5: 30 HALT 00E6: 30 HALT 00E7: 30 HALT 00E8: 30 HALT 00E9: 30 HALT 00EA: 30 HALT 00EB: 30 HALT 00EC: 30 HALT 00ED: 30 HALT 00EE: 30 HALT 00EF: 30 HALT 00F0: 30 HALT 00F1: 30 HALT 00F2: 30 HALT 00F3: 30 HALT 00F4: 30 HALT 00F5: 30 HALT 00F6: 30 HALT 00F7: 30 HALT 00F8: 30 HALT 00F9: 30 HALT 00FA: 30 HALT 00FB: 30 HALT 00FC: 30 HALT 00FD: 30 HALT 00FE: 30 HALT 00FF: 30 HALT 0100: 61 00 MOV REG[X+0],A 0102: 60 00 MOV REG[0],A 0104: 62 00 63 MOV REG[0],99 0107: 00 SSC 0108: E1 FF JACC 0x0308 010A: 00 SSC 010B: 00 SSC 010C: 01 00 ADD A,0 010E: 02 00 ADD A,[__r0] 0110: 03 00 ADD A,[X+0] 0112: 04 00 ADD [__r0],A 0114: 05 00 ADD [X+0],A 0116: 06 00 07 ADD [__r0],7 0119: 00 SSC 011A: 08 PUSH A 011B: 00 SSC 011C: 09 00 ADC A,0 011E: 0A 00 ADC A,[__r0] 0120: 0B 00 ADC A,[X+0] 0122: 0C 00 ADC [__r0],A 0124: 0D 00 ADC [X+0],A 0126: 0E 00 0F ADC [__r0],15 0129: 00 SSC 012A: 10 PUSH X 012B: 00 SSC 012C: 11 00 SUB A,0 012E: 12 00 SUB A,[__r0] 0130: 13 00 SUB A,[X+0] 0132: 14 00 SUB [__r0],A 0134: 15 00 SUB [X+0],A 0136: 16 00 17 SUB [__r0],23 0139: 00 SSC 013A: E3 07 JACC 0x0442 013C: 24 00 AND [__r0],A 013E: 25 36 AND [X+54],A 0140: 26 00 28 AND [__r0],40 0143: 00 SSC 0144: 29 36 OR A,54 0146: 2A 00 OR A,[__r0] 0148: 20 POP X 0149: 00 SSC 014A: 21 06 AND A,6 014C: 22 00 AND A,[__r0] 014E: 2C 20 OR [32],A 0150: 2D 36 OR [X+54],A 0152: 2E 00 FF OR [__r0],255 0155: 60 28 MOV REG[40],A 0157: 64 ASL A 0158: 00 SSC 0159: 63 05 65 MOV REG[X+5],101 015C: 00 SSC 015D: E6 00 JACC 0x075E 015F: 02 00 ADD A,[__r0] 0161: 01 00 ADD A,0 0163: 06 00 05 ADD [__r0],5 0166: 00 SSC 0167: 0A 00 ADC A,[__r0] 0169: 09 00 ADC A,0 016B: 0E 00 0D ADC [__r0],13 016E: 00 SSC 016F: 12 00 SUB A,[__r0] 0171: 11 00 SUB A,0 0173: 16 00 15 SUB [__r0],21 0176: 00 SSC 0177: 27 00 25 AND [X+0],37 017A: 00 SSC 017B: 26 00 2B AND [__r0],43 017E: 00 SSC 017F: 29 00 OR A,0 0181: 2A 00 OR A,[__r0] 0183: 23 00 AND A,[X+0] 0185: 21 00 AND A,0 0187: 22 00 AND A,[__r0] 0189: 2F 00 2D OR [X+0],45 018C: 00 SSC 018D: 2E 00 FF OR [__r0],255 FILE: lib\psocconfig.asm (0001) ; (0002) ; PSoCConfig.asm (0003) ; (0004) ; Version 0.84 (0005) ; Data: 19 December, 2000 (0006) ; Copyright Cypress MicroSystems 2000 (0007) ; (0008) ; This file is generated by the Device Editor on Application Generation. (0009) ; It contains code which loads the configuration data table generated in (0010) ; the file PSoCConfigTBL.asm (0011) ; (0012) ; DO NOT EDIT THIS FILE MANUALLY, AS IT IS OVERWRITTEN!!! (0013) ; Edits to this file will not be preserved. (0014) ; (0015) include "m8c.inc" (0016) (0017) export LoadConfigInit (0018) export _LoadConfigInit (0019) export LoadConfig_psoc_defrost (0020) export _LoadConfig_psoc_defrost (0021) (0022) export NO_SHADOW (0023) export _NO_SHADOW (0024) (0025) FLAG_CFG_MASK: equ 10h ;M8C flag register REG address bit mask (0026) END_CONFIG_TABLE: equ ffh ;end of config table indicator (0027) (0028) AREA psoc_config(rom, rel) (0029) (0030) _LoadConfigInit: (0031) LoadConfigInit: (0032) (0033) lcall LoadConfig_psoc_defrost 0190: 7C 01 94 LCALL 0x0194 (0034) (0035) ret 0193: 7F RET (0036) (0037) ; (0038) ; Load Configuration psoc_defrost (0039) ; (0040) _LoadConfig_psoc_defrost: (0041) LoadConfig_psoc_defrost: (0042) push a 0194: 08 PUSH A (0043) push x 0195: 10 PUSH X (0044) M8C_SetBank1 ;set for bank 1 0196: 71 10 OR F,16 (0045) mov a, 1 0198: 50 01 MOV A,1 (0046) asr a 019A: 67 ASR A (0047) mov A, >LoadConfigTBL_psoc_defrost_Bank1 ;load bank 1 table 019B: 50 01 MOV A,1 (0048) mov X, LoadConfigTBL_psoc_defrost_Bank0 ;load bank 0 table 01A7: 50 01 MOV A,1 (0054) mov X, X-7 024E: 10 PUSH X 024F: 4F MOV X,SP (0050) Timer32_1_WritePeriod(timer_value); 0250: 10 PUSH X 0251: 52 F9 MOV A,[X-7] 0253: 08 PUSH A 0254: 52 FA MOV A,[X-6] 0256: 08 PUSH A 0257: 52 FB MOV A,[X-5] 0259: 08 PUSH A 025A: 52 FC MOV A,[X-4] 025C: 08 PUSH A 025D: 4F MOV X,SP 025E: 79 DEC X 025F: 7C 02 92 LCALL _Timer32_1_WritePeriod 0262: 38 FC ADD SP,252 (0051) Timer32_1_Start(); 0264: 7C 02 8A LCALL Timer32_1_Start 0267: 20 POP X (0052) while (!done) 0268: 3C 01 00 CMP [_done],0 026B: AF FC JZ 0x0268 (0053) ; (0054) (0055) done = 0; 026D: 55 01 00 MOV [_done],0 (0056) } 0270: 20 POP X 0271: 7F RET FILE: lib\timer32_1int.asm (0001) ;------------------------------------------------------------------------------ (0002) ; FILENAME: Timer32_1int.asm (0003) ; VERSION: Rev B, 2002 Mar 30 (0004) ;------------------------------------------------------------------------------ (0005) ; DESCRIPTION: (0006) ; Interrupt handler routine for Timer32 user module instance: (0007) ; Timer32_1. (0008) ;------------------------------------------------------------------------------ (0009) ; Copyright (c) Cypress MicroSystems 2000-2002. All Rights Reserved. (0010) ;------------------------------------------------------------------------------ (0011) (0012) include "Timer32_1.inc" (0013) AREA bss(RAM) (0014) _done: BLK 1 (0015) (0016) AREA text(ROM) (0017) (0018) ;----------------------------------------------------- (0019) ; Export interrupt handler (0020) ; NOTE that interrupt handler is NOT exported (0021) ; for access by C function. Interrupt handlers (0022) ; are not callable by C functions. (0023) ;----------------------------------------------------- (0024) export _done (0025) export Timer32_1INT (0026) (0027) ;----------------------------------------------------------------------------- (0028) ; FUNCTION NAME: Timer32_1Int (0029) ; (0030) ; DESCRIPTION: (0031) ; Timer32 interrupt handler for instance Timer32_1. (0032) ; (0033) ; This is a place holder function. If the user requires use of an interrupt (0034) ; handler for this function, then place code where specified. (0035) ; (0036) ; ARGUMENTS: (0037) ; none. (0038) ; (0039) ; RETURNS: (0040) ; none. (0041) ; (0042) ; SIDE EFFECTS: (0043) ; none. (0044) ; (0045) ; THEORY of OPERATION: (0046) ; none. (0047) ; (0048) ;----------------------------------------------------------------------------- (0049) Timer32_1INT: (0050) mov [_done], 01h Timer32_1INT: 0272: 55 01 01 MOV [_done],1 (0051) call Timer32_1_Stop 0275: 90 17 CALL Timer32_1_Stop (0052) reti 0277: 7E RETI FILE: lib\timer32_1.asm (0001) ;------------------------------------------------------------------------------ (0002) ; FILENAME: Timer32_1.asm (0003) ; VERSION: Rev B, 2002 Mar 30 (0004) ;------------------------------------------------------------------------------ (0005) ; DESCRIPTION: (0006) ; Timer32_1 Timer32 User Module API. (0007) ; (0008) ;------------------------------------------------------------------------------ (0009) ; Copyright (c) Cypress MicroSystems 2000-2002. All Rights Reserved. (0010) ;------------------------------------------------------------------------------ (0011) (0012) ;----------------------------------------------- (0013) ; include instance specific register definitions (0014) ;----------------------------------------------- (0015) include "m8c.inc" (0016) include "Timer32_1.inc" (0017) (0018) area text (ROM, REL) (0019) (0020) ;------------------------------------------------------------------- (0021) ; Declare the functions global for both assembler and C compiler. (0022) ; (0023) ; Note that there are two names for each API. First name is (0024) ; assembler reference. Name with underscore is name refence for (0025) ; C compiler. Calling function in C source code does not require (0026) ; the underscore. (0027) ;------------------------------------------------------------------- (0028) export Timer32_1_EnableInt (0029) export _Timer32_1_EnableInt (0030) export Timer32_1_DisableInt (0031) export _Timer32_1_DisableInt (0032) export Timer32_1_Start (0033) export _Timer32_1_Start (0034) export Timer32_1_Stop (0035) export _Timer32_1_Stop (0036) export Timer32_1_WritePeriod (0037) export _Timer32_1_WritePeriod (0038) export Timer32_1_WriteCompareValue (0039) export _Timer32_1_WriteCompareValue (0040) export Timer32_1_ReadCompareValue (0041) export _Timer32_1_ReadCompareValue (0042) export Timer32_1_ReadTimerSaveCV (0043) export _Timer32_1_ReadTimerSaveCV (0044) export Timer32_1_ReadTimer (0045) export _Timer32_1_ReadTimer (0046) export Timer32_1_ReadCounter ; obsolete (0047) export _Timer32_1_ReadCounter ; obsolete (0048) export Timer32_1_CaptureCounter ; obsolete (0049) export _Timer32_1_CaptureCounter ; obsolete (0050) (0051) ;----------- (0052) ; EQUATES (0053) ;----------- (0054) bfCONTROL_REG_START_BIT: equ 1 ; Control register start bit (0055) (0056) ;----------------------------------------------------------------------------- (0057) ; FUNCTION NAME: Timer32_1_EnableInt (0058) ; (0059) ; DESCRIPTION: (0060) ; Enables this Timer's interrupt by setting the interrupt enable mask bit (0061) ; associated with this User Module. Remember to call the global interrupt (0062) ; enable function by using the macro: M8C_EnableGInt. (0063) ; (0064) ; ARGUMENTS: (0065) ; none. (0066) ; (0067) ; RETURNS: (0068) ; none. (0069) ; (0070) ; SIDE EFFECTS: (0071) ; none. (0072) ; (0073) ; THEORY of OPERATION: (0074) ; Sets the specific user module interrupt enable mask bit. (0075) ; (0076) ;----------------------------------------------------------------------------- (0077) Timer32_1_EnableInt: (0078) _Timer32_1_EnableInt: (0079) M8C_EnableIntMask Timer32_1_INT_REG, bTimer32_1_INT_MASK Timer32_1_EnableInt: _Timer32_1_EnableInt: 0278: 43 E1 08 OR REG[225],8 (0080) ret 027B: 7F RET (0081) (0082) (0083) ;----------------------------------------------------------------------------- (0084) ; FUNCTION NAME: Timer32_1_DisableInt (0085) ; (0086) ; DESCRIPTION: (0087) ; Disables this Timer's interrupt by clearing the interrupt enable mask bit (0088) ; associated with this User Module. (0089) ; (0090) ; ARGUMENTS: (0091) ; none. (0092) ; (0093) ; RETURNS: (0094) ; none. (0095) ; (0096) ; SIDE EFFECTS: (0097) ; none. (0098) ; (0099) ; THEORY of OPERATION: (0100) ; Clears the specific user module interrupt enable mask bit. (0101) ; (0102) ;----------------------------------------------------------------------------- (0103) Timer32_1_DisableInt: (0104) _Timer32_1_DisableInt: (0105) M8C_DisableIntMask Timer32_1_INT_REG, bTimer32_1_INT_MASK Timer32_1_DisableInt: _Timer32_1_DisableInt: 027C: 5D FF MOV A,REG[255] 027E: 70 FE AND F,254 0280: 41 E1 F7 AND REG[225],247 0283: 21 80 AND A,128 0285: A0 03 JZ 0x0289 0287: 71 01 OR F,1 (0106) ret 0289: 7F RET (0107) (0108) (0109) ;----------------------------------------------------------------------------- (0110) ; FUNCTION NAME: Timer32_1_Start (0111) ; (0112) ; DESCRIPTION: (0113) ; Sets the start bit in the Control register of this user module. The (0114) ; counter will begin counting on the next input clock as soon as the (0115) ; enable input is asserted high. (0116) ; (0117) ; ARGUMENTS: (0118) ; none. (0119) ; (0120) ; RETURNS: (0121) ; none. (0122) ; (0123) ; SIDE EFFECTS: (0124) ; none. (0125) ; (0126) ; THEORY of OPERATION: (0127) ; Set the start bit in the Control register of the LSB block. (0128) ; (0129) ;----------------------------------------------------------------------------- (0130) Timer32_1_Start: (0131) _Timer32_1_Start: (0132) or reg[Timer32_1_CONTROL_LSB_REG], bfCONTROL_REG_START_BIT Timer32_1_Start: _Timer32_1_Start: 028A: 43 23 01 OR REG[35],1 (0133) ret 028D: 7F RET (0134) (0135) (0136) ;----------------------------------------------------------------------------- (0137) ; FUNCTION NAME: Timer32_1_Stop (0138) ; (0139) ; DESCRIPTION: (0140) ; Disables Timer operation. (0141) ; (0142) ; ARGUMENTS: (0143) ; none. (0144) ; (0145) ; RETURNS: (0146) ; none. (0147) ; (0148) ; SIDE EFFECTS: (0149) ; After this function completes, the Counter register will latch any data (0150) ; written to the Period register. Writing to the Period register is (0151) ; performed using the Timer32_1_WritePeriod function. (0152) ; (0153) ; THEORY of OPERATION: (0154) ; Clear the start bit in the Control register of the LSB block. (0155) ; (0156) ;----------------------------------------------------------------------------- (0157) Timer32_1_Stop: (0158) _Timer32_1_Stop: (0159) and reg[Timer32_1_CONTROL_LSB_REG], ~bfCONTROL_REG_START_BIT Timer32_1_Stop: _Timer32_1_Stop: 028E: 41 23 FE AND REG[35],254 (0160) ret 0291: 7F RET (0161) (0162) (0163) ;----------------------------------------------------------------------------- (0164) ; FUNCTION NAME: Timer32_1_WritePeriod (0165) ; (0166) ; DESCRIPTION: (0167) ; Write the period value into the Period register. (0168) ; (0169) ; ARGUMENTS: (0170) ; DWORD dwPeriodValue - period count - (0171) ; X register points to 4 byte dword value (0172) ; Note that X points to MSB. (0173) ; (0174) ; RETURNS: (0175) ; none. (0176) ; (0177) ; SIDE EFFECTS: (0178) ; If the Timer user module is stopped, then this value will also be (0179) ; latched into the Counter registers. (0180) ; (0181) ; THEORY of OPERATION: (0182) ; Write data into the Period registers. (0183) ; (0184) ;----------------------------------------------------------------------------- (0185) _Timer32_1_WritePeriod: (0186) ;compensate for compiler (0187) mov A, X _Timer32_1_WritePeriod: 0292: 5B MOV A,X (0188) add A, -3 0293: 01 FD ADD A,253 (0189) mov X, A 0295: 5C MOV X,A (0190) (0191) Timer32_1_WritePeriod: (0192) tst reg[Timer32_1_CONTROL_LSB_REG], bfCONTROL_REG_START_BIT Timer32_1_WritePeriod: 0296: 49 23 01 TST REG[35],1 (0193) jnz .CounterRunning 0299: B0 36 JNZ 0x02D0 (0194) (0195) ; Counter is stopped. Due to chip errata, we have to set the clock low for (0196) ; the write to the period register to cause the data to be immediately transferred (0197) ; into the Counter. (0198) .CounterStopped: (0199) M8C_SetBank1 029B: 71 10 OR F,16 (0200) mov A, reg[Timer32_1_INPUT_LSB_REG] ; save the context of the clock - input register 029D: 5D 21 MOV A,REG[33] (0201) push A 029F: 08 PUSH A (0202) and reg[Timer32_1_INPUT_LSB_REG], F0h ; set the clock signal low 02A0: 41 21 F0 AND REG[33],240 (0203) and reg[Timer32_1_INPUT_ISB1_REG], F0h 02A3: 41 25 F0 AND REG[37],240 (0204) and reg[Timer32_1_INPUT_ISB2_REG], F0h 02A6: 41 29 F0 AND REG[41],240 (0205) and reg[Timer32_1_INPUT_MSB_REG], F0h 02A9: 41 2D F0 AND REG[45],240 (0206) M8C_SetBank0 02AC: 70 EF AND F,239 (0207) mov A, [X] ; load the period registers 02AE: 52 00 MOV A,[X+0] (0208) mov reg[Timer32_1_PERIOD_MSB_REG], A 02B0: 60 2D MOV REG[45],A (0209) mov A, [X+1] 02B2: 52 01 MOV A,[X+1] (0210) mov reg[Timer32_1_PERIOD_ISB2_REG], A 02B4: 60 29 MOV REG[41],A (0211) mov A, [X+2] 02B6: 52 02 MOV A,[X+2] (0212) mov reg[Timer32_1_PERIOD_ISB1_REG], A 02B8: 60 25 MOV REG[37],A (0213) mov A, [X+3] 02BA: 52 03 MOV A,[X+3] (0214) mov reg[Timer32_1_PERIOD_LSB_REG], A 02BC: 60 21 MOV REG[33],A (0215) pop A 02BE: 18 POP A (0216) M8C_SetBank1 02BF: 71 10 OR F,16 (0217) mov reg[Timer32_1_INPUT_LSB_REG], A ; restore the clock 02C1: 60 21 MOV REG[33],A (0218) and A, 0Fh ; High nibble is always 0x3 for higher order bits 02C3: 21 0F AND A,15 (0219) or A, 30h 02C5: 29 30 OR A,48 (0220) mov reg[Timer32_1_INPUT_ISB1_REG], A 02C7: 60 25 MOV REG[37],A (0221) mov reg[Timer32_1_INPUT_ISB2_REG], A 02C9: 60 29 MOV REG[41],A (0222) mov reg[Timer32_1_INPUT_MSB_REG], A 02CB: 60 2D MOV REG[45],A (0223) M8C_SetBank0 02CD: 70 EF AND F,239 (0224) ret 02CF: 7F RET (0225) (0226) ; Counter is running - write the period into the period register. (0227) ; Upon Terminal Count this value will get loaded into the counter. (0228) .CounterRunning: (0229) mov A, [X] 02D0: 52 00 MOV A,[X+0] (0230) mov reg[Timer32_1_PERIOD_MSB_REG], A 02D2: 60 2D MOV REG[45],A (0231) mov A, [X+1] 02D4: 52 01 MOV A,[X+1] (0232) mov reg[Timer32_1_PERIOD_ISB2_REG], A 02D6: 60 29 MOV REG[41],A (0233) mov A, [X+2] 02D8: 52 02 MOV A,[X+2] (0234) mov reg[Timer32_1_PERIOD_ISB1_REG], A 02DA: 60 25 MOV REG[37],A (0235) mov A, [X+3] 02DC: 52 03 MOV A,[X+3] (0236) mov reg[Timer32_1_PERIOD_LSB_REG], A 02DE: 60 21 MOV REG[33],A (0237) ret 02E0: 7F RET (0238) (0239) (0240) ;----------------------------------------------------------------------------- (0241) ; FUNCTION NAME: Timer32_1_WriteCompareValue (0242) ; (0243) ; DESCRIPTION: (0244) ; Writes compare value into the CompareValue register. (0245) ; (0246) ; NOTE! The Timer user module must be STOPPED in order to write (0247) ; the CompareValue register. (0248) ; (0249) ; ARGUMENTS: (0250) ; DWORD dwCompareValue - compare value count - (0251) ; X register points to 4 byte dword value (0252) ; Note that X points to MSB. (0253) ; (0254) ; RETURNS: (0255) ; none. (0256) ; (0257) ; SIDE EFFECTS: (0258) ; none. (0259) ; (0260) ; THEORY of OPERATION: (0261) ; Write data into the CompareValue registers. (0262) ; (0263) ;----------------------------------------------------------------------------- (0264) _Timer32_1_WriteCompareValue: (0265) ;compensate for compiler (0266) mov A, X _Timer32_1_WriteCompareValue: 02E1: 5B MOV A,X (0267) add A, -3 02E2: 01 FD ADD A,253 (0268) mov X, A 02E4: 5C MOV X,A (0269) Timer32_1_WriteCompareValue: (0270) mov A, [X] Timer32_1_WriteCompareValue: 02E5: 52 00 MOV A,[X+0] (0271) mov reg[Timer32_1_COMPARE_MSB_REG], A 02E7: 60 2E MOV REG[46],A (0272) mov A, [X+1] 02E9: 52 01 MOV A,[X+1] (0273) mov reg[Timer32_1_COMPARE_ISB2_REG], A 02EB: 60 2A MOV REG[42],A (0274) mov A, [X+2] 02ED: 52 02 MOV A,[X+2] (0275) mov reg[Timer32_1_COMPARE_ISB1_REG], A 02EF: 60 26 MOV REG[38],A (0276) mov A, [X+3] 02F1: 52 03 MOV A,[X+3] (0277) mov reg[Timer32_1_COMPARE_LSB_REG], A 02F3: 60 22 MOV REG[34],A (0278) ret 02F5: 7F RET (0279) (0280) (0281) ;----------------------------------------------------------------------------- (0282) ; FUNCTION NAME: dwTimer32_1_ReadCompareValue (0283) ; (0284) ; DESCRIPTION: (0285) ; Reads the CompareValue registers. (0286) ; (0287) ; DWORD * pdwCompareValue - a pointer to a DWORD buffer to put the compare value. (0288) ; The pointer is passed in the X register. (0289) ; X points to the MSB. (0290) ; (0291) ; RETURNS: (0292) ; The CompareValue is placed in the data buffer pointed to by pdwCompareValue as (0293) ; passed in the X register. (0294) ; (0295) ; SIDE EFFECTS: (0296) ; none. (0297) ; (0298) ; THEORY of OPERATION: (0299) ; Read the CompareValue register and return value in buffer pointed by (0300) ; X. (0301) ;----------------------------------------------------------------------------- (0302) Timer32_1_ReadCompareValue: (0303) _Timer32_1_ReadCompareValue: (0304) mov A, reg[Timer32_1_COMPARE_MSB_REG] Timer32_1_ReadCompareValue: _Timer32_1_ReadCompareValue: 02F6: 5D 2E MOV A,REG[46] (0305) mov [X], A 02F8: 54 00 MOV [X+0],A (0306) mov A, reg[Timer32_1_COMPARE_ISB2_REG] 02FA: 5D 2A MOV A,REG[42] (0307) mov [X+1], A 02FC: 54 01 MOV [X+1],A (0308) mov A, reg[Timer32_1_COMPARE_ISB1_REG] 02FE: 5D 26 MOV A,REG[38] (0309) mov [X+2], A 0300: 54 02 MOV [X+2],A (0310) mov A, reg[Timer32_1_COMPARE_LSB_REG] 0302: 5D 22 MOV A,REG[34] (0311) mov [X+3], A 0304: 54 03 MOV [X+3],A (0312) ret 0306: 7F RET (0313) (0314) (0315) ;----------------------------------------------------------------------------- (0316) ; FUNCTION NAME: Timer32_1_ReadTimerSaveCV (0317) ; (0318) ; DESCRIPTION: (0319) ; Reads the count in the Counter register. This function preserves the (0320) ; contents of the CompareValue register. However, the cost of doing so (0321) ; is that the counter is halted. This may cause the timer to miss one or (0322) ; more counts, depending on the speed of the input clock. (0323) ; (0324) ; ARGUMENTS: (0325) ; DWORD * pdwCount - a pointer to a DWORD buffer to put the counter value. (0326) ; The pointer is passed in the X register. (0327) ; X points to the MSB (0328) ; (0329) ; RETURNS: (0330) ; The read value is placed in the data buffer pointed to by pdwCount as (0331) ; passed in the X register. (0332) ; (0333) ; SIDE EFFECTS: (0334) ; 1) May cause an interrupt, if interrupt on CompareValue is enabled. (0335) ; 2) The user module is stopped momentarily while the compare value is (0336) ; restored. This may cause the Count register to miss one or more (0337) ; counts depending on the input clock speed. (0338) ; 3) Interrupts are momentarily disabled - this may cause other interrupt (0339) ; latency issues. (0340) ; (0341) ; THEORY of OPERATION: (0342) ; 1) Read and save the CompareValue register. (0343) ; 2) Read the Counter register, causing its data to be latched into (0344) ; the CompareValue register. (0345) ; 3) Read and save the Counter value, now in the CompareValue register, (0346) ; to the buffer. (0347) ; 4) Disable global interrupts (0348) ; 5) Halt the timer (0349) ; 6) Restore the CompareValue register values (0350) ; 7) Start the Counter again (0351) ; 8) Restore global interrupt state (0352) ; (0353) ;----------------------------------------------------------------------------- (0354) Timer32_1_ReadTimerSaveCV: (0355) _Timer32_1_ReadTimerSaveCV: (0356) Timer32_1_ReadCounter: ; obsolete (0357) _Timer32_1_ReadCounter: ; obsolete (0358) (0359) ; save the control register on the stack (0360) mov A, reg[Timer32_1_CONTROL_LSB_REG] _Timer32_1_ReadCounter: Timer32_1_ReadTimerSaveCV: _Timer32_1_ReadTimerSaveCV: Timer32_1_ReadCounter: 0307: 5D 23 MOV A,REG[35] (0361) push A 0309: 08 PUSH A (0362) (0363) ; save the CompareValue register value (0364) mov A, reg[Timer32_1_COMPARE_MSB_REG] 030A: 5D 2E MOV A,REG[46] (0365) push A 030C: 08 PUSH A (0366) mov A, reg[Timer32_1_COMPARE_ISB2_REG] 030D: 5D 2A MOV A,REG[42] (0367) push A 030F: 08 PUSH A (0368) mov A, reg[Timer32_1_COMPARE_ISB1_REG] 0310: 5D 26 MOV A,REG[38] (0369) push A 0312: 08 PUSH A (0370) mov A, reg[Timer32_1_COMPARE_LSB_REG] 0313: 5D 22 MOV A,REG[34] (0371) push A 0315: 08 PUSH A (0372) (0373) ; Read the LSB counter. This latches the counter data into the (0374) ; CompareValue register of all bytes of chained PSoC blocks! (0375) ; This may cause an interrupt. (0376) mov A, reg[Timer32_1_COUNTER_LSB_REG] 0316: 5D 20 MOV A,REG[32] (0377) (0378) ; Read the CompareValue register, which contains the counter value (0379) ; and store ther return result (0380) mov A, reg[Timer32_1_COMPARE_MSB_REG] 0318: 5D 2E MOV A,REG[46] (0381) mov [X], A 031A: 54 00 MOV [X+0],A (0382) mov A, reg[Timer32_1_COMPARE_ISB2_REG] 031C: 5D 2A MOV A,REG[42] (0383) mov [X+1], A 031E: 54 01 MOV [X+1],A (0384) mov A, reg[Timer32_1_COMPARE_ISB1_REG] 0320: 5D 26 MOV A,REG[38] (0385) mov [X+2], A 0322: 54 02 MOV [X+2],A (0386) mov A, reg[Timer32_1_COMPARE_LSB_REG] 0324: 5D 22 MOV A,REG[34] (0387) mov [X+3], A 0326: 54 03 MOV [X+3],A (0388) (0389) ; determine current interrupt state and save in X (0390) mov A, 0 0328: 50 00 MOV A,0 (0391) tst reg[CPU_SCR], CPUSCR_GIEMask 032A: 49 FF 80 TST REG[255],128 (0392) jz .SetupStatusFlag 032D: A0 03 JZ 0x0331 (0393) mov A, FlagGlobalIE 032F: 50 01 MOV A,1 (0394) .SetupStatusFlag: (0395) mov X, A 0331: 5C MOV X,A (0396) (0397) ; disable interrupts for the time being (0398) M8C_DisableGInt 0332: 70 FE AND F,254 (0399) (0400) ; stop the timer (0401) and reg[Timer32_1_CONTROL_LSB_REG], ~bfCONTROL_REG_START_BIT 0334: 41 23 FE AND REG[35],254 (0402) (0403) ; Restore the CompareValue register (0404) pop A 0337: 18 POP A (0405) mov reg[Timer32_1_COMPARE_LSB_REG], A 0338: 60 22 MOV REG[34],A (0406) pop A 033A: 18 POP A (0407) mov reg[Timer32_1_COMPARE_ISB1_REG], A 033B: 60 26 MOV REG[38],A (0408) pop A 033D: 18 POP A (0409) mov reg[Timer32_1_COMPARE_ISB2_REG], A 033E: 60 2A MOV REG[42],A (0410) pop A 0340: 18 POP A (0411) mov reg[Timer32_1_COMPARE_MSB_REG], A 0341: 60 2E MOV REG[46],A (0412) (0413) ; start the timer (0414) pop A 0343: 18 POP A (0415) mov reg[Timer32_1_CONTROL_LSB_REG], A 0344: 60 23 MOV REG[35],A (0416) (0417) ; put the flag register to restore on the stack (0418) push X 0346: 10 PUSH X (0419) (0420) ; Use RETI because it pops a the flag register off the stack (0421) ; and then returns to the caller. (0422) reti 0347: 7E RETI (0423) (0424) (0425) ;----------------------------------------------------------------------------- (0426) ; FUNCTION NAME: Timer32_1_ReadTimer (0427) ; (0428) ; DESCRIPTION: (0429) ; Performs a software capture of the Counter register. A synchronous (0430) ; read of the counter register is performed. The timer is NOT stopped. (0431) ; (0432) ; WARNING - this will cause loss of the CompareValue register data. (0433) ; (0434) ; ARGUMENTS: (0435) ; DWORD * pdwCount - a pointer to a DWORD buffer to put the counter value. (0436) ; The pointer is passed in the X register. (0437) ; X points to the MSB (0438) ; (0439) ; RETURNS: (0440) ; The read value is placed in the data buffer pointed to by pdwCount as (0441) ; passed in the X register. (0442) ; (0443) ; SIDE EFFECTS: (0444) ; May cause an interrupt. (0445) ; (0446) ; THEORY of OPERATION: (0447) ; 1) Read the CounterRegister - this causes the count value to be (0448) ; latched into the CompareValue registers. (0449) ; 2) Read and return the count register values from the CompareValue (0450) ; registers into the return buffer. (0451) ; (0452) ;----------------------------------------------------------------------------- (0453) Timer32_1_ReadTimer: (0454) _Timer32_1_ReadTimer: (0455) Timer32_1_CaptureCounter: ; obsolete (0456) _Timer32_1_CaptureCounter: ; obsolete (0457) (0458) ; Read the LSB counter. This latches the counter data into the (0459) ; CompareValue register of all bytes of chained PSoC blocks! (0460) ; This may cause an interrupt. (0461) mov A, reg[Timer32_1_COUNTER_LSB_REG] Timer32_1_ReadTimer: _Timer32_1_ReadTimer: Timer32_1_CaptureCounter: _Timer32_1_CaptureCounter: 0348: 5D 20 MOV A,REG[32] (0462) (0463) ; Read the CompareValue register, which contains the counter value (0464) ; and store ther return result (0465) mov A, reg[Timer32_1_COMPARE_MSB_REG] 034A: 5D 2E MOV A,REG[46] (0466) mov [X+0], A 034C: 54 00 MOV [X+0],A (0467) mov A, reg[Timer32_1_COMPARE_ISB2_REG] 034E: 5D 2A MOV A,REG[42] (0468) mov [X+1], A 0350: 54 01 MOV [X+1],A (0469) mov A, reg[Timer32_1_COMPARE_ISB1_REG] 0352: 5D 26 MOV A,REG[38] (0470) mov [X+2], A 0354: 54 02 MOV [X+2],A (0471) mov A, reg[Timer32_1_COMPARE_LSB_REG] 0356: 5D 22 MOV A,REG[34] (0472) mov [X+3], A 0358: 54 03 MOV [X+3],A (0473) (0474) ret FILE: 035A: 7F RET