/* -*- c-file-style: "Ellemtel" -*-
 * A COPY OF A SUBSET OF gpc/src-ppc405/u-boot/daq3u_apps/ce.h
 *
 */

#ifndef _INCLUDED_CE
#define _INCLUDED_CE 1

/* Definitions LUT parameter commands. */
#define  CE_PARAM_0             0x00000000
#define  CE_PARAM_1             0x00010000
#define  CE_PARAM_2             0x00020000
#define  CE_PARAM_3             0x00030000
#define  CE_PARAM_4             0x00040000
#define  CE_PARAM_5             0x00050000
#define  CE_PARAM_6             0x00060000
#define  CE_PARAM_7             0x00070000
#define  CE_PARAM_MASK          0x00070000

#define CE_LUT_1                0x00100000
#define CE_LUT_2                0x00200000
#define CE_LUT_3                0x00300000
#define CE_LUT_4                0x00400000
#define CE_LUT_5                0x00500000
#define CE_LUT_6                0x00600000
#define CE_LUT_7                0x00700000
#define CE_LUT_8                0x00800000
#define CE_LUT_9                0x00900000
#define CE_LUT_10               0x00A00000
#define CE_LUT_11               0x00B00000
#define CE_LUT_12               0x00C00000
#define CE_LUT_13               0x00D00000
#define CE_LUT_14               0x00E00000
#define CE_LUT_15               0x00F00000

/* Definition for non-LUT commands. */
#define CE_NON_LUT              0x08000000

#define CE_NON_LUT_WAIT_INT     0x00000000
#define CE_NON_LUT_CMD_INDEX    0x00010000
#define CE_NON_LUT_ADC          0x00020000

#define CE_PARAM_WRITE          0x80000000

/********************************************************************************
 *  FIFO commands. 
 */
#define CE_CMD_DELAY            0x00000001
#define CE_CMD_NOP              0x00000002
#define CE_CMD_PRMDACWR         0x00000004
#define CE_CMD_PRMDACVF         0x00000005
#define CE_CMD_AUXDACWR         0x00000006
#define CE_CMD_AUXDACVF         0x00000007
#define CE_CMD_UPDWR            0x00000008
#define CE_CMD_BPDOVWR          0x0000000C
#define CE_CMD_PARSEQ           0x00000014
#define CE_CMD_VIDSEQ           0x00000018
/*
 * Sync triggers, shutter.
 */
#define CE_CMD_NOTDONE1         0x00000025 /* Assert trig1 so others wait */
#define CE_CMD_NOTDONE2         0x00000029 /* Assert trig2 so others wait */
#define CE_CMD_WAITDONE1        0x00000024 /* Release trig1; wait for others */
#define CE_CMD_WAITDONE2        0x00000028 /* Release trig2; wait for others */
#define CE_CMD_WAIT_NOTEMPTY    0x0000002C
#define CE_CMD_SHUTTERCLOS      0x0000002E
#define CE_CMD_SHUTTEROPEN      0x0000002F

/********************************************************************************
 * FIFO parameter write commands. 
 */
#define CE_PARAM_PRMDACWR_LO    (CE_PARAM_WRITE | CE_LUT_1 | CE_PARAM_0)
#define CE_PARAM_PRMDACWR_HI    (CE_PARAM_WRITE | CE_LUT_1 | CE_PARAM_1)
#define CE_PARAM_PRMDACVF_LO    (CE_PARAM_WRITE | CE_LUT_1 | CE_PARAM_2)
#define CE_PARAM_PRMDACVF_HI    (CE_PARAM_WRITE | CE_LUT_1 | CE_PARAM_3)
#define CE_PARAM_AUXDACWR_LO    (CE_PARAM_WRITE | CE_LUT_1 | CE_PARAM_4)
#define CE_PARAM_AUXDACWR_HI    (CE_PARAM_WRITE | CE_LUT_1 | CE_PARAM_5)
#define CE_PARAM_AUXDACVF_LO    (CE_PARAM_WRITE | CE_LUT_1 | CE_PARAM_6)
#define CE_PARAM_AUXDACVF_HI    (CE_PARAM_WRITE | CE_LUT_1 | CE_PARAM_7)

#define CE_PARAM_UPDWR_LO       (CE_PARAM_WRITE | CE_LUT_2 | CE_PARAM_4)
#define CE_PARAM_UPDWR_HI       (CE_PARAM_WRITE | CE_LUT_2 | CE_PARAM_5)
#define CE_PARAM_UPDWR_DOE      (CE_PARAM_WRITE | CE_LUT_2 | CE_PARAM_5)
#define CE_PARAM_BPDOVWR        (CE_PARAM_WRITE | CE_LUT_2 | CE_PARAM_6)

#define CE_PARAM_PARSEQ_0       (CE_PARAM_WRITE | CE_LUT_4 | CE_PARAM_0)
#define CE_PARAM_PARSEQ_1       (CE_PARAM_WRITE | CE_LUT_4 | CE_PARAM_1)
#define CE_PARAM_PARSEQ_2       (CE_PARAM_WRITE | CE_LUT_4 | CE_PARAM_2)
#define CE_PARAM_PARSEQ_3       (CE_PARAM_WRITE | CE_LUT_4 | CE_PARAM_3)
#define CE_PARAM_PARSEQ_4       (CE_PARAM_WRITE | CE_LUT_4 | CE_PARAM_4)
#define CE_PARAM_PARSEQ_5       (CE_PARAM_WRITE | CE_LUT_4 | CE_PARAM_5)
#define CE_PARAM_PARSEQ_6       (CE_PARAM_WRITE | CE_LUT_4 | CE_PARAM_6)
#define CE_PARAM_PARSEQ_7       (CE_PARAM_WRITE | CE_LUT_4 | CE_PARAM_7)

#define CE_PARAM_VIDSEQ_PG3_0   (CE_PARAM_WRITE | CE_LUT_8 | CE_PARAM_0)
#define CE_PARAM_VIDSEQ_PG3_1   (CE_PARAM_WRITE | CE_LUT_8 | CE_PARAM_1)
#define CE_PARAM_VIDSEQ_PG3_2   (CE_PARAM_WRITE | CE_LUT_8 | CE_PARAM_2)
#define CE_PARAM_VIDSEQ_PG3_3   (CE_PARAM_WRITE | CE_LUT_8 | CE_PARAM_3)
#define CE_PARAM_VIDSEQ_PG3_4   (CE_PARAM_WRITE | CE_LUT_8 | CE_PARAM_4)
#define CE_PARAM_VIDSEQ_PG3_5   (CE_PARAM_WRITE | CE_LUT_8 | CE_PARAM_5)
#define CE_PARAM_VIDSEQ_PG3_6   (CE_PARAM_WRITE | CE_LUT_8 | CE_PARAM_6)
#define CE_PARAM_VIDSEQ_PG3_7   (CE_PARAM_WRITE | CE_LUT_8 | CE_PARAM_7)

#define CE_PARAM_VIDSEQ_PG4_0   (CE_PARAM_WRITE | CE_LUT_9 | CE_PARAM_0)
#define CE_PARAM_VIDSEQ_PG4_1   (CE_PARAM_WRITE | CE_LUT_9 | CE_PARAM_1)
#define CE_PARAM_VIDSEQ_PG4_2   (CE_PARAM_WRITE | CE_LUT_9 | CE_PARAM_2)
#define CE_PARAM_VIDSEQ_PG4_3   (CE_PARAM_WRITE | CE_LUT_9 | CE_PARAM_3)
#define CE_PARAM_VIDSEQ_PG4_4   (CE_PARAM_WRITE | CE_LUT_9 | CE_PARAM_4)
#define CE_PARAM_VIDSEQ_PG4_5   (CE_PARAM_WRITE | CE_LUT_9 | CE_PARAM_5)
#define CE_PARAM_VIDSEQ_PG4_6   (CE_PARAM_WRITE | CE_LUT_9 | CE_PARAM_6)
#define CE_PARAM_VIDSEQ_PG4_7   (CE_PARAM_WRITE | CE_LUT_9 | CE_PARAM_7)

/* These can be used to iterate across multiple related parameter commands,
 * e.g. the VIDSEQ and PARSEQ commands. Use them wisely - they'll correctly
 * manage the parameter as far as absolute min/max values, but they don't
 * know what the min/max are for a single set of commands. */
#define CE_PARAM_PREV(cmd) ((cmd & ~CE_PARAM_MASK) | ((cmd - CE_PARAM_1) & CE_PARAM_MASK))
#define CE_PARAM_NEXT(cmd) ((cmd & ~CE_PARAM_MASK) | ((cmd + CE_PARAM_1) & CE_PARAM_MASK))


/********************************************************************************
 * Global parameter commands. 
 */

#define CE_CMD_GLOBAL_WAIT_INT  (CE_PARAM_WRITE | CE_NON_LUT | CE_NON_LUT_WAIT_INT)
#define CE_CMD_GLOBAL_CMD_INDEX (CE_PARAM_WRITE | CE_NON_LUT | CE_NON_LUT_CMD_INDEX)
#define CE_PARAM_ADC       (CE_PARAM_WRITE | CE_NON_LUT | CE_NON_LUT_ADC)


/********************************************************************************
 * Data-related defines
 *
 * Masks are intended to be applied after 32-bit value is shifted right.
 */

/* 15-bit repetition count for all commands (do it 1 to 32768 times) */
#define CE_ITER_COUNT_MASK      0x7FFF
#define CE_ITER_COUNT_SHIFT     16
#define CE_ITER(n)              ((((n)-1)&CE_ITER_COUNT_MASK)<<CE_ITER_COUNT_SHIFT)

/* Parameter packing for TBD ADC global parameter command. */
#define CE_ADC_GAP_MASK         0xFF
#define CE_ADC_CHAN_MASK        0x03
#define CE_ADC_CHAN_SHIFT       8
#define CE_ADC_SAMP_MASK        0x3F
#define CE_ADC_SAMP_SHIFT       10

/********************************************************************************
 * OCM Interface
 *
 * Current designs include 16K of fast on-chip-memory which is
 * accessed almost as fast as cache memory to the PPC405, and can
 * be written directly by the HDL.  The HDL writes to OCM at an
 * offset programmed by the PowerPC, and a count programmed by
 * the PowerPC.  The count is in units of 32-bit words per amplifier,
 * and the HDL descrambles by amplifier to the extent possible
 * within count*8 (since we always read 8 amplifiers for now).
 *
 * The current settings will triple-buffer 8-amps within 16K.
 * This results in descrambled packets of 170 pixels or 680 bytes.
 * Two of these 680-byte chunks are accumulated per amplifier to
 * build a CATP packet with a payload of 1360 bytes intended to
 * go out in one ethernet packet.  The result is each ethernet
 * packet is nearly full, and contains only pixels from one amp.
 *
 * If 32K of OCM was available, we would probably get rid of this
 * split, and write only one OCM chunk into each ethernet packet.
 *
 * Jumbo packets and gigabit ethernet would require some adjustments
 * here to maintain the best efficiency.
 */
#define CE_OCM_SIZE 32768   /* vp20 max: 16384, vp30 max: 32768 */
#define CE_OCM_SKIP (00*1024) /* Amount of OCM at start to skip.
			       * This memory will not be touched,
			       * mainly for the case where stage1
			       * uses it and we don't want to corrupt
			       * stage1 in case of a powerpc reset.
			       *
			       * 12K is barely enough to skip the
			       * amount of (dev1) memory which stage1
			       * had been hijacking.
			       * %%% We need a "permanent" solution
			       * for getting stage1 to fit without
			       * stealing memory from clocking engine!
			       */
#define CE_OCM_AMP 8                        /* Number of amplifiers per OTA */
#define CE_OCM_MAX ((CE_OCM_SIZE-CE_OCM_SKIP)/CE_OCM_AMP/4/3) /* /4:sizeof(long), /3:triple-buffer */
#define CE_OCM_PIX ((CE_OCM_MAX/12)*12) /* Must be multiple of 6 because clockeng
				       * does not tolerate having to switch
				       * to a new OCM buffer in the middle
				       * of a 3-sample burst that can occur
				       * in RGB mode (or 2-sample in RG mode.)
				       * So to be divisible by 2 and 3, we
				       * round to the nearest multiple of 6.
				       */

/*
 * Math engine.
 *
 * See also: https://svn.ifa.hawaii.edu/gpc/wiki/ClockMath
 */
#define CE_MATH_CMD_SKIP    0x04 /* Skip sample */
#define CE_MATH_CMD_SENDOCM 0x0D /* Send sample directly to OCM */
#define CE_MATH_CMD_SUBACC1 0x10 /* Subtract sample from Accum1 */
#define CE_MATH_CMD_SUBACC2 0x11 /* Subtract sample from Accum2 */
#define CE_MATH_CMD_ADDACC1 0x12 /* Add sample to Accum1 */
#define CE_MATH_CMD_ADDACC2 0x13 /* Add sample to Accum2 */
#define CE_MATH_CMD_RSTACC1 0x16 /* Reset Accum1 to init_value */
#define CE_MATH_CMD_RSTACC2 0x17 /* Reset Accum2 to init_value */
#define CE_MATH_CMD_ACC1OCM 0x1E /* Reset Accum1 after sending value/divisor to OCM */
#define CE_MATH_CMD_ACC2OCM 0x1F /* Reset Accum2 after sending value/divisor to OCM */


/* Make some equivalents ce functions - so we can compile code on the linux host */

typedef struct 
{
   int dev;
} ce_t;

static inline void ce_put( ce_t* ce, unsigned long command)
{
}

static inline int ce_fifostatus_free(ce_t* ce)
{
   return 256;
}

static inline void ce_go(ce_t* ce, int run)
{
}
#endif /* !_INCLUDED_CE */