Bit Summary

The DSP communicates with the array electonics via a 32bits hardware register on it data bus. Individual bits in this word coorespond to control signals of the array & electonics. This file explains the relationship of the bits to the hardware.

1. The array (1024x1024) is really 4 512x512 devices. We need about 16 bits to  handle all the control signals. The 2 top quardants are tied together & the 2 bottom quardarts are tied together in hardware.

Bits 31-16 controls the top half of the array.
Bits 15- 0 controls the bottom half of the array.
The software actually output the same value on the top&bottom. Essentially all 4 quardant are mirror.

2. Bit definition Organization:

The file bdef.p is used to define the bits used by the cpat program.
The file bits  is used for labeling the postscript output. Refer to this file for dpat related output.
There are the bit definition from the bits files:

 00  B.vggcl
 01  B.vrowon
 02  B.vrstr
 03  B.vrstg
 04  B.read_data
 05  B.convert
 06  B.Frame
 07  B.phiSS
 08  B.vddcl
 09  B.phiS1
 10  B.phiS2
 11  B.phiSOE
 12  B.phiDES
 13  B.phiFS
 14  B.phiF1
 15  B.phiF2
 16  T.vggcl
 17  T.vrowon
 18  T.vrstr
 19  T.vrstg
 20  T.read_data
 21  T.convert
 22  undefined
 23  T.phiSS
 24  T.vddcl
 25  T.phiS1
 26  T.phiS2
 27  T.phiSOE
 28  T.phiDES
 29  T.phiFS
 30  T.phiF1
 31  T.phiF2
2. Bit definition organization by function. Just my note, refer to the SBRC user's guide for complete description.
 
 Slow Mux Clocks
 11. phiSOE - select Oodd/Even row.
 10. phiS2 - phase2 shift.
  9. phiS1 - phase1 shift.
  7. phiSS  - Used in P1, to initialize the slow shift register. the slow mux register.

 12. phiDES - Row disable function. (Not used in spex)
      To enable all rows turn on phiDES & phiFS.
      To disable a row pair - Turn on phiDES on while Addressing row.

 Fast Mux Clocks
 15. phiF2 - phase 2 shift.
 14. phiF1 - phase 1 shift.
 13. phiFS - Reset Fast shift registers.(spex did not use this). mux register.

 Bits for ROW resets
  2. vrstr  -  reset row (used in p4 to reset row-pair).
  1. vrowon - row on (used in p4 to reset row-pair).

 Bits global_resets
  0. vggcl -- used in global_reset() only.
  3. vrstg  - used in global_reset() only.
  8. vddcl - used in global_reset() only.

 IRTF bits.
  5.  Convert - commands an A/D sample.
  4.  Read_data - Commands Peter's boards to read A/D and put data in fifos.
        This must be (nword+2) cycle in length. On each clock pulue a
        32 bit value (2pixels) are placed in the fifo and 2. On the
        n-1 clock cycle the bcard DSP get notified data is available.
  6. Frame - used ??? (IRTF bit).


3. Other Important facts:

    vddcl is inverted logically.